Microcontrollers vs Microprocessors
Microprocessors Arbitrary computations Arbitrary control structures Arbitrary data structures Specify function at high-level and use compilers and debuggers Composed of three parts Data-path: data manipulation and storage Control: determines sequence of actions executed in data-path and interactions to be had with environment Interface: signals seen by the environment of the processor Instruction execution engine: fetch/execute cycle Flow of control determined by modifications to program counter Instruction classes: Data: move, arithmetic and logical operations Control: branch, loop, subroutine call Interface: load, store from external memory CSE 466 Microcontrollers 2
Microprocessor basics (cont d) Can implement arbitrary state machine with auxiliary data-path Control instructions implement state diagram Registers and ALUs act as data storage and manipulation Interaction with the environment through memory interface How are individual signal wires sensed and controlled? CSE 466 Microcontrollers 3
Microprocessor organization Controller Inputs: from ALU (conditions), instruction read from memory Outputs: select inputs for registers, ALU operations, read/write to memory Data-path Register file to hold data Arithmetic logic unit to manipulate data Program counter (to implement relative jumps and increments) Interface Data to/from memory (address and data registers in data path) Read/write signals to memory (from control) CSE 466 Microcontrollers 4
General-purpose processor Programmed by user New applications are developed routinely General-purpose Must handle a wide range of applications Interacts with environment through memory All devices communicate through memory data DMA operations between disk and I/O devices Dual-ported memory (e.g., display screen) Generally, oblivious to passage of time CSE 466 Microcontrollers 5
Microcontrollers (uc) Executes a single program (or a limited suite) with few parameters Task-specific Can be optimized for a specific application Interacts with environment in many ways Direct sensing and control of signal wires Communication protocols to environment and other devices Real-time interactions and constraints Power-saving modes of operation to conserve battery power Closer to system on chip much more integrated in same die / package Processor core + co-processors + memory Flash for program memory, RAM for data memory, special registers to interface to outside world ADC, sometimes DAC Parallel I/O ports to sense and control wires PWM (a simple form of DAC) Timer units to measure time in various ways Communication subsystems to permit direct links to other devices Increasingly, will see radios, MEMS sensors, in package with uc CSE 466 Microcontrollers 6
Microcontrollers (cont d) Other features not usually found in general-purpose CPUs Expanded interrupt handling capabilities Multiple interrupts with priority and selective enable/disable Automatic saving of context before handling interrupt Interrupt vectoring to quickly jump to handlers More instructions for bit manipulations Support operations on bits (signal wires) rather than just words Integrated memory and support functions for cheaper system cost Built-in Flash and RAM CSE 466 Microcontrollers 7
Typical general-purpose architecture CPU Memory Display (with dual-port video RAM) system bus I/O (serial line, keyboard, mouse) Disk Network Interface Sound Interface standard interfaces all the parts around the processor are usually required CSE 466 Microcontrollers 8
Typical task-specific architecture medium-speed interactions General Purpose I/O Microcontroller (CPU+mem+ ) A/D-D/A Conversion low-speed interactions Special I/O Device Driver Flash Timers RAM Custom Logic (now rare) high-speed interactions standard interface any of the parts around the microcontroller are optional CSE 466 Microcontrollers 9
How does this change things? Sense and control of environment Processor must be able to read and write individual wires Controls I/O interfaces directly Measurement of time Many applications require precise spacing of events in time Reaction times to external stimuli may be constrained Communication Protocols must be implemented by processor Integrate I/O device or emulate in software Capability of using external device when necessary CSE 466 Microcontrollers 10
Block diagram of processor (Harvard) Register transfer view of Harvard architecture Separate busses for instruction memory and data memory Example: PIC 16 load path OP REG AC 16 16 store path rd wr data Data Memory (16-bit words) N Z 16 addr Control FSM 16 OP IR PC 16 16 data Inst Memory (8-bit words) addr 16 CSE 466 Microcontrollers 11
Block diagram of processor (Princeton) Register transfer view of Princeton / von Neumann architecture Single unified bus for instructions, data, and I/O Example: MSP430 16 load path OP REG 16 AC 16 store path rd wr data Data Memory (16-bit words) Control FSM N Z 16 IR 16 8 PC 16 addr MAR Memory Address Register OP 16 CSE 466 Microcontrollers 12
The MSP430: Introduction
MSP430: An Introduction The MSP430 family Technology Roadmap Typical Applications The MSP430 Documentation MSP430 Architecture MSP430 Devices MSP430 RISC core CSE 466 Microcontrollers 14
The Family Broad family of TI s 16-bit microcontrollers from 1Kbytes ROM, 128 bytes RAM (approx. $1 ) to 256Kbytes ROM, 16Kbytes RAM ( $10) Many subfamilies MSP430x1xx: Flash/ ROM based MCUs offer 1.8V to 3.6V operation, up to 60kB, 8MIPs with Basic Clock. MSP430F2xx: 16 MHz. integrated on-chip oscillator, internal pullup/pull-down resistors MSP430x4xx: 120kB/ Flash/ ROM 8MIPS with FLL + SVS, integrated LCD controller MSP430x5xx: 25 MIPS, 1.8 to 3.6V, Power Management Module for optimizing power consumption, 2x memory CSE 466 Microcontrollers 15
Part numbering convention CSE 466 Microcontrollers 16
MSP430 Roadmap Performance Device Production Sampling Development Future F20xx 1xx-Catalog 8 MIPS 1-60KB F21x1 F22xx F261x F241x F23x-F24x F23x0 F/C41x 5xx-Next Gen 25 MIPS 32-256 KB USB-RF F21x2 F15x-F16x F13x-F14x F12xx F/C11xx Fx42x0 Integration Fx42x F44x F5xx F563x USB F543x F5xx RF F471x7 2xx-Catalog 16 MIPS 1-120KB 500nA Stand By CG461x Fx43x FG461x F47x4 4xx-LCD 8/16 MIPS 4-120KB LCD Driver F = Flash C = Custom ROM
MSP430 Typical Applications Handheld Measurement Air Flow measurement Alcohol meter Barometer Data loggers Emission/Gas analyser Humidity measurement Temperature measurement Weight scales Medical Instruments Blood pressure meter Blood sugar meter Breath measurement EKG system Utility Metering Gas Meter Water Meter Heat Volume Counter Heat Cost Allocation Electricity Meter Home environment Air conditioning Control unit Thermostat Boiler control Shutter control Meter reading system (RF) Irrigation system White goods (Washing machine,..) Sports equipment Altimeter Bike computer Diving watches Security Glass break sensors Door control Smoke/fire/gas detectors Misc Smart card reader Taxi meter Smart Batteries CSE 466 Microcontrollers 18
MSP430 modes of operation Active mode (AM) All clocks are active Low-power mode 0 (LPM0) CPU is disabled MCLK is disabled Low-power mode 1 (LPM1) DCO's dc-generator is disabled if DCO not used in active mode Low-power mode 2 (LPM2) SMCLK disabled DCO's dc-generator remains enabled Low-power mode 3 (LPM3) DCO's dc-generator is disabled Low-power mode 4 (LPM4) ACLK is disabled Crystal oscillator is stopped CSE 466 Microcontrollers 19
MSP 430 Modular Architecture CSE 466 Microcontrollers 20
JTAG Joint Test Action Group (originally created standard) Now IEEE1149.1 4 or 5 wire debugging / test interface MSP430 uses JTAG as primary development interface & for test Writing Flash Debugger JTAG: serial sequence of commands and responses Emulation tool translates ops from host into a sequence of JTAG commands TAP: Test Access Port http://i.cmpnet.com/embedded//2009/0109_jan%202009/0109esdti01.gif Good article on JTAG & Spi-Bi-Wire http://www.embedded.com/design/prototyping-and-development/4008197/mcu-debug-on-a-pin-count-budget CSE 466 Microcontrollers 21
Spy-Bi-Wire Goal: JTAG functionality with only 2 wires Re-use existing JTAG blocks Serialized JTAG SBWTIDO shared with reset pin /RST SBWTCK must be held low for a while to enable /RST http://i.cmpnet.com/embedded//2009/0109_jan%202009/0109esdti03.gif CSE 466 Microcontrollers 22
Embedded Emulation Real-time in-system debug No application resources used Full speed execution H/W breakpoints Single stepping Complex triggering Trace capability Easy to use tools Spy Bi-Wire 2-wire debug interface No pin function impact JTAG
Embedded Emulation Module (EEM) MSP430 implements an embedded emulation module (EEM) accessed and controlled through JTAG. In general (varies by MSP430 part #), the following features are available: Non intrusive code execution with real time breakpoint control Single step, step into and step over functionality Full support of all low-power modes Support for all system frequencies, for all clock sources Up to eight (device dependent) hardware triggers/breakpoints on memory address bus (MAB) or memory data bus (MDB) Up to two (device dependent) hardware triggers/breakpoints on CPU register write accesses CSE 466 Microcontrollers 24
USB Flash Emulation Tool (FET) MSP430 FET: real-time debug and programming tool Supports ALL MSP430 devices 4-wire JTAG 2-wire Spy Bi-Wire Available with socketed target board Example: MSP-FET430U14 = FET Interface + 14-pin target board Supported by all MSP430 IDEs
ez430-f2013 Development Tool Complete development tool that fits in your pocket Supports MSP430F20xx devices only MSP430F20xx devices available in DIP Unrestricted programming and debugging Fast, easy to use operation Includes IAR Kickstart IDE Supported by CCE V2 $20
Digital I/O Independently programmable individual I/Os Port1 Port2 Port3 Port6 Function Select Register PxSEL yes yes Up to 6 ports (P1 P6) Each has 8 I/O pins Each pin can be configured as input or output P1. P2. P3. 7 Interrupt Edge Select Register PxIES Interrupt Enable Register PxIE Interrupt Flag Register PxIFG Direction Register PxDIR Output Register PxOUT Input Register PxIN 6 5 4 3 2 1 0 yes yes yes yes yes yes no no no yes yes yes P1 and P2 pins can be configured to assert an interrupt request P4. P5. P6. CSE 466 Microcontrollers 27
Watchdog Timer WDT module performs a controlled system restart after a software problem occurs Can serve as an interval timer (generates interrupts) WDT Control register is password protected Note: Powers-up active CSE 466 Microcontrollers 28
Example 1: msp430x20x3_1.c // MSP430F20xx Demo - Software Toggle P1.0 #include <msp430x20x3.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer P1DIR = 0x01; // Set P1.0 to output direction for (;;) { volatile unsigned int i; P1OUT ^= 0x01; // Toggle P1.0 using XOR i = 50000; // Delay do (i--); while (i!= 0); } } WDTCTL: Watch Dog Timer ConTroL WDTPW: WDT PassWord WTDHOLD: WDT Hold P1DIR: Port 1 DIRection P1OUT: Port 1 OUTput state CSE 466 Microcontrollers 29
Example 2: msp430x20x3p1_01.c // MSP430F20xx Demo - Software Poll P1.4, Set P1.0 if P1.4 = 1 // Desc: Poll P1.4 in a loop, if hi P1.0 is set, if low, P1.0 reset. // ACLK = n/a, MCLK = SMCLK = default DCO #include <msp430x20x3.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer P1DIR = 0x01; // Set P1.0 to output direction while (1) // Test P1.4 { if ((0x10 & P1IN)) P1OUT = 0x01;// if P1.4 set, set P1.0 else P1OUT &= ~0x01; // else reset } } CSE 466 Microcontrollers 30
MSP430 Memory Model Not present in F2013 SFR: Special Function Registers CSE 466 Microcontrollers 31
Memory Organization CSE 466 Microcontrollers 32
End of lecture CSE 466 Microcontrollers 33
Recall from last time Example 2: msp430x20x3p1_01.c // MSP430F20xx Demo - Software Poll P1.4, Set P1.0 if P1.4 = 1 // Desc: Poll P1.4 in a loop, if hi P1.0 is set, if low, P1.0 reset. // ACLK = n/a, MCLK = SMCLK = default DCO #include <msp430x20x3.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer P1DIR = 0x01; // Set P1.0 to output direction while (1) // Test P1.4 { if ((0x10 & P1IN)) P1OUT = 0x01;// if P1.4 set, set P1.0 else P1OUT &= ~0x01; // else reset } } CSE 466 Microcontrollers 34
Questions about example 2 Q: Why does (0x10 & P1IN) test P1.4? A: 0x10 is hexadecimal notation for 16: 0x10 = 1*16 1 + 0*16 0 = 16 (base 10) Converting hex to binary is easy, that s why hex is useful in embedded systems: each hex digit maps straight onto 4 bits: The 1 (high digit) becomes 0001 The 0 (low digit) becomes 0000 Concatenating, we get 0x10 = 00010000 b In the binary representation, bit 4 (counting from 0) is high This mask is how you select only pin 4 of port 1 Note: MSP430 header files define constants BIT0, BIT1, etc: BIT0 = 00000001b = 1 in base 10 BIT1 = 00000010b = 2 in base 10 BIT2 = 00000100b = 4 in base 10 etc CSE 466 Microcontrollers 35
Question about example 2 Q: Why use this ORing notation P1OUT = 0x01 to set the low bit of P1, instead of just P1OUT = 0x01? A: By ORing the value in, we don t modify any of the other bits of P1 there may be other pieces of code that want other bits of P1 to be in a certain state Discuss: what s the analogous technique to CLEAR a single bit, leaving the other bits unchanged? CSE 466 Microcontrollers 36
MSP 430 Architecture: A Closer Look CSE 466 Microcontrollers 37
F2013-specific peripherals Ports P1 (8 bit port) and 2 bits of P2 Any pin can function as input or output, and generate an interrupt Individually programmable pull up & pull down resistors for each pin Clock: the usual, plus VLO (Very Low frequency Oscillator) Timer_A2 Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. USI (MSP430F20x2 and MSP430F20x3) The universal serial interface (USI) module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C. SD16_A (MSP430F20x3) The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit sigma-delta core and reference generator. In addition to external analog inputs, internal VCC sense and temperature sensors are also available. CSE 466 Microcontrollers 38
Basic Clock System Basic Clock Module provides the clocks for the MSP430 devices VLO (in MSP430F2xx): 4-20kHz CSE 466 Subsystem Master CLocK Microcontrollers 39
Wake up time DCO frequency DCO takes constant number of periods to wake up? CSE 466 Microcontrollers 40
Timer_A TASSEL---Timer A Source SELect SMCLK, ACLK, 2 external sources ID --- Input divider /1 /2 /4 /8 MC---Mode Control Continuous Up Down Up/Down TACLR --- Timer A CLeaR TAIE --- Timer A Interrupt Enable TAIFG --- Timer A Interrupt Flag CSE 466 Microcontrollers 41
Timer_A Also, Continuous mode (which requires a new Compare value to be set in ISR) CSE 466 Microcontrollers 42
Timer_A F2013 has Timer_A2 2 CCR channels TAR Timer A Register 16 bit counter TASSEL Timer A Source SELect TAIFG Timer A Interrupt FlaG raised when counter = 0 TACCRn TA Capture Compare Register Capture: when event occurs, record TAR value in TACCR1 Circles: signals that can be made external Compare: generate event when TAR=TACCR1 CSE 466 Microcontrollers 43
Timer_A Timer_A is a 16-bit timer/counter with multiple capture/compare registers (2 in F2013) Capture external signals Compare PWM mode CSE 466 Microcontrollers 44
Example 3: msp430x20x3_ta_01.c // MSP430F20xx Demo - Timer_A, Toggle P1.0, CCR0 Cont. Mode ISR, DCO SMCLK // Description: Toggle P1.0 using software and TA_0 ISR. Toggles every // 50000 SMCLK cycles. SMCLK provides clock source for TACLK. // During the TA_0 ISR, P1.0 is toggled and 50000 clock cycles are added to // CCR0. TA_0 ISR is triggered every 50000 cycles. CPU is normally off and // used only during TA_ISR. // ACLK = n/a, MCLK = SMCLK = TACLK = default DCO #include <msp430x20x3.h> void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR = 0x01; // P1.0 output CCTL0 = CCIE; // CCR0 interrupt enabled CCR0 = 50000; TACTL = TASSEL_2 + MC_2; // SMCLK, contmode _BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt } // Timer A0 interrupt service routine #pragma vector=timera0_vector interrupt void Timer_A (void) { P1OUT ^= 0x01; // Toggle P1.0 CCR0 += 50000; // Add Offset to CCR0 } CSE 466 Microcontrollers 45
MSP430 CPU Introduction RISC architecture with 27 instructions and 7 addressing modes. Orthogonal architecture with every instruction usable with every addressing mode. 16-bit address bus allows direct access and branching throughout entire memory range; no paging 16-bit data bus allows direct manipulation of word-wide arguments. Constant generator provides six most used immediate values and reduces code size. Direct memory-to-memory transfers without intermediate register holding. Word and byte addressing and instruction formats. Compact silicon 30% smaller than an 8051 saves power and cost CSE 466 Microcontrollers 46
MSP430 register properties Large 16-bit register file eliminates single accumulator bottleneck, reduces fetches to memory. Full register access including program counter, status registers, and stack pointer. Single-cycle register operations. CSE 466 Microcontrollers 47
MSP430 Registers CSE 466 Microcontrollers 48
Registers: PC (R0) Each instruction uses an even number of bytes (2, 4, or 6) PC is word aligned (the LSB is 0) Format: OP SRC, DST ; NB, a lot of processors use DST,SRC MOV #LABEL,PC ; Branch to address LABEL MOV LABEL,PC ; Branch to address contained in LABEL MOV @R14,PC ; Branch indirect, indirect R14 CSE 466 Microcontrollers 49
Registers: SP (R1) Stack pointer for return addresses of subroutines and interrupts Stack is in general purpose RAM (unlike e.g. PIC) SP is word aligned (the LSB is 0) Pushing a single byte on the stack wastes a byte the byte at the wasted location is not modified by the push Contrast with single-byte register operations, which zero the unused byte SP points to most recently added word (not to next free word) Starts from top of memory (0x0280 in F2013) In assembly, you must initialize the SP yourself! Don t try to jump in to an initialization subroutine to set up the SP if the SP is not set up before the subroutine call, you won t return properly from the initialization subroutine! CSE 466 Microcontrollers 50
Registers: SP (R1) Example stack manipulations: MOV 2(SP),R6 ; Item I2 > R6 2(SP) means 2+SP MOV R7,0(SP) ; Overwrite TOS with R7 PUSH #0123h ; Put 0123h onto TOS POP R8 ; R8 = 0123h Highest RAM address is 0x0280 in F2013 TOS: Top Of Stack TOS is actually the lowest address in the stack! CSE 466 Microcontrollers 51
Registers: SR (R2) C: SR(0) Carry Z: SR(1) Zero N: SR(2) Negative (==msb of result) GIE: SR(3) Global interrupt enable CPUOff: SR(4) LPM control OSCOff: SR(5) LPM control SCG0: SR(6) System Clock Generator 0 LPM control SCG1: SR(7) System Clock Generator 0 LPM control V: SR(8) signed overflow CSE 466 Microcontrollers 52
Example: msp430x20x3_1.asm.cdecls C,LIST, "msp430x20x3.h" ;------------------------------------------------------------------------------.text ; Progam Start ;------------------------------------------------------------------------------ RESET mov.w #0280h,SP ; Initialize stackpointer StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT SetupP1 bis.b #001h,&P1DIR ; P1.0 output ; Mainloop xor.b #001h,&P1OUT ; Toggle P1.0 Wait mov.w #50000,R15 ; Delay to R15 L1 dec.w R15 ; Decrement R15 jnz L1 ; Delay over? jmp Mainloop ; Again ; ;------------------------------------------------------------------------------ ; Interrupt Vectors ;------------------------------------------------------------------------------.sect ".reset" ; MSP430 RESET Vector.short RESET ;.end CSE 466 Microcontrollers 53
Status bits NB: in MSP430, mov operations do not affect status register CSE 466 Microcontrollers 54
Demo interlude, including debugger! CSE 466 Microcontrollers 55
End of lecture CSE 466 Microcontrollers 56
Constant Generators As source register addressing mode in the instruction word CPE/EE 421/521 Microcomputers 57
Constant generator examples Address Assembled instr Viewed in debugger ; Original user s asm code 0xF81C: 434F CLR.B R15 ; mov.b #0,R15 0xF81E: 435F MOV.B #1,R15 ; mov.b #1,R15 0xF820: 436F MOV.B #2,R15 ; mov.b #2,R15 0xF822: 407F 0003 MOV.B #0x0003,R15 ; mov.b #3,R15 0xF826: 426F MOV.B #4,R15 ; mov.b #4,R15 0xF828: 407F 0080 MOV.B #0x0080,R15 ; mov.b #80h,R15 0xF82C: 407F 007F MOV.B #0x007f,R15 ; mov.b #7Fh,R15 0xF830: 430F CLR.W R15 ; mov.w #0,R15 0xF832: 431F MOV.W #1,R15 ; mov.w #1,R15 0xF834: 432F MOV.W #2,R15 ; mov.w #2,R15 0xF836: 403F 0003 MOV.W #0x0003,R15 ; mov.w #3,R15 0xF83A: 422F MOV.W #4,R15 ; mov.w #4,R15 0xF83C: 403F 0080 MOV.W #0x0080,R15 ; mov.w #80h,R15 0xF840: 433F MOV.W #-1,R15 ; mov.w #0xFFFF,R15 Move operations that can use the constant generator assemble to 1 word Move operations that cannot use the constant generator assemble to 2 words CSE 466 Microcontrollers 58
CISC / RISC Instruction Set Good summary of MSP430 instructions: http://cnx.org/content/m23503/latest/ CSE 466 Microcontrollers 59
27 Core RISC Instructions Notes: -.b or.w: byte or word - add / addc: without/with carry - dadd: decimal add w/ carry (bin. coded decimal math) swpb: swap bytes sxt: sign extend (copies sign bit from b7 to b15-b8 for converting signed byte into signed word) rra: Roll right rrc: Roll right, through carry CSE 466 Microcontrollers 60
Emulated Instructions CSE 466 Microcontrollers 61
51 Total Instructions CSE 466 Microcontrollers 62
Example 2: msp430x20x3_p1_01.asm ;*******************************************************************************.cdecls C,LIST, "msp430x20x3.h" ;------------------------------------------------------------------------------.text ; Program Start ;------------------------------------------------------------------------------ RESET mov.w #0280h,SP ; Initialize stackpointer StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT SetupP1 bis.b #001h,&P1DIR ; P1.0 output Mainloop bit.b #010h,&P1IN ; P1.4 hi/low? jc ON ; jmp--> P1.4 is set ; OFF bic.b #001h,&P1OUT ; P1.0 = 0 / LED OFF jmp Mainloop ; ON bis.b #001h,&P1OUT ; P1.0 = 1 / LED ON jmp Mainloop ; ; ;------------------------------------------------------------------------------ ; Interrupt Vectors ;------------------------------------------------------------------------------.sect ".reset" ; MSP430 RESET Vector.short RESET ;.end CSE 466 Microcontrollers 63
Double operand instructions CSE 466 Microcontrollers 64
Single Operand Instruction CSE 466 Microcontrollers 65
Jump Instructions CSE 466 Microcontrollers 66
3 Instruction Formats CSE 466 Microcontrollers 67
Addressing Modes CSE 466 Microcontrollers 68
Register Addressing Mode CSE 466 Microcontrollers 69
Register-Indexed Addressing Mode Useful for implementing arrays above, 100h is the base address of the source array, and the contents of R4 are the index of the source array. Difference between C and MSP430 assembly: in assembly bytes are indexed, even if we re dealing with an array of words of larger in C, the index counts the items, whatever size they are CSE 466 Microcontrollers 70
Symbolic Addressing Mode mov.w LoopCtr, R6 ; load word LoopCtr into R6, symbolic mode becomes mov.w X(PC),R6 ; load word LoopCtr into R6, symbolic mode Where X = LoopCtr PC --- calc done by assembler Could also be called PC relative Gives a relative addressing scheme that can be used to create positionindependent code. Less useful in flash-based systems than RAM-based (since moving code is very costly in time and energy for flash). CSE 466 Microcontrollers 71
Absolute Addressing Mode mov.b &P1IN,R6 ; load byte P1IN into R6, abs mode becomes mov.b P1IN(SR),R6 ; load byte P1IN into R6, abs mode SR returns 0 in this case a kind of constant generator fn CSE 466 Microcontrollers 72
SP-relative Not claimed as an addressing mode by TI some other manufacturers call this a distinct addressing mode mov.w 2(SP),R6 ; most recent word but one from stack CSE 466 Microcontrollers 73
Register Indirect Addressing Mode Memory at addr held in R4 is moved into R5 This mode can t be used for destination addresses, only source Instead, need to use indexed addressing for destination: CSE 466 Microcontrollers 74
Register Indirect Autoincrement Addressing Mode Inverse operation: mov.w R6,0(R5) ; store word from R6 into addr 0+(R5)=4 incd.w R5 ; R5 += 2 CSE 466 Microcontrollers 75
Immediate Addressing Mode Equivalent to mov.w @PC+,R6 ; load immediate word 1234h into R6 DW 1234h ; CSE 466 Microcontrollers 76
MSP430 example peripherals CSE 466 Microcontrollers 77
Comparator_A (see also Comparator_A+) Comparator_A is an analog voltage comparator Compares analog input voltage to a reference voltage Useful for slope analogto-digital conversions Supply voltage supervision, and Monitoring of external analog signals. CSE 466 Microcontrollers 78
SAR ADCs http://www.maximintegrated.com/app-notes/index.mvp/id/1080 CSE 466 Microcontrollers 79
ADC10 10 bit ADC SAR (Successive Approximation Register) Fast ~200k samples per sec (ksps) Binary chopping CSE 466 Microcontrollers 80
ADC12 High-performance 12-bit analog-todigital converter More than 200 Ksamples/sec Programmable sample & hold 8 external input channels Internal storage CSE 466 Microcontrollers 81
Sigma-Delta ADC CSE 466 Microcontrollers 82
SD16_A Sigma-Delta ADC 16 bits of precision Slow Example application: metering CSE 466 Microcontrollers 83
USART Serial Port The universal synchronous/ asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module UART or SPI (Synchronous Peripheral Interface) modes Double-buffered Baud-rate generator CSE 466 Microcontrollers 84
USI module 8 or 16 bit shift register that can output data streams HW to ease I2C or SPI communication 3 wire SPI mode support I2C mode support Slave operation in LPM4 no internal clock required CSE 466 Microcontrollers 85
End of lecture CSE 466 Microcontrollers 86