Organization in Memory

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Jasmin Gilbert
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1 in 16 addresses for sub-routines Is written once prior to initialization, however it can be changed in chunks of 512 bytes during operation two small blocks programmed via scatt.-fl. only 2kB fast RAM no real memory behind those addresses, but connected with the "outside world" (memory-mapped) 0xFFE0-0xFFFF 0x1100-0xFFDF 0x1000-0x10FF 0x0A00-0x0FFF 0x0200-0x09FF 0x0100-0x01FF 0x0000-0x00FF Interrupt Vectors ca. 60 kbyte Flash-ROM for firmware, programs, data, tables If there's enough energy left, the application can itself write data here! 2x128 Byte Flash-ROM Boot-Loader ROM (fix) RAM (for variables, stack) 16-Bit periphery ( mapped) 8-Bit periphery ( mapped) only word-wise (16 Bit) reading only byte-wise (8 Bit) reading

2 MSP430 The MSP430 has 16 registers R0-R15. Therefrom the first four have a specific meaning. Hint: Other assemblers permit the usage of the terms PC, SP, SR for the special registers. However, with the GNU msp430 tools the (precise) register names have to be used. Of course everyone can define her own replacements (take care not to generat side effects) R0: Program Counter, for short PC. If you write a value into R0, it's interpreted by the processor as the address, where the next instruction to be performed is located. Loading R0 with an address is equivalent to a jumping to the corresponding address. Basic rule: the PC is always even! Note that some instruction take n*2 bytes in memory. That's why not every even address is necessarily a valid instruction. R1: Stackpointer, for short SP. It's always even, too. The LSB (Least Significant Bit) ist not implemented at all. The stack gets initialised with its highest address and increases downwards. The stack is never completely under control of the main program. Interrupt routines can change it at any time, but have to revise the changes before the return.

3 MSP430 R2: Status Register, for short SR. Every bit has its own, independent meaning. Bit 9-15: reserved for future address extensions Overflow Low Power Mode Bit 1 Low Power Mode Bit 0 Oscillator switch (off=1, on=0) CPU switch (on=1) CPU OSC V SCG 1 SCG 0 OFF General Interrupt Enable (on=1) Negative Flag Zero Flag Carry Flag OFF GIE N Z C

4 MSP430 R3: constant register. Reading this register always returns zero. Writing is possible, but has no effect (like /dev/null under linux). The constant register is mainly used internally in order to create the constants #-1, #0, #1, #2, #4 and #8. Why? A direct constant like #61 has to be put into memory after the instruction word. But the six constants above mentioned, are frequently used in applications. So it makes sense to code them as flags in an instruction word. Gain: shorter programs and faster execution because one memory-access is saved.

5 Different permit reading and writing of the memory in different ways. Classic RISC Processors often have only two explicit addressing instructions LOAD and STORE. Thereby all other operations can only access registers. At the MSP430 all can be combined with all instructions. Constants #0x1F00 hexadecimal (more precisely sedecimal) #49152 decimal Constants can certainly be only source operands, but never destination operands. example: mov #1234, R7 Program Counter indirect (PC) nnnn // load the number 1234 into register R7 Addresses the "storage cell" PC+nnnn This is the std. addressing of the MSP430. Counting the address nnnn PC indirect is not necessary. The assembler does this job.

6 Absolute Address &nnnn Addresses the storage cell with the house number nnnn example: mov.b #7, &0029 // Addresses storage cell Register (direct) Rn Register n serves as operand. example: mov R5, R6 // loads Register 6 with content of Register 5 Register Register n contains the house number of the storage cell, whose content gets addressed example: mov #FFFE, R15 // loads Register 15 with address FFFE mov // write the value 2100 into (ab) FFFE

7 Register (with index) offset(rn) Register n contains the house number + offset of the storage cell, whose content gets addressed example: mov #FFFF, R15 // loads Reg. 15 with address (as the case may be number) FFFF example: mov #0123, -1(R15) // writes 123 starting at address FFFE Register indirect with // addresses Register Rn and increments // it instantly after the by 2 example: mov #1234, &0200 // writes 1234 starting at storage cell 200 example: mov #0200, R7 // loads Register 7 with value (address) 200 R1 // loads Register R1 with 1234 // then 202 stands in R7 What does the following expression: -2(R15)

8 In particular, conditional jumps take place after comparisons or arithmetic operations, leaving their marks in the flags of the Status Register. Depending on these flags, the following conditional jumps can be executed. Hint for a better understanding: A comparison cmp src, dest is implemented as subtraction from dest-src. JNE/JNZ Jump Not Zero Jump if Z==0 (if src!= dest) JEQ/JZ Jump Zero Jump if Z==1 (if src == dest) JN Jump Negative Jump if N==1 (if dest < src) only correct, if no overflow Beware of overflow: cmp.b 1, -127 checking = is already out of the codomain. As a result, only the carry bit is set! The negative bit, which one would have liked to keep, gets in a way overwritten by the illegal bit of the -128 JL Jump Less than Jump if N==1 xor C==1 (if dest < src) Here as well, the result of the subtraction can be wrong because of the overflow, however depending on the bits, jumping is at least correct.

9 JNC Jump Not Carry Jump if C==0 (if (op1+op2)<=0xffff) JC Jump Carry Jump if C==1 JGE Hint: Jump if Greater or Equal Jump if (N xor V) == 0 (if dest > src) Analogical to the consideration of JL vs. JN one could implement easily a "Jump Greater or Equal" as "Jump Not Negative". In this case however, the same problem with the carry at JN with big numbers arises. It is solved by adding the Carry-Bit. Only if both are set "greater or equal" is valid. JMP Jump Jump in any case

10 Hint: mov src, dest add src, dest addc src, dest sub src, dest subc src, dest cmp src, dest dadd src, dest ~ is the bit-wise NOT operator (as defined in C for example) all instructions can have Byte.b or Words.w as arguments..w is optional and can be left out. mov.b &0100, &0200 // content of storage cell &200 = &100 mov.w &0100, &0200// &200 = &100 and &201 = &101 dest = src dest = dest + src dest = dest + src + C (for > 16 Bit calculations) dest = dest src dest = dest - src + C dest src (like subtraction, but without storage) dest = dest + src + C (Binary Coded Decimal) bit src, dest dest & src (but without storage) bic src, dest dest = dest & ~src bis src, dest dest = dest src xor src, dest dest = dest ^ src and src, dest dest = dest & src

11 Remember: the binary complement +40 in binary representation (S = sign) S (a) Bit-wise inverting S (b) +1 (= -40 as binary complement) S

12 rrc.b or rrc.w swapb C->BIT(n)->BIT(n-1)->BIT(1)->C i.e. rotation of a 9 respectively 17 Bit Operand to the right swap high-order and low-order Byte. Only makes sense for Word-Operands rra.b or rra.w arithmetic shift right, i.e. division by 2 BIT(n)->BIT(n) and BIT(n)->BIT(n-1)->BIT(1)->C Why is BIT(n) both saved and copied? The reason is, otherwise the binary complement is not kept. Example:

13 rra.b or rra.w arithmetic shift right, i.e. division by 2 BIT(n)->BIT(n) and BIT(n)->BIT(n-1)->BIT(1)->C Why is BIT(n) both saved and copied? In order that the binary complement is treated correctly. Example: +40 in binary representation (S = sign) S (as binary complement) S rra.w (results in 20) S rra.w (results in -20) S

14 push operand call dst push operand on the stack and decrement SP by 2 (at push.b! SP is always even, too) example: push R5 // can be replaced by sub 2, SP // SP always points to the last pushed date // on the stack. But we want to save here // a new one immediately. mov jumps to a subprogram, whose address is stored in dst. CAUTION: we don't jump to dst itself. The absolute addressing would be &dst. Difference to jmp: a comfortable return happens with ret. example: call dst // can be replaced by sub 2, SP // we're about to save the return address mov // mov dst, PC // the jump happens through direct // manipulation of the Program Counter PC

15 ret reti This way subprograms are terminated, which were called by call. A return to the next address after the call occurs. example: ret // can be emulated by mov add 2, SP // get saved address from stack // forget address PC // the same in only one expression Return from Interrupt. example: reti // like ret, but additionally the SR is saved sxt operator mov add 2, SP mov add 2, SP // get saved flags from stack // forget address // get saved address from stack // forget address expands 8 Bit word to 16 Bit. Algebraic sign is kept! Only makes sense in the.w version.

16 Multiplications are not included into the core of the MSP430. However there is a hardware multiplier, which is addressed via the mapped memory for 16 Bit periphery (0x100-0x1FF) just like every other external device (e.g., the light emitting diodes). TI denotes the four types of multiplications with MPY, MPYS, MAC and MACS. MPY: 1. Operand unsigned Multiplication MPYS: 1. Operand signed Multiplication MAC: 1. Operand unsigned Mult. a. Add. MACS: 1. Operand signed Mult. a. Add. 2. Operand signed/unsigned RESLO: 16 LSW of the result RESHI: 16 MSW of the result SUMMEXT: Sum Extension 0x130 0x132 0x134 0x136 0x138 0x13A 0x13C 0x13E

17 Calling the multiplications within the program: (1) Selection of the memory for the first 16 Bit operand and loading of the memory with the 1. operand. The memory is also named register of the multiplier. mov #0xFFFF, &0x130 // this way the unsigned multiplication is chosen (2) For all types of multiplications does apply: 0x138 is the register for the 2. operand. In the moment of writing in 0x138 the multiplier is started (automatically). The writing triggers the execution. The processor stays thereby unstressed. mov #0xFFFF, &0x138 // 0xFFFF is the second operand (3) The first 16 Bit of the result are located in the addresses starting at 0x13A (thus 0x13A and 0x13B), the second 16 Bit at 0x13C (thus 0x13C and 0x13D). SUMEXT contains a carry at unsigned operations. At unsigned operations it contains the algebraic sign. Note: The result is available after 2 clock cycles. That's why there possibly has to be inserted a "nop" after the calculation with short instructions (or you do something else useful). Hint: Beware of interrupts!

18 MSP430 Classical proactive Programming: The main program is completely responsible for the whole processing. void main(...) // first access after run { while(endless) // runs continuous until end { if hardware_event then HandleHardwareEvent(...); if idle then Sleep(100ms); } // end while } // end main exit point re-entry point It's elegant not to block the processor all the time with the while(endless)-loop. This uses in either case 100% of the processor power, no matter how fast that is. In the example the Sleep()-instruction eases this issue, if there's no event. Then the process is ignored for 100ms by the scheduler of the OS and other processes are able to obtain the cpu resources. But thus the response time gets worse to 50ms in average case.

19 MSP430 Reactive Programming: That's what most modern OS expect: void HandleHardwareEvent(...) {... } // end HandleHardwareEvent void main(...) // first access after run { InitAllYouNeed(...); OperatingSystem.RegisterHWEventHandler(HandleHardwarEvent); } // end main After run the application can initialize all necessary. Otherwise the program defines functions for events, which it wants to process. These functions are registered at the OS. If later on an event actually occurs, the OS calls the before registered program functions. So the program is in a way the service provider of the OS. Basically the programming of the MSP430 is reactive. If nothing happens, the processor is deactivated as fast as possible to save electricity.

20 MSP430 (Watchdog) The program can be woken up by a number of sensor-states via the comparators, if e.g. certain levels (e.g. the brightness) exceeds a reference value. has an exceptional position within the Interrupt Logic. It checks whether the program had a hang-up. It's active after the reset of the processor, however it can be deactivated in the program. The WD waits for a given maximum number of clock cycles. If it wasn't resetted until then, two different things depending on the mode of the WD could happen. It can trigger an interrupt or a reset in order to prevent, that rarely appearing problems lead to a total breakdown of the system. The WD works like the automatic emergency brake in trains, which is designed to prevent that the driver falls asleep.

21 MSP430 (Watchdog) 16-Bit Word-Register starting at address 0x0120 controls the Watchdog. If the Watchdog gets active, nothing else happens than a trigger of an interrupt. WD Timer (Vec 0xFFF4) WG HW Interrupt (Vec 0xFFFE) Password (is compared to 0x5A) WDTHOLD (0=active / 1=inactive) WDTNMIES WDTNMI WDTTMSEL (0=HW / 1=Timer) WDTCNTCL (1 = Counter reset) WDTSSEL Timer settings WDTTIS WDTTIS0

PHYS 319. Things to do before next week's lab Whirlwind tour of the MSP430 CPU and its assembly language Activity 1.

PHYS 319. Things to do before next week's lab Whirlwind tour of the MSP430 CPU and its assembly language Activity 1. PHYS 319 Things to do before next week's lab Whirlwind tour of the MSP430 CPU and its assembly language Activity 1. Before next week's lab: Read manual for Lab 2 and your OS setup guide then prepare your