Lancelot VGA video controller for the Altera Excalibur processors. v2.1 Marco Groeneveld May 1 st, 2003 http://www.fpga.nl
1. Description Lancelot is a VGA video controller for the Altera Nios and Excalibur ARM processors. The peripheral consists of two parts; the Lancelot core and the Lancelot hardware. The last part is a add-on daughter board, which fits on the expansion interface of various Altera (and Altera partner) development boards, like the Altera Cyclone Nios Development Board, Altera Stratix Nios development board and the Altera EPXA1 Development board. The board holds the Video DAC and the VGA, PS2 and audio connectors. The Lancelot core is written in VHDL and can be used for Altera APEX 20KE/C, APEX II, Cyclone and Stratix devices. Master Registers State Machine Line Buffer Line Buffer Colour Table Video DAC R G B Slave Registers Local Registers State Machine HS VS Bus Wrapper Video Core Board The Lancelot core is divided into two blocks. The video reads out the line buffers, drives the external video DAC and generates the sync signals. The bus wrapper is the bridge between the local interface and the Avalon (Nios) or AHB (ARM) interface with DMA capabilities. After the processor initialises and starts Lancelot, the VGA state machine requests new video data. The bus wrapper state machine reads one horizontal video line from the SDRAM and stores it in the line buffer. While one (empty) line buffer is filled by the bus wrapper DMA controller, the other (full) line buffer is readout by the VGA state machine. When the video line buffer is empty and the other line buffer is full, the line buffers are swapped and the process starts again. The colour table converts the 256 color data to 24-bits color pixels. The VGA state machine is also responsible for generating VGA timing and video DAC control signals. Lancelot VGA controller Page 2
2. Lancelot Core Signals Depending on the processor selected the Lancelot core will have different signals at the bus interface side. Table 2.1. shows the Lancelot core signals for the Nios processor and table 2.2. shows the signals for the Excalibur ARM processor. The principle for both cores is the same. The master port connects to the SDRAM controller and reads video data from the SDRAM using DMA. The processor can access the Lancelot register through the slave port. Signal Size Direction Description system_clk 1 In System clock video_clk 1 In Video clock reset_n 1 in Reset master_addr 32 out Avalon master address master_rddata 32 in Avalon master read data master_rd 1 out Avalon master read select master_waitreq 1 in Avalon master wait request slave_cs 1 in Avalon slave chip select slave_addr 3 in Avalon slave address slave_rddata 32 out Avalon slave read data slave_wrdata 32 in Avalon slave write data slave_rd 1 in Avalon slave read select slave_wr 1 in Avalon slave write select R 7 out Red output to video DAC G 7 out Green output to video DAC B 7 out Blue output to video DAC HS 1 out Hsync to VGA VS 1 out Vsync to VGA M1 1 out Mode select video DAC M2 1 out Mode select video DAC Blank_n 1 out Control signal to video DAC Sync_n 1 out Control signal to video DAC Sync_t 1 out Control signal to video DAC Table 2.1. Lancelot Nios Core signals Lancelot VGA controller Page 3
Signal Size Direction Description hclk 1 In System clock vclk 1 In Video clock hreset_n 1 in Reset master_haddr 32 out AHB master address master_htrans 2 out AHB master transfer master_hwrite 1 out AHB master write master_hsize 2 out AHB master transfer master_hburst 3 out AHB master burst master_hwdata 32 out AHB master write data master_hrdata 32 in AHB master read data master_hready 1 in AHB master ready master_hresp 2 in AHB master response master_hlock 1 out AHB master lock master_hbusreq 1 out AHB master bus request master_hgrant 1 in AHB master grant slave_haddr 5 in AHB slave address slave_htrans 2 in AHB slave transfer slave_hwrite 1 in AHB slave write slave_hsize 2 in AHB slave size slave_hburst 3 in AHB slave burst slave_hwdata 32 out AHB slave write data slave_hrdata 32 in AHB slave read data slave_hreadyo 1 out AHB slave ready out slave_hreadyi 1 in AHB slave ready in slave_hresp 2 out AHB slave response slave_hsel 1 in AHB slave select R 7 out Red output to video DAC G 7 out Green output to video DAC B 7 out Blue output to video DAC HS 1 out Hsync to VGA VS 1 out Vsync to VGA M1 1 out Mode select video DAC M2 1 out Mode select video DAC Blank_n 1 out Control signal to video DAC Sync_n 1 out Control signal to video DAC Sync_t 1 out Control signal to video DAC Table 2.2. Lancelot ARM Core signals Lancelot VGA controller Page 4
3. Lancelot Registers The Lancelot core has 7 registers, which are all 32-bits wide. Register Map Offset Register Mode 0 Control W 0 Status R 1 Colour Table W 2-3 - 4 Resolution R/W 5 Horizontal Timing R/W 6 Vertical Timing R/W 7 DMA R/W Control Register Bit Name Description 5 VS Polarity Writing a logic 1 inverts the VS output. 4 HS Polarity Writing a logic 1 inverts the HS output. 3 Set DAC Mode A logic 1 sets the Video DAC in RGB mode. 2 Start Video Writing 1 to this bit starts the internal video state machine. 0 Reset The Lancelot Core is automatic reseted during power-up. Status Register Bit Name Description 31 16 Signature MG (5247) 9 New Frame This bit is 1 when the next frame is the first frame of the screen. 8 Frame Missed The bit is set when the line buffer isn t filled with a new line after an dma request or writing the line buffer data took longer than maximum line time (32 µs). 7 Line Buffer Video Full This bit is 1 when the video line buffer is full. 6 Line Buffer Video Empty This bit is 1 when the video line buffer is empty. 5 Line Buffer DMA Full This bit is 1 when the DMA line buffer is full. 4 Line Buffer DMA Empty This bit is 1 when the DMA line buffer is empty. 3 Blank VS This bit indicates the vertical blank status ( 1 = vertical blank). 2 Blank HS This bit indicates the horizontal blank status ( 1 = horizontal blank). 1 VS Internal vsync signal. 0 HS Internal hsync signal. Colour Table Register Bit Description Lancelot VGA controller Page 5
31-24 Colour index 23-16 Red value 15 8 Green value 7 0 Blue value Resolution Register Bit Description 25-16 Horizontal Resolution 15 0 Vertical Resolution Horizontal Timing Register Bit Description 23 16 Pulse Width 15 8 Back Porch Width 7 0 Front Porch Width Vertical Timing Register Bit Description 13 16 Pulse Width 15 8 Back Porch Width 7 0 Front Porch Width DMA Register Bit Description 31-0 DMA start address Lancelot VGA controller Page 6
4. Video Timing The two figures below show the timing of a video line and video frame. According to the resolution a line consists of 640, 800 or 1024 pixels. A frame is divided into 480, 600 or 768 lines. If the BLANKn signal is asserted the output of the video DAC is forced to zero. When the horizontal sync signal (HS) is low indicates a new line. A new frame is indicated by a low pulse on the vertical sync signal (VS). Active Line BLANKn RGB HS A B C D E Figure 4.1. Horizontal Video Timing (Line) Active Line BLANKn RGB VS F G H I J Figure 4.2. Vertical Video Timing (Frame) Lancelot VGA controller Page 7
Resolution 640 x 480 800 x 600 1024 x 768 A Line Period 32.8 µs 26.4 µs 20.7 µs B Hsync Sync Period 3.8 µs 3.2 µs 2.1 µs C Hsync Back Porch 1.9 µs 2.2 µs 2.5 µs D Active Video 25.4 µs 20 µs 15.7 µs E Hsync Front Porch 0.6 µs 1 µs 0.4 µs F Frame Period 16.7 ms 16.58 ms 16.67 ms G Vsync Sync Period 0.05 ms 0.1 ms 0.12 ms H Vsync Back Porch 1 ms 0.6 ms 0.6 ms I Active Frame 15.3 ms 15.84 ms 15.88 ms J Vsync Front Porch 0.3 ms 0.02 ms 0.06 ms Table 4.1. Video Timing Table 4.2. shows the video settings, which can be used to set the Lancelot horizontal and vertical timings registers. Resolution 640 x 480 800 x 600 1024 x 768 * Video Clock 25.2 Mhz 40 Mhz 65 Mhz Horizontal Resoltution 640 800 1024 Vertical Resolution 480 600 768 Hsync Pulse Width 95 128 136 Hsync Back Porch Width 40 88 160 Hsync Front Porch Width 25 40 24 Vsync Pulse Width 2 4 6 Vsync Back Porch Width 22 23 29 Vsync Front Porch Width 10 1 3 Table 4.2. Video Settings * Note; This video mode is only supported by the Excalibur ARM reference design. Lancelot VGA controller Page 8
5. Lancelot Board I/O pins This table lists the Lancelot I/O pins and their connections on the Excalibur Development board devices. Signal Name Lancelot # EP20K200E EPXA1 EP1S10 EP1C20 Red 0 JP1-25 R5 T14 AD23 U12 Red 1 JP1-23 K15 T15 AF23 V12 Red 2 JP1-21 P20 U12 AH23 T13 Red 3 JP1-18 K16 U13 AE22 R13 Red 4 JP1-17 P21 U14 AF22 Y13 Red 5 JP1-16 N21 U15 AH22 W13 Red 6 JP1-15 L7 V13 AG22 U13 Red 7 JP1-14 N5 V14 AG20 V13 Green 0 JP1-3 N20 Y22 AD19 T15 Green 1 JP1-4 K20 Y16 AE19 W15 Green 2 JP1-5 P4 Y15 AF18 Y15 Green 3 JP1-6 K4 Y14 AH20 U15 Green 4 JP1-7 V11 Y13 AH21 V15 Green 5 JP1-8 K22 Y12 AF20 V14 Green 6 JP1-9 K19 W16 AE20 U14 Green 7 JP1-10 P22 W15 AF21 Y14 Blue 0 JP1-27 N6 T13 AG23 T12 Blue 1 JP1-28 L20 T12 AE23 T11 Blue 2 JP1-29 J18 R13 AH24 W12 Blue 3 JP1-32 M17 AB16 AG24 W8 Blue 4 JP1-31 K18 AB17 AE24 Y12 Blue 5 JP1-33 J3 AB15 AF25 Y8 Blue 6 JP1-36 R4 AA17 AG25 V9 Blue 7 JP1-35 K5 AB14 AH25 U9 HS JP1-37 J7 AA16 AH26 T9 VS JP1-39 J5 AA15 AG26 R9 Blank_n JP1-13 V12 V15 AD21 R14 Sync_n JP1-12 R22 W13 AE21 T14 Sync_t JP1-11 N22 W14 AG21 W14 M1 JP2-11 J1 AA6 AA19 V11 M2 JP2-12 J12 AA5 Y17 U11 Audio Left JP2-5 M20 AA12 AC21 W9 Audio Right JP2-7 R21 AA10 AA20 U10 PS2 Select JP2-9 K3 AA8 W19 W10 PS2 Keyboard Clock JP2-10 N2 AA7 W18 Y10 PS2 Keyboard Data JP2-8 L17 AA9 Y19 V10 PS2 Mouse Clock JP2-6 L16 AB4 AC19 T10 PS2 Mouse Data JP2-4 N18 AA14 AF24 Y9 Lancelot VGA controller Page 9
6. Reference Designs 6.1. Altera APEX Nios Development Board Follow these steps to run the Lancelot reference design; - Power off the APEX Nios development board. - Attach the Lancelot daughter card to the 3V3-expansion prototype connector (JP8, JP9 & JP10). The VGA connector should point away from the APEX Nios development board. - Connect a VGA monitor to the Lancelot daughter board. - Insert a SDRAM module into the SODIMM socket J2. - Connect a serial cable to the APEX Nios development board serial port. - Power the APEX Nios development board. - Open the Nios SDK shell and change the directory to /<lancelot_installation_directory> - Type nr x lancelot.hexout.flash to program the APEX Nios development board with the Lancelot hardware. - Press SW2 to reset the APEX Nios development board and activate the Lancelot hardware. - Change to directory to /<lancelot_ installation_directory>/cpu_sdk/src - Upload the image to the APEX Nios development board by typing nr x image_640x480.flash - Run the Lancelot software by typing nr lancelot.srec The utility convert, which is located in the /<lancelot_installation_directory>/cpu_sdk/src directory, converts a 640 x 480 BMP-image with 256 colours to the custom Lancelot image HEX-format. The command convert my_image.bmp my_image.flash 0x10000 flash converts your image and places it in the image buffer address location. The address 0x10000 is the start of the image buffer used in this Lancelot reference design. Reset the APEX Nios development board by pressing SW3 and upload your image by typing nr x my_image.flash. Type nr lancelot.srec to run the Lancelot software. To edit the Lancelot reference design open the file lancelot.quartus in the Quartus II software. Lancelot VGA controller Page 10
6.2. Altera Excalibur EPXA1 Development Board To run the Lancelot reference design on the EPXA1 development board perform the following steps; - Power off the EPXA1 development board. - Attach the Lancelot daughter board to the EPXA1 standard expansion headers (J10, J11 & J15). The VGA connector should point away from the EPXA1 development board. - Connect a VGA video monitor to the VGA connector. - Connect an Altera programmer cable (ByteBlaster or MasterBlaster) to the EXPA1 development board JTAG header. - Power the EPXA1 development board. - Open a DOS prompt and change the directory to \<lancelot_installation_ directory>\arm_stripe_sdk\src - Upload the image to the EPXA1 development board flash memory by typing exc_flash_programmer e 1 image.hex - Change the directory to \<lancelot_installation_directory> - Type exc_flash_programmer e 0 g lancelot_flash.hex to upload and start the Lancelot reference demo. You can replace the default image by your own image. Use the convert utility (located in the <lancelot_installation_directory>\arm_stripe_sdk\src directory) to convert a 1024 x 768 BMP-image (or lower resolution) with 256 colours to the custom Lancelot image HEX format. Type convert my_image.bmp my_image.hex 0x0 hex to convert your image. In this Lancelot reference design the flash connected to EBI1 is used as image buffer and starts at address 0x0. Upload your picture to the EPXA1 development board by typing exc_flash_programmer e 1 g my_image.hex To edit the Lancelot reference design open the file lancelot.quartus in the Quartus II software. Lancelot VGA controller Page 11
6.3. Cyclone Nios Development Board The following steps describes how to run the Lancelot reference design on the Cyclone Nios development board; - Switch off the power of the Cyclone Nios development board. - Attach the Lancelot daughter board to the expansion proto type connector (J15, J16 & J17). The VGA connector should point away from the Cyclone Nios development board. - Connect the VGA monitor to the Lancelot VGA connector. - Connect a serial cable to the console serial port of the Cyclone Nios development board. - Power the Cyclone Nios development board. - Hold switch SW0 while pressing the Safe Config switch (SW9) to start the default safe configuration. - Open the Nios SDK shell and change the directory the /<lancelot_installation_directory>. - Upload the Lancelot hardware image to the development board by typing nr x lancelot.hexout.flash - Press the Reset Config switch (SW10) to activate the Lancelot hardware. - Change the directory to /<lancelot_installation_directory>/cpu_sdk/src - Type nr x image_800x600.flash to program the test image to the flash memory. - Press the CPU Reset switch (SW8). - Finally type nr lancelot.srec to upload and execute the Lancelot software. The utility convert, which is located in the /<lancelot_installation_directory>/cpu_sdk/src directory, converts a 800 x 600 BMP-image (or lower resolution) with 256 colours to the custom Lancelot image HEX-format. The command convert my_image.bmp my_image.flash 0x0 flash converts your image and places it in the image buffer address location. The address 0x0 is the start of the image buffer in the flash memory used in this Lancelot reference design. Reset the Cyclone Nios development board by pressing the Power-On-Reset button and upload your image by typing nr x my_image.flash. Type nr lancelot.srec to run the Lancelot software. To edit the Lancelot reference design open the file lancelot.quartus in the Quartus II software. Lancelot VGA controller Page 12
6.4. Stratix Nios Development Board The following steps describes how to run the Lancelot reference design on the Stratix Nios development board; - Switch off the power of the Stratix Nios development board. - Attach the Lancelot daughter board to the expansion proto type connector (J15, J16 & J17). The VGA connector should point away from the Stratix Nios development board. - Connect the VGA monitor to the Lancelot VGA connector. - Connect a serial cable to the console serial port of the Stratix Nios development board. - Power the Stratix Nios development board. - Hold switch SW0 while pressing the Safe Config switch (SW9) to start the default safe configuration. - Open the Nios SDK shell and change the directory the /<lancelot_installation_directory>. - Upload the Lancelot hardware image to the development board by typing nr x lancelot.hexout.flash - Press the Reset Config switch (SW10) to activate the Lancelot hardware. - Change the directory to /<lancelot_installation_directory>/cpu_sdk/src - Type nr x image_800x600.flash to program the test image to the flash memory. - Press the CPU Reset switch (SW8). - Finally type nr lancelot.srec to upload and execute the Lancelot software. The utility convert, which is located in the /<lancelot_installation_directory>/cpu_sdk/src directory, converts a 800 x 600 BMP-image (or lower resolution) with 256 colours to the custom Lancelot image HEX-format. The command convert my_image.bmp my_image.flash 0x0 flash converts your image and places it in the image buffer address location. The address 0x0 is the start of the image buffer in the flash memory used in this Lancelot reference design. Reset the Cyclone Nios development board by pressing the Power-On-Reset button and upload your image by typing nr x my_image.flash. Type nr lancelot.srec to run the Lancelot software. To edit the Lancelot reference design open the file lancelot.quartus in the Quartus II software. Lancelot VGA controller Page 13
7. Simulation 7.1. Nios Simulation The following steps will run the simulation of the Lancelot Nios core; - Open ModelSim - Change the working directory to /<lancelot_installation_directory>/nios_sim - Execute the simulation script (do setup_vga.do) - Start the simulation by entering the s-command. - Run the simulation (run 10 ms) 7.2. Excalibur ARM Simulation The following steps will run the simulation of the Lancelot ARM core. - Open ModelSim - Change the working directory to /<lancelot_installation_directory>/arm_sim - Execute the simulation script (do run.do) - Run the simulation (run 10 ms) Lancelot VGA controller Page 14
8. Lancelot Daughter Board Lancelot Board Schematic Lancelot VGA controller Page 15
Lancelot Daughter Board Component Side Lancelot Daughter Board Solder Side Lancelot Daughter Board Silk Screen Designator Description C1 Capacitor / Tantalum / 22 uf / 10 V / SMD Case B C2 Capacitor / Tantalum / 22 uf / 10 V / SMD Case B C3 Capacitor / 100 nf / SMD 0805 Lancelot VGA controller Page 16
C4 Capacitor / 100 nf / SMD 0805 C5 Capacitor / 100 nf / SMD 0805 C6 Capacitor / 100 nf / SMD 0805 C7 Capacitor / 10 nf / SMD 0805 C8 Capacitor / 100 nf / SMD 0805 C9 Capacitor / 100 nf / SMD 0805 C10 Capacitor / 100 nf / SMD 0805 C11 Capacitor / 100 nf / SMD 0805 C12 Capacitor / 10 nf / SMD 0805 C13 Capacitor / 10 nf / SMD 0805 C14 Capacitor / 10 pf / SMD 0805 C15 Capacitor / 100 nf / SMD 0805 D1 Diode / LL4148 / SOD80C J1 Header / Male / Single Row / 3 pins J4 Connector / High Density SUBD / 15 pins / PCB / Right Angle J5 Connector / Mini Din / 6 Way Socket J6 Connector / Mini Din / 6 Way Socket J7 Connector / Audio Stereo Jack 3 mm / LJE0361-5 JP1 Header / Female / Dual Row / 40 contacts JP2 Header / Female / Dual Row / 14 contacts JP3 Header / Female / Dual Row / 20 contacts L1 Inductor / 10 uh / 100 ma / SMD 0805 R1 Resistor / 390R / SMD 0805 R2 Resistor / 75R / SMD 0805 R3 Resistor / 75R / SMD 0805 R4 Resistor / 75R / SMD 0805 R5 Resistor / 33R / SMD 0805 R6 Resistor / 33R / SMD 0805 R7 Resistor / 10K / SMD 0805 R8 Resistor / 10K / SMD 0805 R9 Resistor / 10K / SMD 0805 R10 Resistor / 10K / SMD 0805 R11 Resistor / 10K / SMD 0805 R12 Resistor / 10K / SMD 0805 R13 Resistor / 10K / SMD 0805 R14 Resistor / 10K / SMD 0805 R15 Resistor / 10K / SMD 0805 U1 IC / Video DAC / THS8134BCPHP U2 IC / Regulator / LP2954AIS U3 IC / Bus Switch / PI5C3125L U4 IC / Opamp / LMC6462AIM X1 IC / 25.175 Mhz Oscillator / SMD Lancelot Daughter Board Bill of Materials Lancelot VGA controller Page 17