Department of Electrical Engineering Lecture 4 The 8051 Architecture 1
In this Lecture Overview General physical & operational features Block diagram Pin assignments Logic symbol Hardware description Pin description Read-modify-write port instructions 2
Overview of the 8051 Made by Intel in 1981 An 8-bit, single-chip microcontroller optimized for control applications 128 bytes RAM, 4096 bytes (4KB) ROM, 2 timers, 1 serial port, 4 I/O ports 40 pins in a dual in-line package (DIP) layout 3
General Physical Features 4KB ROM 128 bytes internal RAM 4 register banks of 8 bytes each (R0-R7) 16 bytes of bit-addressable area 80 bytes of general purpose memory Four 8-bit I/O ports (P0-P3) Two 16-bit timers (Timer0 & Timer1) One serial receiver-transmitter interface Five interrupt sources (2 external & 3 internal) One oscillator (generates clock signal) 4
General Operational Features Memory of 8051 can be increased externally: Increase memory space for codes (programs) by 64K Increase memory space for data by 64K Boolean instructions work with 1 bit at a time Assume clock frequency = 12MHz, it takes about 4 µs (i.e. 4 x 10-6 s) to carry out a 8-bit multiplication instruction 5
The 8051 Block Diagram External Interrupts Interrupt Control 4K byte ROM 128 byte RAM Timer 1 Timer 0 Counter Inputs CPU OSC Bus Control I/O Ports Serial Port TXD RXD P0 P2 P1 P3 (Address/Data) 6
The 8051 Pin Assignments P1.0 P1.1 1 2 40 39 V CC P0.0 (AD0) P1.2 3 38 P0.1 (AD1) P1.3 4 37 P0.2 (AD2) P1.4 P1.5 5 6 8051 36 35 P0.3 (AD3) P0.4 (AD4) P1.6 7 34 P0.5 (AD5) P1.7 8 33 P0.6 (AD6) RST 9 32 P0.7 (AD7) (RXD) P3.0 10 31 EA/VPP (TXD) P3.1 11 30 ALE/PROG (INT0) P3.2 12 29 PSEN (INT1) P3.3 13 28 P2.7 (A15) (T0) P3.4 14 27 P2.6 (A14) (T1) P3.5 15 26 P2.5 (A13) (WR) P3.6 16 25 P2.4 (A12) (RD) P3.7 17 24 P2.3 (A11) XTAL2 18 23 P2.2 (A10) XTAL1 19 22 P2.1 (A9) GND 20 21 P2.0 (A8) 7
The 8051 Logic Symbol VSS VCC RST XTAL1 XTAL2 EA P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 P O R T 0 ADDRESS AND DATA BUS PSEN ALE P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 P O R T 1 SECONDARY FUNCTIONS RxD TxD INT0 INT1 T0 T1 WR RD P O R T 3 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P O R T 2 ADDRESS BUS 8
Hardware Description 1. Oscillator circuit 2. Program counter (PC) 3. Data pointer (DPTR) 4. Accumulator ( A ) register 5. B register 6. Flags 7. Program status word (PSW) 8. Internal memory (ROM, RAM, additional memory) 9. Stack & stack pointer (SP) 10. Special function register (SFR) 9
Oscillator Circuit The heart of the 8051 Produces clock pulses Synchronize all 8051 s internal operations 10
Machine Cycle Machine cycle is the basic repetitive process that the CPU performs once it is powered on. A machine cycle consists of a fixed number of clock cycles (pulses). It is different for different kinds of CPU. The 8051 family needs 12 clock cycles for a machine cycle. The CPU takes one or more machine cycles to complete an instruction. More complex instructions require more number of machine cycles to complete the instruction. The number of machine cycles of the 8051 instructions are ranging from 1 to 4. 11
Example 4-14 Find the elapse time of the machine cycle for: (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz (c) XTAL = 20 MHz Solution: (a) 11.0592 MHz / 12 = 921.6 khz Machine cycle = 1 / 921.6 khz = 1.085 µs (b) 16 MHz / 12 = 1.333 MHz Machine cycle = 1 / 1.333 MHz = 0.75 µs (c) 20 MHz / 12 = 1.667 MHz Machine cycle = 1 / 1.667 MHz = 0.60 µs 12
Program Counter (PC) PC is a 16-bit register EEE3410 Microcontroller Applications PC is the only register that does not have an internal address Holds the address of the memory location to fetch the program instruction Program ROM may be on the chip at addresses 0000H to 0FFFH (4Kbytes), external to the chip for addresses that exceed 0FFFH Program ROM may be totally external for all addresses from 0000H to FFFFH PC is automatically incremented (+1) after every instruction byte is fetched 13
Data Pointer (DPTR) DPTR is a 16-bit register DPTR is made up of two 8-bit registers: DPH and DPL DPTR holds the memory addresses for internal and external code access and external data access DPTR is under the control of program instructions and can be specified by its 16-bit name, or by each individual byte name, DPH and DPL DPTR does not have a single internal address; DPH and DPL are each assigned an address (83H and 82H) 14
Accumulator (A Register) Most versatile CPU register and is used for many operations, including addition, integer multiplication and division, and Boolean bit manipulations A register is also used for all data transfer between the 8051 and any external memory 15
B Register B register is used with the A register for multiplication and division operations No other special function other than as a location where data may be stored 16
Flags Flags are 1-bit registers provided to store the results of certain program instructions Other instructions can test the condition of the flags and make decisions based on the flag states Flags are grouped inside the program status word (PSW) and the power control (PCON) registers for convenient addressing Math flags: respond automatically to the outcomes of math operations (CY, AC, OV, P) User flags: general-purpose flags that may be used by the programmer to record some event in the program (F0, GF0, GF1) 17
Program Status Word (PSW) PSW contains the math flags, user program flag F0, and the register select bits that identify which of the four general-purpose register banks is currently in use by the program 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV -- P 18
Program Status Word (PSW) Bit 7 6 5 4 3 2 1 0 Symbol CY AC F0 RS1 RS0 OV -- P Function Carry Flag; used in arithmetic, JUMP, ROTATE, and BOOLEAN instruction Auxiliary carry flag; used for BCD arithmetic User flag 0 Register bank select bit 1 Register bank select bit 0 Overflow flag; used in arithmetic instructions Reserved for future use Parity flag; shows parity of register A: 1 = Odd Parity 19
Instruction that Affect Flag Bits Instruction CY OV AC Instruction CY OV AC ADD X X X SETB C 1 ADDC X X X CLR C 0 SUBB X X X CPL C X MUL 0 X ANL C, bit X DIV 0 X ANL C, /bit X DA X ORL C, bit X RRC X ORL C, /bit X RLC MOV C, bit X X CJNE Note: X can be 0 or 1 X 20
Internal Memory A functioning computer must have memory for program code bytes, commonly in ROM, and RAM memory for variable data that can be altered as the program runs 8051 has internal RAM (128 bytes) and ROM (4Kbytes) 8051 uses the same address but in different memories for code and data Internal circuitry access the correct memory based on the nature of the operation in progress Can add memory externally if needed 21
8051 Internal RAM Organisation Bank 0 Bank 1 Bank 2 Bank 3 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 7F 78 77 70 6F 68 67 60 5F 58 57 50 4F 48 47 40 3F 38 37 30 2F 28 27 20 1F 18 17 10 0F 08 07 00 30 EEE3410 Microcontroller Applications Working Registers Bit Addressable General Purpose 7F 22
Example 2-52 State the contents of RAM locations after the following program: MOV R0, #99H MOV R1, #85H MOV R2, #3FH MOV R7, #63H MOV R5, #12H After the execution of the above program we have the following: RAM location 0 has value 99H RAM location 1 has value 85H RAM location 2 has value 3FH RAM location 7 has value 63H RAM location 5 has value 12H 23
Example 2-62 Repeat Example 2-5 using RAM addresses instead of register names. This is called direct addressing mode and uses the RAM address location for the destination address. MOV 00, #99H MOV 01, #85H MOV 02, #3FH MOV 07, #63H MOV 05, #12H 24
Example 2-72 EEE3410 Microcontroller Applications State the contents of RAM locations after the following program: SETB PSW.4 MOV R0, #99H MOV R1, #85H MOV R2, #3FH MOV R7, #63H MOV R5, #12H By default, PSW.3=0 and PSW.4=0; therefore, the instruction SETB PSW.4 sets RS1=1 and RS0=0, thereby selecting register bank 2. Register bank 2 uses RAM locations 10H 17H. After the execution of the above program we have the following RAM location 10 has value 99H RAM location 11 has value 85H RAM location 12 has value 3FH RAM location 17 has value 63H RAM location 15 has value 12H 25
Stack and Stack Pointer (SP) SP is a 8-bit register used to hold an internal RAM address that is called the top of the stack Stack refers to an area of internal RAM that is used in conjunction with certain opcodes to store and retrieve data quickly SP holds the internal RAM address where the last byte of data was stored by a stack operation When data is to be placed on the stack, the SP increments before storing data on the stack so that the stack grows up as data is stored As data is retrieved from the stack, the byte is read from the stack, and then the SP decrements to point to the next available byte of stored data 26
Stack Operation Store Data Get Data SP = 0A Address 0A SP = 0A Store Data Get Data SP = 09 Address 09 SP = 09 Store Data Get Data SP = 08 Address 08 SP = 08 SP = 07 Address 07 SP = 07 Storing Data on the Stack (Increment then store) Internal RAM (Get then decrement) Getting Data From the Stack 27
Example 2-82 Show the stack and stack pointer for the following. Assume the default stack area. MOV R6, #25H MOV R1, #12H MOV R4, #0F3H PUSH 6 PUSH 1 PUSH 4 EEE3410 Microcontroller Applications After PUSH 6 After PUSH 1 After PUSH 4 0B 0A 09 08 0B 0A 09 08 25 0B 0A 09 08 12 25 0B 0A 09 08 F3 12 25 SP = 07 SP = 08 SP = 09 SP = 0A 28
Example 2-92 Examine the stack, show the contents of the registers and SP after execution of the following instruction. All values are in hex. POP 3 ;POP stack into R3 POP 5 ;POP stack into R5 POP 2 ;POP stack into R2 After POP 3 After POP 5 After POP 2 0B 0A 09 08 54 F9 76 6C 0B 0A 09 08 54 F9 76 6C 0B 0A 09 08 54 F9 76 6C 0B 0A 09 08 54 F9 76 6C Start SP = 0B SP = 0A R3 = 54 SP = 09 R5 = F9 SP = 08 R2 = 76 29
Example 2-102 Show the stack and stack pointer for the following. MOV SP, #5FH MOV R2, #25H MOV R1, #12H MOV R4, #0F3H PUSH 2 PUSH 1 PUSH 4 63 62 61 60 EEE3410 Microcontroller Applications After PUSH 2 After PUSH 1 After PUSH 4 63 62 61 60 25 63 62 61 60 63 62 61 60 Start SP = 5F SP = 60 SP = 61 SP = 62 12 25 F3 12 25 30
Special Function Registers (SFR) 8051 has 21 SFRs which occupy the addresses from 80H to FFH (128bytes) Not all of the addresses from 80H to FFH are used for SFRs Attempt to use the empty addresses may get unpredictable result 31
Special Function Register Map Bit addressable 32
Internal ROM Internal ROM occupies the code address space from 0000H to 0FFFH Program addresses higher than 0FFFH will automatically fetch code bytes from external program memory Code bytes can also be fetched exclusively from an external memory by connecting the external access pin (EA) to ground 33
Some Important Pins VCC (pin 40 - provides supply voltage of +5V) GND (pin 20) XTAL1 & XTAL2 (pins 19 & 18 - to crystal and then caps) RST (pin 9- reset) EA (pin 31 - external access) PSEN (pin 29 - program store enable) ALE (pin 30 - address latch enable) Ports 0-3 34
I/O Ports (P0 - P3) One of the most useful features of the 8051 is that it consists of 4 I/O ports (P0 - P3) All ports are bidirectional (they can take input and to provide output) All ports have multiple functions (except P1) All ports are bit addressable On RESET all the ports are configured as output When a bit latch is to be used as an input, a 1 must be written to the corresponding latch by the program to configure it as input 35
Port 0 Occupies a total of 8 pins (Pins 32-39) Can be used for : Input only Output only Input and output at the same time (i.e. some pins for input and the others for output) Can be used to handle both address and data Need pull-up resistors 36
Port 0 as an Output Port The following code will continuously send out to port 0 the alternating values 55H and AAH MOV A, #55H BACK: MOV P0, A ACALL DELAY CPL A SJMP BACK 37
Port 0 as an Input Port In the following code, port 0 is configured first as an input port by writing 1s to it, and then data is received from that port and sent to P1 MOV A, #0FFH MOV P0, A BACK: MOV A, P0 MOV P1, A SJMP BACK 38
Dual Role of Port 0 When connecting an 8051 to an external memory, port 0 provides both address and data (AD0 AD7) When ALE = 0, it provides data D0 D7 When ALE = 1, it provides data A0 A7 ALE is used for demultiplexing address and data with the help of a 74LS373 latch 39
Port 1 Occupies a total of 8 pins (Pins 1-8) Can be used as input or output Does not need any pull-up resistors Upon reset, port 1 is configured as an output port No alternative functions 40
Port 1 as an Output Port The following code will continuously send out to port 1 the alternating values 55H and AAH MOV A, #55H BACK: MOV P1, A ACALL DELAY CPL A SJMP BACK 41
Port 1 as an Input Port EEE3410 Microcontroller Applications In the following code, port 1 is configured first as an input port by writing 1s to it, and then data is received from that port and saved in R7, R6, and R5 MOV MOV MOV MOV ACALL MOV MOV ACALL MOV MOV A, #0FFH P1, A A, P1 R7, A DELAY A, P1 R6, A DELAY A, P1 R5, A 42
Port 2 Occupies a total of 8 pins (Pins 21-28) Similar function as Port 1 Can be used as input or output Does not need any pull-up resistors Upon reset, port 1 is configured as an output port 43
Port 2 as an Output Port The following code will continuously send out to port 2 the alternating values 55H and AAH MOV A, #55H BACK: MOV P2, A ACALL DELAY CPL A SJMP BACK 44
Port 2 as an Input Port In the following code, port 2 is configured first as an input port by writing 1s to it, and then data is received from that port and sent to P1 MOV A, #0FFH MOV P2, A BACK: MOV A, P2 MOV P1, A SJMP BACK 45
Dual Role of Port 2 When connecting an 8051 to an external memory, port 2 provides both address (A8 A15) It is used along with P0 to provide the 16-bit address When P2 is used for the upper 8 bits of the 16- bit address, it cannot be used for I/O 46
Port 3 Occupies a total of 8 pins (Pins 10-17) Similar function as Port 1 and Port 2 Can be used as input or output Does not need any pull-up resistors Upon reset, port 1 is configured as an output port Pins can be individually programmable for other uses Most commonly be used to provide some important signals (e.g. interrupts) 47
Port 3 Alternate Functions P3 Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Function RxD TxD INT0 INT1 T0 T1 WR RD Pin 10 11 12 13 14 15 16 17 48
Read-Modify Modify-Write Feature A method used to access the 8051 ports Combining all 3 actions in a single instructions : Read the data at the port Modify (do operation on) the data at the port Write the results to the port MOV P1, #55H AGAIN: XRL P1, #0FFH ACALL DELAY SJMP AGAIN 49
Single-bit Addressability of Ports One of the most powerful features of the 8051 Access only one or several bits of the port instead of the entire 8 bits BACK: CPL P1.2 ACALL DELAY SJMP BACK 50
Example 4-24 Write a program to perform the following: (a) Keep monitoring the P1.2 bit until it becomes high; (b) When P1.2 becomes high, write value 45H to port 0; and (c) Send a high-to-low (H-to-L) pulse to P2.3 SETB P1.2 MOV A, #45H AGAIN: JNB P1.2, AGAIN MOV P0,A SETB P2.3 CLR P2.3 51
Summary General physical & operational features 8051 hardware description 8051 pin description Read-modify-write port instructions 52
Review Questions 1. In the 8051, the program counter is bits wide. 2. True or false. Every member of the 8051 family, regardless of the maker, wakes up at memory 0000H when it is powered up. 3. At what ROM location do we store the first opcode of an 8051 program? 4. The instruction MOV A, #44H is a -byte instruction. 5. What is the ROM address space for the 8052 chip? 6. The flag register in the 8051 is called. 7. What is the size of the flag register in the 8051? 8. Which bits of the PSW register are user-definable? 53
Review Questions 9. Find the CY and AC flag bits for the following code. MOV A, #0FFH ADD A, #01 10. Find the CY and AC flag bits for the following code. MOV A, #0C2H ADD A, #3DH 11. What is the size of the SP register? 12. With each PUSH instruction, the stack pointer register (SP) is (incremented/decremented) by 1. 13. With each POP instruction, the SP (incremented/decremented) by 1. 14. ON power up, the 8051 uses RAM location as the first location of the stack. 54
Review Questions 15. On power up, the 8051 uses bank for registers R0 R7. 16. On power up, the 8051 uses RAM locations to for register R0 R7 (register bank 0). 17. Which register bank is used if we alter RS0 and RS1 of the PSW by the following two instruction? SETB SETB PSW.3 PSW.4 18. In Question 17, what RAM locations are used for register R0 R7? 55
Read reference The 8051 Microcontroller and Embedded Systems - Using Assembly and C, Mazidi Chapter 8 P.217 P.227 The 8051 Microcontroller Hardware, Software and Interfacing, James W. Stewart Chapter 1 P.1 P.16 Chapter 2 P.19 P.35 56