UFS Unified Memory Extension

UFS Unified Memory Extension Nobuhiro KONDO Toshiba Corporation JEDEC at CES 2014 Copyright 2013-2014 Toshiba Corporation

What & Why. UNIFIED MEMORY (UM)

What is Unified Memory? Share huge chunk of host memory with device. A single huge chunk of memory is better than plural small chunks. Common technology used, in particular, in today s graphics memory. Purpose. To realize fast access speed such as SSD at a reasonable cost such as e MMC. Large working memory (e.g., several MBytes) is a means for fast access. To reduce the chip size of device controller. Reduce the size of chip and deviceintegrated RAM. Unified Memory Architecture DRAM main memory Working Memory

Why UFS? Fast Communication Speed. UFS communication speed is fast enough to access host memory from device; which is up to 5.8 Gbps for a single lane. Rich Features. Full duplex. SCSI compliant commands. Multiple outstanding. Cost-Sensitive Mobile s. SSD for PC; which has enough deviceintegrated RAM as working memory. UFS SSD

Merits of Unified Memory UM Size >> -Embedded RAM. Faster in particular for random write. $ UM Controller < $ Conventional Controller (with -Embedded RAM).

Demerits of Unified Memory More Fragile at Power Loss. Extra-Complexity in Communication.

How to Realize Define a new protocol (UMPIU *1 ) to manipulate Unified Memory. Normal UFS uses a specific protocol (UPIU *2 ), which is compatible with SCSI commands. Flexibility of UFS framework. *1 Unified Memory Protocol Information Unit. *2 UFS Protocol Information Unit.

Cost / Power Target Area SSD e MMC UFS UFS UM Ext. Performance

How it works? What are differences? COMPARISON

Unified Memory Architecture Conventional Architecture Unified Memory Architecture DRAM main memory UFS HC UFS IF Controller Working Memory Working RAM in DRAM main memory UFS HC UFS IF Slave BUS IF Master IF Controller ECC DMA Working Memory Working RAM in ECC

SCSI Write (Command) Conventional Architecture Unified Memory Architecture DRAM main memory Command UFS HC DRAM main memory Command UFS HC UFS IF Controller Write Buffer Working RAM in UFS IF Slave BUS IF Master IF Controller ECC DMA Write Buffer Working RAM in ECC

SCSI Write (Data) Conventional Architecture Unified Memory Architecture DRAM main memory UFS HC Data Write UFS IF Controller Write Buffer Working RAM in DRAM main memory UFS HC Data Write UFS IF Slave BUS IF Master IF Controller ECC DMA Write Buffer Working RAM in ECC

SCSI Write (Write Back) Conventional Architecture Unified Memory Architecture DRAM main memory UFS HC DRAM main memory UFS HC UFS IF Controller Write Buffer ECC Working RAM in Data Write Back UFS IF Slave BUS IF Master IF Controller ECC DMA Data Write Back Write Buffer Working RAM in

Architecture Summary (Write Buffer) Conventional Architecture Unified Memory Architecture Command DRAM main memory UFS HC Data Write UFS IF Controller Write Buffer Working RAM in DRAM main memory Command UFS HC Data Write UFS IF Slave BUS IF Master IF Controller ECC DMA Data Write Back Write Buffer Working RAM in ECC Data Write Back

Hit Ratio Write Cache Effect 30.0% Cache Size Hit Ratio 25.0% 1MB 20.0% 2MB 15.0% 512KB 10.0% 5.0% 0.0% 0 1 2 3 4 5 6 7 8 9 Cache Size [MB]

Large L2P Table Cache Conventional Architecture Unified Memory Architecture (1) L2P Table Request DRAM main memory UFS HC UFS IF Controller ECC (2) L2P Table Entry (~ 50 msec) (1) L2P Table Request DRAM main memory UFS HC UFS IF Slave BUS IF Master IF Controller ECC DMA (2) L2P Table Entry (~ 0.5 msec) Large L2P Table Cache Working RAM in

Timing Chart of Random Read (A Single NAND Case) (UM Ext. OFF) Cmd A L2P table read Data read FW -> SLC tr -> L2P dataout from NAND - > FW -> MLC tr -> 4 KB dataout from NAND -> FW -> 4 KB dataout to HOST Cmd B Cmd C Cmd A Cmd B FW -> L2P data read from DRAM -> FW -> MLC tr -> 4 KB dataout from NAND -> FW -> 4 KB dataout to HOST Cmd C (UM Ext. ON) L2P table read Data read

Implementation (Protocol) UPIU SCSI compatible issues / Responds UMPIU Non-SCSI Issues / Responds

Conventional UFS Layer Application Layer UFS Command Set Layer (UCS) UPIU Manager (QueryRequest) UFS Native Command Set Simplified SCSI Command Set Future Extension Task Manager UDM_SAP UTP_CMD_SAP UTP_TM_SAP UFS Transport Protocol Layer (UTP) UIO_SAP UIC_SAP UFS InterConnect Layer (UIC) MIPI UniPro MIPI M-PHY

UMA UFS Layer Appended for UMA UPIU UMPIU

Spec. Roadmap 2011 2012 2013 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 UFS Spec. UFS1.0 UFS1.1 UFS2.0 UM Ext. Spec. Publish as UFS2.0 Additional Volume UME1.0 MIPI Spec. M-PHY1.0 Unipro1.40 M-PHY2.0 Unipro1.41 M-PHY3.0 Unipro1.60

UME System Validation Toshiba UFS UM Extension demo system, Apr. 2013 UFS with UME UFS with UME

Summary UFS Unified Memory Extension (Optional) Work memory In device controller In host system Protocol unit UPIU UMPIU Initiator Complexity - Extra communication Performance - Faster random access (NV memory << DRAM) Power consumption - Lower energy consumption (NV memory >> DRAM) Cost - Smaller device controller memory Standardization UFS 2.0 Sep., 2013 Unified Memory Extension 1.0 Sep., 2013

Thank You!