Test Application Time and Volume Compression through Seed Overlapping

Transcription

1 Test Application Time and Volume Compression through Seed verlapping ABSTRACT We propose in this paper an approach based on the Scan Chain Concealment technique to further reduce test time and volume. The scheme attempts to overlap consecutive test vector seeds thus providing increased flexibility in exploiting the large volume of don t-care bits in test vectors effectively. The proposed methodology introduces no extra hardware upon the existing SCC scheme, while it produces significant reductions over all current test compression techniques. Various implementation strategies have also been explored and an analysis is given for their distinct application. Experimental data show promising results on the proposed scheme. 1. INTRDUCTIN The rapid development of IC technologies has made it possible to put an increasing number of transistors on a single chip while at the same time delivering intense challenges to the test domain. Scan based design prevails as it enhances both controllability and observability with a limited number of input and output pins. However, in large circuits that necessitate long scan chains, scan based design is confronted with the problem of highly increased testing time and memory requirement, which consequently lead to high test cost. To attack this problem, a variety of schemes have been proposed for scan based designs to achieve test time and volume reductions. Through the process of test pattern generation, compaction is applied to compatible test cubes to decrease the size of the test vector set. The compaction of test vectors utilizes the fact that the majority of bits in most test cubes are unspecified, which increases the probability of mutual compatibility. While compaction focuses on reducing the number of test vectors, compression schemes aim at reducing the number of bits shifted per test vector. More generally, compression schemes try to apply a set of test vectors by inputting a reduced amount of data. Traditionally, data compression is accomplished by exploiting the redundant data or the unbalanced frequencies of various patterns. Statistical coding [1] and run-length coding [2] are well known software techniques that have been imported to the VLSI test domain. The fact that most bits in a test vector can be don t-cares turns out to be an important feature exploitable for compression. Hence, in the VLSI test domain, various schemes have been proposed to reduce test time and volume by utilizing the unspecified bits. The Scan Chain Concealment SCC compression scheme [] breaks a long scan chain into multiple partitions and uses an XR network to provide them with test vectors. The XR network uses limited input pins and expands a set of input seed vectors to all the scan chain partitions as a test vector. The feasibility of using a small amount of input data to generate the required test vectors stems from a well-constructed XR network and the large number of don t-care bits in the test vectors. The ratio of input to output pins of the XR decompression network determines the compression ratio of the SCC design, and thus is fixed. The SCC scheme provides a threshold during the ATPG process, based on which a compromise is made between compaction and compression to attain a fixed heuristic compression rate. Since the number of don t-care bits in each test vector determines the maximum possible compression rate for every test vector, providing the flexibility of adjusting the compression ratio according to the ratio of don t-care bits promises further reductions in test time and volume. Introducing further overlapping between the compressed vectors of the SCC design provides an additional dimension for compression rate adjustment, one that is inherently decided by the number of don t-care bits in the test vectors to be applied. In this paper we propose an approach to increase the compression rate for test time and test volume based on the SCC design, which enables the adjustment of the compression rate to fit the ratio of don tcare bits in test vectors. The experimental data shows evident improvements upon the previously suggested SCC technique [], the hitherto leading test compression technique. The paper is organized as follows: Section 2 gives an outline of previous work in the area of reducing test time and test volume. In Section we briefly review the SCC compression scheme. The proposed idea is described in Section 4 while Section 5 provides the test vector generation algorithm for the proposed idea. We show some experimental data in Section 6; Section summarizes the paper and draws a number of conclusions. 2. PREVIUS WRK A variety of approaches [4, 5, 6] have been proposed focusing on improving test vector compaction during the test pattern generation process. These approaches mainly aim at minimizing the test vector set by providing various heuristic ways of compacting test cubes, either statically or dynamically. Statistical coding and run length coding such as Huffman code [1] and Golomb code [2] have been studied and applied to the area of scan chain based testing as well [1, 2]. These approaches take test vectors as data to be compressed and apply compression schemes that exploit the varying frequency of patterns. The large number of don t-care bits existing in test vectors are assigned to preferred values accordingly to achieve high compression ratios. Different implementations of hardware decoder architectures have been proposed as well [1, 2]. n the other hand, some compression schemes start from the aspect that exploits the architecture of scan chain based designs [,, 9, ]. A long scan chain is usually partitioned into multiple smaller internal scan chains that can be fed simultaneously. A variety of strategies are provided to supply test vectors to the multiple internal scan chains through the limited input pins. The output of the multiple inner scan chains is usually compressed using a MISR and the signature is shifted out through the main output pins. Some approaches try to achieve compression by reusing the data within scan chains [10, 11]. By shifting in and out only a part of the scan chain, the number of bits needed to be shifted for each test cycle is reduced. In these approaches test vectors are either reordered statically by some heuristic algorithm to attain maximal overlapping

2 scan in Seed VectorN XR Network NxM Multi-Input Signature Register M Signature utput network it is usually feasible to solve the set of equations and find a suitable seed for the required output. The SCC test vector generation algorithm starts by generating a test cube for a fault in a fault list. Then it tries to compact test cubes for other faults in the list as long as finding seeds to acquire the test vector is possible. A test vector is then generated and its seeds are accordingly calculated. Fault simulation is then incorporated to drop other faults in the list that can be detected by the current generated test vector. The above process iterates until all or a certain percentage of the faults have been caught. With the SCC compression scheme, usually over 0% reduction in test volume and test time can be achieved. Test application time and volume reductions ranging from 12.9% to 5.1% over current schemes are reported in []. Figure 1: SCC architecture of hidden scan chains [11] or dynamically generated to ensure certain overlapping with the previous response [10].. PRELIMINARIES The SCC scheme develops a decompression network which decodes an bit seed from ATE and produces outputs to feed internal hidden scan chains on the circuit. The -bit seed forms an outer scan chain which is visible to the ATE and is shifted in at the start of every test cycle. The XR decompression network thus decodes the bits seed into an bit vector and shifts each bit into one internal hidden scan chain accordingly. If we suppose that the length of all the internal hidden scan chains is, then after such test cycles, all the internal hidden scan chains will have been fed with proper test vectors ready to be applied to the circuit. The test time and volume reduction ratio is thus to. It has been previously shown that test cubes or test vectors with a large number of unspecified bits can be encoded with an LFSR seed [12, ]. The decompression network in SCC can be built based on a LFSR sequence and implemented in a parallel way using an XR network to drive a high number of internal scan chains through a limited number of external pins. The scan chain architecture for SCC is depicted in Figure 1 while an example of a decompression XR network is shown in Figure 2. The seed of the XR decompression network for certain output vectors is calculated by solving a set of linear equations, the number of which is determined by the number of specified bits in the required output vector. The coefficients of the equations, however, are determined by the construction of the XR network. Thus, when the ratio of specified bits in a test vector is low, with a properly designed XR 4. VERLAPPING F SEEDS In the SCC scheme, the size of the outer scan chain together with the number of internal scan chains essentially decides the compression ratio, and the fixed ratio furthermore puts constraints on the capability of exploiting don t-care bits in compaction and compression. During the SCC test vector generation algorithm, the don t-care bits in test vectors are exploited through two stages: compaction at first and then compression. Since compaction is followed by compression, it needs to terminate at a certain point to guarantee the feasibility of compression, which demands a certain ratio of don t-care bits left over by compaction, due to the fixed ratio constraint. The exploitation of don t-care bits by compression, on the other hand, aims at the don tcare bits left over after compaction concludes. However, due to the fixed compression ratio, when the don t-care bits left over by compaction exceed the threshold, the maximum possible compression rate cannot be achieved. This situation usually happens in the later stages of the test vector generation process, where faults are not clustered together and test cubes cannot undergo a large amount of compaction, thus leaving test vectors with a large amount of don t-care bits while catching a small number of new faults. We introduce the seed overlapping scheme, which aims at further compression of test time and volume by providing the flexibility to fit the number of don t-care bits left over by compaction. Unlike the inner scan chains or an ordinary scan chain, an outer scan chain contains always a seed that is to be decoded for feeding multiple inner scan chains while no response is ever written back into the outer scan chain itself. Thus, it is feasible to apply overlapping between consequent seeds whenever possible to exploit further compression flexibly. The amount of overlapping that is achievable between certain seeds is essentially decided by the don t-care numbers in the expected next output vector. We show next the feasibility of overlapping between seeds in terms of matrix operations by an example. Figure illustrates a matrix representation of the XR network ex- S S 2 S 1 S = S = S2 S = S1 S2 S S1 S 2 S S1 S 2 S1 S S2 = S1 S S2 S = S S = S S 0 S 1 S 2 Figure 2: An example of XR network Figure : Matrix representation of XR network example

3 # # ' = ample shown previously in Figure 2. If we denote the seed vector as, the output vector as and the XR network matrix as, then the relationship between an output vector and its seed can be expressed as: Suppose the output vector needed contains four specified bits, such as x1xx0x1xx0. Thus, with only specified to 1010, the seed can be determined by utilizing the four rows in matrix corresponding to and. The seed vector is calculated by the reduced equation below corresponding to the rows for the specified bits : "! $# "% *,- **. /,.,*.,/1,*.,*- **- 0 The output vector is consequently fully specified 454 by the pseudoran- "2. To show the example of overlapping, we now consider the next out- dom fill of the XR matrix as put vector, *6, that follows. Let -6 be xx0x1xxxxx thus containings only two specified bits at and. We can then form the next seed vector by only shifting in two bits upon the previous seed, where "# % and! derived! from the shifting of former and. The newly shifted and can be calculated by solving the equation below.! : 9, *, * 0 <! 1** -*/ :-;,= * / & '! By solving the equation the output vector 6 can be 5 generated by shifting only half of the seed vector. The seed ? thus can specify the output vector -6 as -6 6@ A2. The example above shows the method applied so as to exploit the overlapping between seed vectors and also illustrates that the amount of overlapping between seeds matches the don t-care bit rate in the output vector. Instead of fully shifting in every seed vector, overlapping can be applied to every two adjacent seed vectors to reduce the required amount of shifting. In general, an XR network can be designed in a way that introduces no linear dependency among a small number of rows in the matrix X, thus making it always feasible to generate a seed that overlaps with the previous one in the amount that matches the number of don t-care bits in the output vector. The flexibility of changing the compression ratio according to the variety of don t-care bit ratio is therefore achieved through the proposed scheme. * / > 5. TEST GENERATIN ALGRITHM In order to exploit the large ratio of don t-care bits in test vectors to accomplish the compression of test time and volume, the test vector generation algorithm must be incorporated to guarantee the full coverage of faults. Since the proposed scheme aims at applying overlapping between seed vectors in the SCC scheme, the test vector generation algorithm in this work is based on the algorithm proposed in the SCC design with the appropriate modification made for the overlapping feature. Two distinct strategies can be applied in the test vector generation algorithm, and they are presented and discussed below. 5.1 Compaction first algorithm The compaction first algorithm is based on the strategy that tries to perform as much compaction as possible with the compression capability acting as a constraint. The compression capability is set to the maximum possible seed length, i.e. no overlapping between seeds, to help perform more compactions. Thus, no overlapping is assumed during the compaction stage and overlapping between seeds is subsequently attempted. We give the Compaction first algorithm for test vector generation below: B Compaction first algorithm 1. Select C! a fault from the fault list and generate a test cube that catches it. 2. Iterate for all faults in the C fault list: a Generate a test cube or use already generated test cube. C CD! b If is not compatible with, then go back to step 2. c If the resultant test cube C 6 is not compressible by a sequence of non-overlapped seed vectors, then go back to step 2. d Merge C and C! and store C 6 as C!.. Perform maximal possible overlapping between adjacent seeds for the current test pattern C!. 4. Perform fault simulation and drop detected faults from the fault list. 5. If undetected faults remain, go to step 1. In the algorithm, the iteration part of applying compaction first and compression afterwards is similar to the corresponding part in the SCC algorithm. Compaction is performed under the constraint that compression is using the full seed vector i.e. no overlapping is assumed. The resultant test cube is decomposed into a sequence of output vectors in step to be used for calculating and generating overlapped seed vectors. In this step, the maximal possible overlapping between every two adjacent seed vectors is analysed according to the number of don t-care bits in the next output vector. The sequence of overlapped seeds is computed by solving a set of matrix equation and thereby a sequence of output vectors is determined which essentially constitute the test vector. Fault simulation is then applied with the generated test vector and fault dropping is performed to get rid of the detectable faults. This process is iterated until no undetected fault remains in the fault list, thus guaranteeing full fault coverage. The algorithm described above exhibits most reduction in test time in terms of shifting cycles since the number of overlapping bits between two seeds can vary from 0 to to fit the don t-care bits ratio maximally. Test volume, in terms of test data that need to be stored on ATE, can be improved over the SCC design as well, although not as significantly as that of test time since a slight amount of additional information is needed to be stored to indicate the amount of shift for the

4 Compress first TPG Algorithm Compaction first TPG Algorithm none or half overlapping any length of overlapping Ptn Vol compress Time compress Ptn Vol compress Time compress Ptn Vol compress Time compress circuit num #bits cmp #bits cmp num #bits cmp #bits cmp num #bits cmp #bits cmp S % % % % % % S % % % % % % S % % % % % % S % % % % % % S % % % % % % Ave % % % % % % Table 1: Comparison between different strategies of test vector generation algorithms seeds. Use of a limited number of discrete shifting steps enables minimization of the communication necessary for directing the amount of shift, albeit at a slight deterioration of application time improvement. 5.2 Compression first algorithm An alternative algorithm tries to put a stricter constraint for compaction to guarantee improved compression. A fixed amount of overlapping is set as a constraint for compaction up to a predefined percentage of fault coverage. This constraint is subsequently loosened to enable the full shifting of seed vectors. The algorithm is shown below. B Compression first algorithm 1. Select a fault from the fault list and generate a test cube C! that catches it. 2. Iterate for all faults in the C fault list: a Generate a test cube or use already generated test cube. b If C is not compatible with CD!, go back to step 2. c If the resultant test cube C 6 is not compressible by a sequence of half-overlapped seed vectors, then go back to step 2. d Merge C and C! and store C 6 as C!.. Perform fault simulation and drop detected faults from the fault list. 4. If fault coverage threshold is not attained, go to step Perform the Compaction first algorithm for all the undetected faults in the fault list. The main structure of this algorithm is similar to the previous one, while the constraint for compaction is tightened to half-overlapping among seeds. With this stricter constraint, the number of test patterns that are needed may increase slightly, yet the threshold of fault coverage percentage can be adjusted to attain an optimal solution. 6. EXPERIMENTAL DATA ur experiment is carried out using ATALANTA [1] as the test cube generation tool and HPE [14] for fault simulation. The seed overlapping compression algorithm is implemented in a C program and is based on a reimplemented SCC compression scheme. We perform our scheme on the largest five ISCAS9 benchmark4 circuits with a randomly generated XR network of the size EGFIHJE. Thus, the length of a seed vector is 24 and the length of an output vector is 200, which further determines the number of internal scan chains in each circuit to be 200 as well. The length of each internal scan chain is 4 for the circuits S120 and S1550, 9 for S592 and S41 but for S54. In Table 1 we show a comparison between various test vector generation strategies. The Compression first algorithm is shown on the left part and the Compaction first algorithm is shown on the right. Within the Compaction first algorithm, two kinds of implementations are listed. The first one performs only one fixed form of overlapping half overlapping between seeds in Compaction first algorithm. Thus, either none or 12 bits of overlapping is applied in order to decrease the amount of data needed to indicate the length of shifting from ATE. The second one allows any length of overlapping from 0 to 2 between two seeds, thus exploiting the maximal possible compression on test time. Within each strategy, we list experimental data obtained under the strategy. The first column named Ptn num gives the number of test patterns required while the remaining columns contain data for test volume and test time compression. The column indicated by #bits shows the test volume in terms of number of bits or test time in terms of number of cycles. The number of bits in test volume is higher than the shifting cycles in test time due to the extra information needed for indicating the amount of overlapping. The column denoted cmp gives the compression ratio reduced by the compression scheme compared to the plain implementation of shifting all test patterns sequentially with no compression scheme applied. The number of test patterns necessary for a plain implementation without shifting is obtained from [], and the test time and volume are calculated as the multiplication of test pattern number and scan chain length. The best result for each circuit is indicated in bold phase. The experimental data is consistent with our analysis of the various strategies. In general, the Compression first algorithm generates slightly more test patterns while the Compaction first algorithm requires less. n the other hand, indicated by the number of bits in test volume, Compression first performs better than Compaction first. This is due to the reason that Compression first forces a fixed half overlapping until a certain percentage of faults has been covered, which requires less extra information on specifying overlapping bits. Also, for the same reason, the none or half overlapping strategy outperforms the any length of overlapping strategy in the Compaction first algorithm in test volume. However, with the increased freedom to perform any length of overlapping, the any length of overlapping strategy achieves best test time compression rate in most cases. The circuit S592 provides an exception due to the fact that its faults are trivial to detect and thus coverable by a very small set of test vectors. In spite of the difference, all strategies show a high reduction of around 5% on both test time and volume compared to a no compression scheme. In Table 2 we show the comparison of the proposed scheme to previous results in test application time reduction. The results from the Compaction first algorithm are used for the proposed scheme to aim

5 PSFS FDR SCC VSC Procircuit [] [15] [] [] posed imp S % S % S N/A % S % S % Ave % imp.% 40.%.% 4.4% without overlapped scheme circuit SCC over- test volume test time [] lapping #bits imp #bits imp S % % S % % S % % S % % S % % Ave % % Table 2: Test time reduction comparison with previous work at the best reduction for test application time. ther previous work included in the comparison are the Parallel Serial Full Scan PSFS, [], the Frequency Directed Run-Length FDR coding [15], the Scan Chain Concealment SCC [] and the Virtual Scan Chain VSC []. The best previous result for each circuit is shown in bold font, and an improvement percentage is listed in the last column based on the comparison to the best previous result for each circuit. The last row includes the improvement made by the proposed scheme compared to each of the previous works on average. Significant improvement is seen for the proposed technique compared to previous ones. To further investigate the reduction solely attributable to overlapping, we have performed a non-overlapping experiment with our implementation of SCC scheme. Due to the difference in implementation 1, the SCC approach we implemented outperforms the SCC on test time and volume in []. However, significant improvement in test time can still be obtained by performing overlapping. Test volume, although slightly increased by the extra information needed to indicate the amount of overlapping, still shows improvement by performing overlapping in general. The result is shown in Table. In this table, the column SCC [] shows the result from the SCC scheme from [] while the column without overlapping indicates the enhanced implementation of SCC yet without performing any overlapping. The rest of the columns show the results of the approach with overlapping performed from the aspects of both test volume and test time. The column #bits indicates test volume and test time in terms of bit number and shifting cycles while the column imp shows improvement ratios upon the approach without overlapping i.e. column.. CNCLUSIN A compression scheme based on the SCC design for test time and volume reduction is proposed. Through the overlapping of seeds the compression ratio is able to be adjusted according to the don t-care ratio within test vectors. The flexibility thereby achieved makes it possible to maximize the compression ratios of test time and volume. The methodology of performing seed overlapping is provided in this paper and several strategies of test vector generation algorithms are discussed accordingly. We provide three sets of experimental results. The set of results for comparison among various test pattern generation algorithm strategies exhibits consistency with our analysis. Another set of data provides a comparison between the proposed scheme and previous work, proving attainment of significantly elevated compression ratios with the proposed scheme as well as significant improvement compared to previous related work. The third set of results clearly confirms the promising improvement achieved through the proposed overlapping scheme. The variance originates from a difference in the outer scan chain length and code parameter definitions. Table : Reduction attributable solely to overlapping. REFERENCES [1] A. Jas, J. Ghosh-Dastidar and N. A. Touba, Scan Vector Compression/Decompression Using Statistical Coding, in VTS, pp , [2] A. Chandra and K. Chakrabarty, System-on-a-Chip Test- Data Compression and Decompression Architectures Based on Golomb Codes, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, n., pp. 55 6, March [] I. Bayraktaroglu and A. railoglu, Test Volume and Application Time Reduction Through Scan Chain Concealment, in DAC, pp , [4] I. Hamzaoglu and J. Patel, Test Set Compaction Algorithms for Combinational Circuits, in ITC, pp. 2 29, 199. [5] I. Pomeranz, L. Reddy and S. Reddy, CMPACTTEST: a Method to Compact Test Sets for Combinational Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, n., pp , July 199. [6] S. Bhatia and P. Varma, Test Compaction in a Parallel Access Scan Environment, in ATS, pp , 199. [] I. Hamzaoglu and J. Patel, Reducing Test Application Time for Full Scan Embedded Cores, in FTCS, pp , [] A. Jas, B. Pouya and N. A. Touba, Virtual Scan Chains: A Means for Reducing Scan Length in Cores, in ITC, pp., [9] S. Reda and A. railoglu, Reducing Test Application Time Through Test Data Mutation Encoding, in DATE, pp. 9, [10] omitted for blind review. [11] C. Su and K. Hwang, A Serial Scan Test Vector Compression Methodology, in ITC, pp. 91 9, 199. [12] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, Built-in Test for Circuits with Scan Based on Reseeding of Multiple-polynomial Linear Feedback Shift Registers, IEEE Transactions on Computers, vol. 44, n. 2, pp. 22 2, February [1] H. K. Lee and D. S. Ha, n the Generation of Test Patterns for combinational Circuits, Technical report 12-9, Dep t of Electrical Eng., Virginia Polytechnic Institute and State University, 199. [14] H. K. Lee and D. S. Ha, HPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits, in DAC, pp. 6 40, [15] A. Chandra and K. Chakrabarty, Test Resource Partitioning for SCs, IEEE Design & Test of Computers, vol. 1, n. 5, pp. 0 91, September/ctober 2001.