FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction
|
|
- Avice James
- 5 years ago
- Views:
Transcription
1 FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, and Tatsuo Ohtsuki Dept. of Computer Science Waseda University, Japan Grad. School of IPS Waseda University, Japan Abstract This paper proposes a new multiscan-based test input data compression technique by employing a Fan-out Compression Scan Architecture (FCSCAN) for test cost reduction. The basic idea of FCSCAN is to target the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression. Due to the low specified bit density in test cube set, FCSCAN can significantly reduce input test data volume and the number of required test channels so as to reduce test cost. The FCSCAN technique is easy to be implemented with small hardware overhead and does not need any special ATPG for test generation. In addition, based on the theoretical compression efficiency analysis, improved procedures are also proposed for the FCSCAN to achieve further compression. Experimental results on both benchmark circuits and one real industrial design indicate that drastic reduction in test cost can be indeed achieved. I. INTRODUCTION The central issue in manufacturing test has always been how to apply sufficient test data to a design to ensure that the highest quality is reached, while at the same time to minimize test cost. Nowadays, almost all of the current design-for-test (DFT) techniques start with a baseline of scan technology. However, the chip complexity continuous increasing, which results in excessive test data volume even for single-stuck-at faults with single-detection [1]. In conventional external testing, this huge amount of test data must be stored on the external automatic test equipment (ATE) and be transferred to and from the circuit-under-test (CUT) through the limited test channels. This poses a serious problem on manufacturing test because, as test data volume increases, it takes more tester buffer space to hold the complete test set, and longer to deliver the test set through limited test channels, both leading to higher test cost. Therefore, to reduce tester storage and tester channel bandwidth requirements for million-gates designs is recognized as an extremely important problem and, consequently, is receiving a lot of attention in the past five years. In the literature numerous papers have been published on test cost reduction using test data compression, which involves employing on-chip DFT structures to reduce the amount of data stored on the ATE and thereby shorten the time it takes to load or observe the scan chains. An important class of test data compression (TDC) techniques involves using an on-chip linear decompressor to decompress test vectors. This includes techniques based on linear feedback shift register (LFSR) reseeding [2, 3] and combinational linear expansion circuits [4]. There are also some commercial tools based on LFSR reseeding combined with on-chip decompression developed recently including Mentor Graphics TestKompress [5], Smart- BIST from IBM/Cadence [6] and Synopsys DBIST [7]. Unfortunately, although these techniques can achieve high compression ratios, for an efficient implementation, most of them need to be combined with fault simulation or interleaved with automatic test pattern generation (ATPG). Another group of compression techniques uses lossless source coding for test data reduction, such as selective Huffman coding [8], runlength coding [9], and dictionary coding [10]. However, when applied to multiscan-based designs, the effectiveness of these methods is limited either by the additional hardware overhead or or the increased test time. In addition, there are some methods focused on reducing external test channels to achieve great compression for designs with multiple scan chains. A technique using a single input supporting multiple scan chains was proposed in [11], but its application is limited to test multiple independent full scan circuits in parallel. The Illinois scan architecture [12] overcomes this limitation by using two modes of scan operation, parallel scan and serial scan. CircularScan [13] configures the scan chains in a circular form, enabling the generation of the next pattern from the captured response. CircularScan efficiently overcomes the tester channel bandwidth limitation, however it introduces a new problem on the test diagnosis process due to the undeterministic property of the test response. The approaches proposed in [14] and [15] explored the logic dependencies of the internal scan chains to construct a simple logic gates based decompression network, so that a great number of scan chains could be driven by a limited number of external scan channels and test cost is reduced. In this paper we propose a new DFT technique Fan-out Compression Scan Architecture (FCSCAN), to drastically reduce test cost for multiscan-based designs. The basic idea of the proposed FCSCAN technique is to only encode the minority specified 1 or 0 bits (either 1 or 0) (to be referred as coded bits in this paper) in scan slices for compression. While retaining the original number of scan chains, it drastically reduces input test data volume as well as the number of required test channels for precomputed test sets of multiscan-based designs so as to reduce test cost. To be mentioned that we assume
2 number of bits No. of specified bits No. of coded bits DCU + decoder init conf ms cck sck FCN number of test cubes Fig. 1. Test cube profile for one industrial circuit - ASIC 1 the test response could be compacted using a Multiple Input Signature Register (MISR) or some other techniques [16], and we only consider the input test data reduction in this work. The proposed FCSCAN technique is very easy to implement with small hardware overhead and it does not need any special ATPG for test generation. In addition, starting with the analysis on the compression efficiency of FCSCAN, improved procedures by exploring the linear dependencies of the internal scan chains are also proposed for further compression. Unlike previous works, the computation complexity is greatly reduced with better compression. Experimental results indicate that drastic reduction in test cost can be indeed achieved using the proposed FCSCAN technique. The rest of this paper is organized as follows: Section 2 presents the FCSCAN technique. Section 3 makes an analysis on the compression efficiency of the FCSCAN scheme and then describes the procedures for improvement. Finally experimental results and conclusions are given in Section 4 and 5, respectively. II. FCSCAN TECHNIQUE In practice, in an ATPG-based test set even with the application of state-of-the-art dynamic and static test pattern compaction techniques, only 1%-10% of the total test data is specified with logic values for fault detection, and the other larger part of bits are don t cares. One example is shown in Figure 1, where ASIC 1 is a real industrial circuit used in our work. Due to the large fraction of don t-cares in test set, most of the test input data compression techniques as referred above focus on the don t-cares and utilize them for test data compression. In our work, in addition to low specified bit densities, we have further studied the care bits information and found some other useful scan test properties. Specifically, in each scan slice, the number of the minority specified 1 or 0 bits (either 1 or 0) is definitely to be less than half of the total number of specified bits. In this paper we call the specified bits with the minority specified density in the current slice as coded bits and the coded bit density in the current slice, P ci, is equal to min(p i (0),P i (1)). Figure 1 also illustrates this observation for ASIC 1, where there are 128 scan chains and the specified bit density is 12%. It can be seen that the total number of MISR Fig. 2. The proposed fan-out compression scan (FCSCAN) architecture coded bits is much less than that of specified bits. With this important observation greater compression can be expected by loading only the coded bits information other than loading all the specified bits. Details will be illustrated as follows. Figure 2 shows the proposed FCSCAN architecture, which enables the scan chains to be assigned proper data through one of the two loading mode: broadcast mode and configuration mode. Broadcast mode all the internal scan chains are loaded the same value, which is similar to the parallel scan mode in Illinois Scan Architecture [12]. Configuration mode in this mode according to the values supplied from the test channels, an individual scan chain is selected to be inverted on the pre-loaded values in Broadcast mode. The proposed FCSCAN architecture mainly consists of a decompression control unit (DCU), a flip configuration network (FCN) and a log 2 N-to-N decoder. The DCU is a finite-state machine, which is responsible for controlling the decompression process, generating the mode selection signal ms and controlling the scan clock sck for the CUT. The flip configuration network is a combinational block composed of one XOR gate and one MUX for each internal scan chain. The multiplexers are controlled by the ms signal provided from DCU. When ms is 0, the FCSCAN is operated in broadcast mode, otherwise it runs in configuration mode. The i th bitofthelog 2 N-to-N decoder is XORed with the feedback of the first scan cell in the i th scan chain that allows for the pre-existing values to be kept or inverted in the scan cells of the associated chain. Based on the FCSCAN architecture, a compressed form of a scan slice contains the following: (1) an initial vector: to indicate the initial value for the scan cells (1 bit) and the number of coded bits in the current slice (M-1 bits). Since the number of internal scan chains is N sc and the number of coded bits in any scan slice would be less than 0.5 N sc, when M = log 2 N sc, it can guarantee a regular test application. (2) configuration vectors: to indicate the positions of the coded bits needed by the decompressor to specify an inversion on any bits in the current slice.
3 TABLE I FCSCAN COMPRESSION EXAMPLE c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 s1: X X X X s2: 1 0 X X X X s3: 1 X 0 1 X X X X X X s4: X 1 X 0 X s5: X 0 X 1 X X 1 1 X 1 s6: 0 X 0 X X 0 X X 0 X s7: X 1 1 X X X X X X X s8: 1 X X 0 X 1 1 X 1 X (a) init vector conf. vector final vec s s s s s s s s (b) Example I - Table I (a) shows an example of test data for multiple scan chains. There are 10 scan chains (c 1, c 2,...,c 10 ) and 8 scan slices (s 1, s 2,...,s 8 ). In the proposed method, instead of using 10 external test channels, only 4 are used. Look at the second slice (s 2 ), in the first stage, we load an initial vector i 2 =1011 to the decompressor. In this paper we assume the leftmost bit of the initial vector is the initial value for the current slice, and the other three bits are used to indicate the number of coded bits, which is 011 (i.e. there are three bits to be flipped). Thus by clocking cck as shown in Figure 2, the scan cells are filled with the same logic values as the initial data (i.e. the current content in the scan cells is v = ). In the second stage, we load the configuration vector vc 1 = 0010 into the decompressor, and clock cck again. Thus the conf signal is , and an XOR operation is performed on the conf signal with the previously loaded scan slice v. Then the second bit position of the v is flipped while at the same time the counter is decremented. The configuration process is repeated until the counter reaches zero. Then in the next cycle, shift the current slice into the next scan cells by enabling the clock sck; while at the same time comes the next initial block i 3 = The compressed test data is shown in Table I (b). In our work the decompression logic is implemented in VHDL and synthesized using Synopsys design compiler to access the hardware overhead of the decompressor. The synthesized circuit (DCU) for the above example only contains two flip flops and 19 combinational gates, which is very small. III. OPTIMIZATION FOR FURTHER COMPRESSION In this section we first make an analysis on the compression efficiency of the proposed FCSCAN technique, from which we derive that the compression efficiency is affected by two parameters, such as the number of test channels and the total number of coded bits. Consequently, an optimized solution is proposed to further the compression through reducing the two parameters. A. Compression Analysis In our work, we use the compression ratio γ to analyze the compression efficiency, which is defined as the ratio of the compressed data volume ( T E ) to the original uncompressed data size ( T D ) (i.e. γ = T E / T D ), where γ must always be less than unity for the compression method to be effective. Equation 1 computes the number of bits in the compressed test set ( T E ) using the proposed FCSCAN technique. T E = N v N sl M (1 + n i,j ) (1) i=1 j=1 Where M is the number of external scan channels, N v is the total number of test patterns, N sl represents the maximum scan length, and n i,j is equal to the number of coded bits in slice s i,j. The compression ratio γ therefore can be calculated as following. γ = N v N sl i=1 j=1 M (1 + n i,j ) N v N sl N sc = M N sc + M P c (2) Where the product of N v N sl N sc amounts to the uncompressed test data volume T D, while P c is the coded bit density that is equal to the total number of coded bits divided by T D. Look at the example shown in Table I again, where N sc = 10, M =4and for the 8 test cubes the number of coded bits is (1, 3, 1, 3, 1, 0, 0, 1) respectively. Thus the coded bit density is 10/80 = 12%, the total number of test data after compression is 72 bits and for this example we can achieve 10% savings in the test data volume. Since this test data example is very small and the filling rate (P s = 48%) is relatively high when compared with typical industry designs (P s 1% 10%), greater compression could be expected for the larger circuits. For example, if we have a CUT with 1000 scan chains and the average filling rate is 10%, using the proposed FCSCAN scheme only 10 external test channels are required for a regular test application. Furthermore, in the worst case (i.e. P c 0.5 P s =5%) our method can still achieve 49% reduction in test input data volume no matter whether the specified bit distribution is uniform or non-uniform. As can be seen from Equation 2, the compression efficiency of FCSCAN depends on two parameters, such as the number of test channels (M) and the total number of coded bits N v N sl (N c = n i,j ). If the required test channels M and/or i=1 j=1 the total number of coded bits decreases, then the compression level will increase provided further reduction in test cost. Reducing M can help to reduce the number of bits for both initial vectors and configuration vectors, while reducing total number of coded bits could be used to decrease the number of configuration vectors. An improved solutions based on the FCSCAN scheme is presented in the following subsections, while keep both of these parameters intact.
4 1. For a precomputed test set, descendingly sort the scan chains according to the number of specified bits S =(c 1,c 2,...,c n) and SC = ; 2. Loop until no entry left in S i) select the first entry c k in S; ii) for each c i in SC iii) iv) if (d(c k,k i)=0or d(c k,k i)=n sc) // d: hamming distance update k i and delete c k from S; else copy c k to SC and delete it from S; 3. According to the logic dependencies between scan chain inputs, build the fan-out network only with inverters. Fig. 3. Scan chain clustering algorithm B. Minimizing Required Test Channels The first step is to minimize the required test channels (M). This is achieved by exploiting the compatibilities among the internal scan chains for a given test set to construct a simple fan-out structure between the decompressor output and the scan chains. In the literature, there are a number of published papers based on constructing such a simple logic fan-out network structure through compatibility analysis for test cost reduction. Our method generalizes the design techniques introduced in [17, 14] by constructing a single-level fan-out structure with inverters. This structure is chosen because it is very low cost, but still capable of achieving significant compression for the proposed FCSCAN technique. Figure 4(a) shows an example of such a network through exploiting the compatibility and inverse compatibility of the internal scan chains. To build such a fan-out structure needs to divide the internal scan chains into scan clusters, which can be viewed as a clique-partitioning problem such as illustrated in [15, 14]. However due to the NP completeness of the clique covering problem, finding an optimal solution might require exponential time. Therefore a simple heuristic summarized in Figure 3 has been developed. The proposed scan chain clustering (SCC) algorithm has two steps. In the first step, it descendly sorts the scan input of each internal scan chain into S according to the corresponding number of specified bits. The computation complexity of this step is O(n 2 ), where n is the number of scan chains. In the second step, initially the scan cluster set SC is empty, and the first scan chain input c 1 in S is moved from S to SC as the first entry (k 1 ). Then the remaining scan chain inputs (c i ) are analyzed one by one according to their corresponding hamming distance with the entries in SC. If the hamming distance between c i and k k is 0 or N sc, i.e. c i and k k are directly/inversely compatible, then remove c i from SC and properly fill the don tcares in k k ; otherwise copy c i to SC and delete it from S. This process is repeated until the set S is empty. In addition, we also set some constraints in our algorithm because our goal is to divide the N sc internal scan chains into m scan clusters, where log 2 m < log 2 Nsc, so as to reduce M. Thus when the number of entries in SC is larger than 2 log 2 Nsc, the process is stopped. To do this is very useful, because it can not only help to reduce the useless computation but also preserve the compression space. The computation complexity k 1 k 2 k 3 k 4 c 1 c 6 c 4 c 8 c 9 c 10 c 2 c 7 c 3 c 5 (a) init vec conf. vec scan in k i final vec c i s s s s s s s s (b) Fig. 4. Compression example using scan chain clustering (a)single-level fan-out structure with inverters and (b) the compressed data with final test set of this step is O(n log 2 n), where n = N sc, therefore the total computation complexity of the proposed SCC algorithm is: O(n 2 )+O(n log 2 n) O(n 2 ). While for the previous approaches based on scan chains clustering such as [14, 15], the computation complexity is O(n 4 ) and O(n 3 ) respecively. Example II - We use the same test data as in Table I. Initially, N sc is 10, so we set the constraint to the number of scan clusters, when m>7 the procedure is terminated. Then the SCC algorithm is applied, which divides the 10 scan chains into 4 scan clusters k 1 = {c 1,c 6 }, k 2 = {c 4,c 8,c 9,c 10 }, k 3 = {c 2,c 7 } and k 4 = {c 3,c 5 }, as shown in Figure 4(a). Three scan inputs can fan out to 10 scan chains, thus M is reduced from 4 to 3. Figure 4(b) shows the corresponding compressed data with the final fully specified test vectors. In this example, the total number of test data after compression is 48 bits, and we can achieve 40% savings in the test data volume. When compared with that in Example I, 24 bits are reduced. In addition, the number of coded bit is reduced from 10 to 8. This is an additional benefit of the scan chain clustering algorithm. C. Reducing Coded Bits While dividing scan chains into directly/inversely compatible scan clusters provides a lot of benefits for test cost reduction, we can achieve additional compression by reducing the number of coded bits for the FCSCAN scheme. Since the basic idea of the FCSCAN is to encode the minority specified 1 or 0 bits (either 1 or 0) in scan slices for compression, we can alter and reshape the space of the scan inputs (i.e. the output space of the decompressor) by inserting some appropriate inverters. Figure 5 shows the procedure how to reshape the scan inputs to reduce the total number of coded bits. Our heuristic seeks to
5 1. Counting the number of coded bits for each scan inputs (k i); 2. Loop until for each scan input, the number of coded bits is less than half of the number of specified bits (k i < 0.5 s i) i) select k j with the maximum coded bits; ii) invert k j; iii) add an inverter to the fan-out structure; iv) re-counting k i for each scan inputs; 3. Optimization for reducing the number of inverters. Fig. 5. Heuristic for coded bits reduction k 1k 2k 3k 4 k 1k 2k 3k 4 k 1k 2 k3k X X10X X XX X (a) (b) (c) k 1 k 2 k 3 k 4 c 1 c 6 c 4 c 8 c 9 c 10 c 2 c 7 c 3 c 5 Fig. 6. Example for reducing coded bits (d) reduce the number of coded bits in the scan clusters extracted from Section 3.2 by adding appropriate inverters between the decompressor and the fan-out structure. Example III - Figure 6 illustrates the example how to reduce coded bits for the previous test data after scan clustering. Figure 6 (a) shows the test data after scan chain clustering, in which there are some don -cares left. After carefully filling the don t-cares, the number of coded bits is 7 as shown in Figure 6 (b). Since k 2 has 4 coded bits, which is larger than half of its specified bits (i.e. 7 bits). Then k 2 is inverted, and now the total number of coded bits for the whole test set is reduced to 5 when carefully fill the left don t-cares as shown in Figure 6 (c). When compared with Example II, three coded bits are reduced with only one additional inverter. IV. EXPERIMENTAL RESULTS In this section, we present experimental results for the five largest ISCAS 89 benchmark circuits and one real industry design (ASIC 1) to validate the effectiveness of the proposed FC- SCAN technique. For each circuit, a commercial ATPG tool is used to generate test cubes with dynamic and static compaction providing 100% coverage of detectable faults. In our work, We first apply the scan clustering technique to minimize the number of required channels based on the test cube set, and then use the method proposed in Section 3.3 to reduce the number of coded bits and construct the fan-out structure using inverters. Finally the basic FCSCAN technique is applied. Table II presents the results on the compression efficiency of the proposed FCSCAN technique for the six circuits with varying number of scan chains. In the table, the name of circuits, the internal scan cells, and the number of test vectors are shown in the first three columns, respectively. Because we focus on test cost reduction for large designs with multiple scan chains, thus we set the number of scan chains to be 50, 100 and 200 as representatives for the benchmark circuits and 100,200 and 400 for ASIC 1. The size of uncompressed test data ( T D ) is shown followed by the average specified bit density (P s ) and the varying number of scan chains (N sc ). The compressed results for the basic FCSCAN scheme and the improved technique proposed in Section 3 are also listed, where T E and M are the compressed data size and the number of external test channels, respectively. In the improved scheme column, cluster indicates the number of scan clusters after applying the heuristic of Figure 3, and the number of added inverters is also summarized. Because we assume that the scan chains already exist in the CUT and scan chain reordering is prohibited, the data shown for FCSCAN do not use the scan chain reordering methods. From the table, we can observe that as the number of scan chains increases, FCSCAN leads to greatly reduced input test data volume with small hardware overhead. It is notable that for the four largest benchmark circuits (s15850, s35932, s38417 and s38584), the volume of compressed test data is less than the number of specified bits in the original test set. Table 3 shows a comparison of the results for the proposed method with CircularScan [13], 9C coding [19], Dictionary Coding with Correction (DCC) [20] and Frugal Linear network (FLN) [14], which are the representatives of the recently introduced test data compression schemes. The result of the Mintest ATPG-compacted test sets [18] is also listed for the sake of comparison. The result listed for the proposed method is the minimum size shown in boldface in Table II. Since different ATPG tools may be used, Table 3 shows both the number of vectors and the total number of compressed bits for each case. As can be seen from the table, the results obtained using the proposed FCSCAN scheme are better than those of CircularScan [13] and DCC [20] for all the circuits. When compared with 9C coding [19] and FLN [19], our method achieves higher compression for all but one of the circuits (s35932). We should note that when compared with industrial designs, the used benchmark circuits are very smaller in size and the specified bit density is relatively higher, which will limit the compression efficiency of the proposed FCSCAN technique. Finally, it must be mentioned that although the proposed FC- SCAN is very easy to implement, it really leads to drastic reduction in test cost, reducing both test data volume and the test channel requirement, which is especially effective for the designs with a great number of scan chains. V. CONCLUSIONS We have presented a FCSCAN technique that can reduce both input test data volume and external test channel requirement with small hardware overhead for large designs. Improved procedures have also been proposed to help the FC- SCAN to further the compression. Experimental results for the
6 TABLE II COMPRESSION RESULTS OF FCSCAN No. of No. of Size of P s FCSCAN Improved FCSCAN Circuits FFs vectors original bits (%) N sc M T E cluster M T E P c No. of inverters s , % , , % , , % , , % 46 s % , , % , , % , , % 48 s , % , , % , , % , , % 35 s , % , , % , , % , , % 29 s , % , , % , , % , , % 47 ASIC ,972,182 12% , , % , , % , , % 58 TABLE III COMPARISON WITH PREVIOUS WORKS Mintest [18] Circular Scan [13] 9C [19] DCC [20] FLN [14] Proposed Circuits vectors T E vectors T E vectors T E vectors T E vectors T E vectors T E s , , , , , ,290 s , , , , , ,072 s , , ,029 N/A N/A ,045 s , , , , , ,550 s , , , , , ,020 larger benchmark circuits and a real industrial ASIC demonstrate that FCSCAN provides significant improvement over other recent works. One notable result is that the test data volume could be reduced to less than or close to the number of specified bits in the original test set. REFERENCES [1] H. Furukawa F. Hsu S. Lin S. Tsai K. Abdel-hafez L. Wang, X. Wen and S. Wu. VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. In Proceedings IEEE International Test Conference (ITC), pages , October [2] J. Rajski S. Hellebrand and el. Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers. IEEE Transactions on Computers, 44(22): , February [3] B. Pouya A. Jas and N. A. Touba. Virtual scan chains: a means for reducing scan length in cores. In Proceedings IEEE VLSI Test Symposium (VTS), pages 73 78, May [4] I. Bayraktaroglu and A. Orailoglu. Test volume and application time reduction through scan chain concealment. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages , June [5] M. Kassab J. Rajski, J. Tyszer and N. Mukherjee. Embedded Deterministic Test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(5): , May [6] B. Koenemann et al. A smartbist variant with guaranteed encoding. In Proceedings IEEE Asian Test Symposium (ATS), pages , November [7] S.Patel P.Wohl, J.Waicukauski and M.Amin. Efficient Compression and Application of Deterministic Patterns in a Logic BIST architecture. In Proceedings ACM/IEEE Design Automation Conference (DAC), pages , June [8] M.-E. Ng A. Jas, J. Ghosh-Dastidar and N. A. Touba. An Efficient Test Vector Compression Scheme Using Selective Huffman Coding. IEEE Transactions on Computer-Aided Design, 22(6): , November [9] A. Chandra and K. Chakrabarty. Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression. In Proceedings IEEE VLSI Test Symposium (VTS), pages 42 47, May [10] K. Chakrabarty L. Li and N. Touba. Test data compression using dictionaries with selective entries and fixed-length indices. ACM Transactions on Design Automation of Electronic Systems, 8(4): , October [11] J.-J. Chen K.-J. Lee and C.-H. Huang. Using a single input to support multiple scan chains. In Proceedings International Conference on Computer-Aided Design (ICCAD), pages 74 78, November [12] K. Butler F. Hsu and J. Patel. A case study on the implementation of the Illinois scan architecture. In Proceedings IEEE International Test Conference (ITC), pages , October [13] B. Arslan and A. Orailoglu. CircularScan A Scan Architecture for Test Cost Reduction. In Proceedings Design, Automation, and Test in Europe (DATE), pages , March [14] A. Orailoglu W. Rao and G. Su. Frugal Linear Network-Based Test Decompression for Drastic Test Cost Reduction. In Proceedings International Conference on Computer-Aided Design (ICCAD), pages , November [15] S. Kajihara L. Li, K. Chakrabarty and S. Swaminathan. Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. In Proceedings IEEE VLSI Design (VLSID), pages 53 58, January [16] S. Mitra and K. S. Kim. X-Compact: An efficient response compaction technique for test cost reduction. In Proceedings IEEE International Test Conference (ITC), pages , October [17] C. Chen and S. Gupta. A methodology to design efficient BIST test pattern generators. In Proceedings IEEE International Test Conference (ITC), pages , October [18] I. Hamzaoglu and J. H. Patel. Test set compaction algorithms for combinational circuits. In Proceedings IEEE International Test Conference (ITC), pages , October [19] M. Nourani M. Tehranipour and K. Chakrabarty. Nine-coded Compression Technique with Application to Reduced Pin-count Testing and Flexible On-chip Decompression. In Proceedings Design, Automation, and Test in Europe (DATE), pages , March [20] C. S. Tautermann A. Wurtenberger and S. Hellebrand. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. In Proceedings IEEE International Test Conference (ITC), pages , October 2004.
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering
More informationReconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center University of Texas at Austin {kjbala,touba}@ece.utexas.edu
More informationTest Data Compression Using Dictionaries with Fixed-Length Indices
Test Data Compression Using Dictionaries with Fixed-Length Indices Lei Li and Krishnendu Chakrabarty Department of Electrical and Computer Engineering Duke University, Durham, NC 27708 {ll, krish}@ee.duke.edu
More informationTest Data Compression Using Dictionaries with Selective Entries and Fixed-Length Indices
Test Data Compression Using Dictionaries with Selective Entries and Fixed-Length Indices LEI LI and KRISHNENDU CHAKRABARTY Duke University and NUR A. TOUBA University of Texas, Austin We present a dictionary-based
More informationTest Application Time and Volume Compression through Seed Overlapping
Test Application Time and Volume Compression through Seed verlapping ABSTRACT We propose in this paper an approach based on the Scan Chain Concealment technique to further reduce test time and volume.
More informationEfficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition
Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition Jinkyu Lee and Nur A. Touba Computer Engineering Research Center University of Teas, Austin, TX 7872 {jlee2, touba}@ece.uteas.edu
More informationWITH integrated circuits, especially system-on-chip
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006 1227 Improving Linear Test Data Compression Kedarnath J. Balakrishnan, Member, IEEE, and Nur A. Touba, Senior
More informationTEST cost in the integrated circuit (IC) industry has
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 8, AUGUST 2014 1219 Utilizing ATE Vector Repeat with Linear Decompressor for Test Vector Compression Joon-Sung
More informationScan-Based BIST Diagnosis Using an Embedded Processor
Scan-Based BIST Diagnosis Using an Embedded Processor Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas
More informationTest-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns Anders Larsson, Erik Larsson, Krishnendu Chakrabarty *, Petru Eles, and Zebo Peng Embedded
More informationTEST DATA COMPRESSION BASED ON GOLOMB CODING AND TWO-VALUE GOLOMB CODING
TEST DATA COMPRESSION BASED ON GOLOMB CODING AND TWO-VALUE GOLOMB CODING Priyanka Kalode 1 and Mrs. Richa Khandelwal 2 1 Department of Electronics Engineering, Ramdeobaba college of Engg and Mgt, Nagpur
More informationEMBEDDED DETERMINISTIC TEST FOR LOW COST MANUFACTURING TEST
EMBEDDED DETERMINISTIC TEST FOR LOW COST MANUFACTURING TEST Janusz Rajski, Jerzy Tyszer *, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski
More informationCompression-based SoC Test Infrastructures
Compression-based SoC Test Infrastructures LIRMM, Univ. Montpellier II/CNRS, 161 rue Ada, 34932 Montpellier cedex 5, France {dalmasso, flottes, rouzeyre}@lirmm.fr Abstract. Test Data Compression techniques
More informationOn Using Machine Learning for Logic BIST
On Using Machine Learning for Logic BIST Christophe FAGOT Patrick GIRARD Christian LANDRAULT Laboratoire d Informatique de Robotique et de Microélectronique de Montpellier, UMR 5506 UNIVERSITE MONTPELLIER
More informationDelay Test with Embedded Test Pattern Generator *
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 29, 545-556 (2013) Delay Test with Embedded Test Pattern Generator * Department of Computer Science National Chung Hsing University Taichung, 402 Taiwan A
More informationTAM design and Test Data Compression for SoC Test Cost Reduction
TAM design and Test Data Compression for SoC Test Cost Reduction Julien DALMASSO, Marie-Lise FLOTTES, Bruno ROUZEYRE LIRMM, UMR5506 CNRS/Université Montpellier II 161 rue Ada, 34932 Montpellier cedex 5,
More informationA Novel Test Data Compression Algorithm
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn : 2278-800X, www.ijerd.com Volume 5, Issue 5 (December 2012), PP. 08-18 A Novel Test Data Compression Algorithm Ms.K.Hemalatha
More informationLow Power Test-Compression for High Test-Quality and Low Test-Data Volume
2011 Asian Test Symposium Low Power Test-Compression for High Test-Quality and Low Test-Data Volume Vasileios Tenentes, Xrysovalantis Kavousianos Dept. of Computer Science, University of Ioannina, Greece,
More informationRTL Scan Design for Skewed-Load At-Speed Test under Power Constraints
RTL Scan Design for Skewed-Load At-Speed Test under Power Constraints Ho Fai Ko and Nicola Nicolici Department of Electrical and Computer Engineering McMaster University, Hamilton, ON, L8S 4K1, Canada
More informationAt-Speed Scan Test with Low Switching Activity
21 28th IEEE VLSI Test Symposium At-Speed Scan Test with Low Switching Activity Elham K. Moghaddam Department of ECE, University of Iowa, Iowa City, IA 52242 ekhayatm@engineering.uiowa.edu Janusz Rajski
More informationA Technique for High Ratio LZW Compression
A Technique for High Ratio LZW Compression Michael J. Knieser Francis G. Wolff Chris A. Papachristou Daniel J. Weyer David R. McIntyre Indiana University Purdue University Indianapolis Case Western Reserve
More informationA Reconfigured Twisted Ring Counter Using Tristate Coding For Test Data Compression
A Reconfigured Twisted Ring Counter Using Tristate Coding For Test Data Compression 1 R.Kanagavalli, 2 Dr.O.Saraniya 1 PG Scholar, 2 Assistant Professor Department of Electronics and Communication Engineering,
More informationAn Efficient Test Relaxation Technique for Synchronous Sequential Circuits
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits Aiman El-Maleh and Khaled Al-Utaibi King Fahd University of Petroleum and Minerals Dhahran 326, Saudi Arabia emails:{aimane, alutaibi}@ccse.kfupm.edu.sa
More informationSpecial ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST Madhavi Karkala Nur A. Touba Hans-Joachim Wunderlich Computer Engineering Research Center Computer Architecture Lab Dept. of Electrical
More informationDeterministic BIST ABSTRACT. II. DBIST Schemes Based On Reseeding of PRPG (LFSR) I. INTRODUCTION
Deterministic BIST Amiri Amir Mohammad Ecole Polytechnique, Montreal, December 2004 ABSTRACT This paper studies some of the various techniques of DBIST. Normal BIST structures use a PRPG (LFSR) to randomly
More informationA Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods Kanad Basu 1 and Prabhat Mishra 2
A Novel Test-Data Compression Technique using Application-Aware Bitmask and Selection Methods Kanad Basu 1 and Prabhat Mishra 2 Computer and Information Science and Engineering Department University of
More informationA Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis Chunsheng Liu and Krishnendu Chakrabarty Department of Electrical & Computer
More informationGate Level Fault Diagnosis in Scan-Based BIST
Gate Level Fault Diagnosis in Scan-Based BIST Ismet Bayraktaroglu Computer Science & Engineering Department University of California, San Diego La Jolla, CA 92093 ibayrakt@csucsdedu Alex Orailoglu Computer
More informationDeterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor
JOURNAL OF ELECTRONIC TESTING: Theory and Applications 18, 503 514, 2002 c 2002 Kluwer Academic Publishers. Manufactured in The Netherlands. Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip
More informationTest Data Compression Using Variable Prefix Run Length (VPRL) Code
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 2, Ver. I (Mar-Apr. 2014), PP 91-95 e-issn: 2319 4200, p-issn No. : 2319 4197 Test Data Compression Using Variable Prefix Run Length
More informationTest Data Compression Using a Hybrid of Bitmask Dictionary and 2 n Pattern Runlength Coding Methods
Test Data Compression Using a Hybrid of Bitmask Dictionary and 2 n Pattern Runlength Coding Methods C. Kalamani, K. Paramasivam Abstract In VLSI, testing plays an important role. Major problem in testing
More informationCore-Level Compression Technique Selection and SOC Test Architecture Design 1
17th Asian Test Symposium Core-Level Compression Technique Selection and SOC Test Architecture Design 1 Anders Larsson +, Xin Zhang +, Erik Larsson +, and Krishnendu Chakrabarty * + Department of Computer
More informationALTERING A PSEUDO-RANDOM BIT SEQUENCE FOR SCAN-BASED BIST
ALTERING A PSEUDO-RANDOM BIT SEQUENCE FOR SCAN-BASED BIST Nur A. Touba* and Edward J. McCluskey Center for Reliable Computing Departments of Electrical Engineering and Computer Science Stanford University
More informationA Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing Anders Larsson, Erik Larsson, Petru Eles, and Zebo Peng Embedded Systems Laboratory Linköpings Universitet SE-582 83 Linköping,
More informationSystem-on-Chip Test Data Compression Based on Split-Data Variable Length (SDV) Code
Circuits and Systems, 2016, 7, 1213-1223 Published Online June 2016 in SciRes. http://www.scirp.org/journal/cs http://dx.doi.org/10.4236/cs.2016.78105 System-on-Chip Test Data Based on Split-Data Variable
More informationReducing Control Bit Overhead for X-Masking/X-Canceling Hybrid Architecture via Pattern Partitioning
Reducing Control Bit Overhead for X-Masking/X-Canceling Hybrid Architecture via Pattern Partitioning Jin-Hyun Kang Semiconductor Systems Department Sungkyunkwan University Suwon, Korea, 16419 kangjin13@skku.edu
More informationHow Effective are Compression Codes for Reducing Test Data Volume?
How Effective are Compression Codes for Reducing Test Data Volume Anshuman Chandra, Krishnendu Chakrabarty and Rafael A Medina Dept Electrical & Computer Engineering Dept Electrical Engineering & Computer
More informationStatic Compaction Techniques to Control Scan Vector Power Dissipation
Static Compaction Techniques to Control Scan Vector Power Dissipation Ranganathan Sankaralingam, Rama Rao Oruganti, and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer
More informationEfficient Algorithm for Test Vector Decompression Using an Embedded Processor
Efficient Algorithm for Test Vector Decompression Using an Embedded Processor Kamran Saleem and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University
More informationAn Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture
An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture Elaheh Sadredini,, Reza Rahimi, Paniz Foroutan, Mahmood Fathy and Zainalabedin Navabi el_sadredini@comp.iust.ac.ir, g_rahimi@ce.sharif.edu,
More informationDesign for Test of Digital Systems TDDC33
Course Outline Design for Test of Digital Systems TDDC33 Erik Larsson Department of Computer Science Introduction; Manufacturing, Wafer sort, Final test, Board and System Test, Defects, and Faults Test
More information1 Introduction & The Institution of Engineering and Technology 2008 IET Comput. Digit. Tech., 2008, Vol. 2, No. 4, pp.
Published in IET Computers & Digital Techniques Received on 15th May 2007 Revised on 17th December 2007 Selected Papers from NORCHIP 06 ISSN 1751-8601 Architecture for integrated test data compression
More informationTesting Embedded Cores Using Partial Isolation Rings
Testing Embedded Cores Using Partial Isolation Rings Nur A. Touba and Bahram Pouya Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas, Austin, TX
More informationPower-Mode-Aware Buffer Synthesis for Low-Power Clock Skew Minimization
This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Power-Mode-Aware Buffer Synthesis for Low-Power
More informationContents 1 Basic of Test and Role of HDLs 2 Verilog HDL for Design and Test
1 Basic of Test and Role of HDLs... 1.1 Design and Test... 1.1.1 RTL Design Process... 1.1.2 Postmanufacturing Test... 1.2 Test Concerns... 1.2.1 Test Methods... 1.2.2 Testability Methods... 1.2.3 Testing
More informationA Controller Testability Analysis and Enhancement Technique
A Controller Testability Analysis and Enhancement Technique Xinli Gu Erik Larsson, Krzysztof Kuchinski and Zebo Peng Synopsys, Inc. Dept. of Computer and Information Science 700 E. Middlefield Road Linköping
More informationEfficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering
Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering Aiman El-Maleh, Saqib Khurshid King Fahd University of Petroleum and Minerals Dhahran, Saudi Arabia
More informationA New Optimal State Assignment Technique for Partial Scan Designs
A New Optimal State Assignment Technique for Partial Scan Designs Sungju Park, Saeyang Yang and Sangwook Cho The state assignment for a finite state machine greatly affects the delay, area, and testabilities
More informationTwo Pattern Test Cubes for Transition Path Delay Faults Test for ISCAS-85 C432
Two Pattern Test Cubes for Transition Path Delay Faults Test for ISCAS-85 C432 T.Vishnu Murty 1, G.Seetha Mahalakshmi 2 M.Tech, Asst. Professor, Dept of Electronics & Communication Engineering, Pragati
More informationDUE TO innovations in the manufacturing technology of
274 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 35, NO. 2, FEBRUARY 2016 Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression
More informationLow-Power Weighted Pseudo-Random BIST Using Special Scan Cells
Low-Power Weighted Pseudo-Random BIST Using Special Scan Cells Shalini Ghosh 1, Eric MacDonald 2, Sugato Basu 3, and Nur A Touba 1 1 Dept of Electrical & Computer Engg University of Texas at Austin Austin,
More informationA Universal Test Pattern Generator for DDR SDRAM *
A Universal Test Pattern Generator for DDR SDRAM * Wei-Lun Wang ( ) Department of Electronic Engineering Cheng Shiu Institute of Technology Kaohsiung, Taiwan, R.O.C. wlwang@cc.csit.edu.tw used to detect
More informationBit-Fixing in Pseudorandom Sequences for Scan BIST
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 4, APRIL 2001 545 Bit-Fixing in Pseudorandom Sequences for Scan BIST Nur A. Touba, Member, IEEE, and Edward J.
More informationAS FEATURE sizes shrink and designs become more complex,
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 10, OCTOBER 2004 1447 Identification of Error-Capturing Scan Cells in Scan-BIST With Applications to System-on-Chip
More informationMULTIPLE FAULT DIAGNOSIS FOR HIGH SPEED HYBRID MEMORY ARCHITECTURE
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 2, Issue. 5, May 2013, pg.33
More informationLossless Compression using Efficient Encoding of Bitmasks
Lossless Compression using Efficient Encoding of Bitmasks Chetan Murthy and Prabhat Mishra Department of Computer and Information Science and Engineering University of Florida, Gainesville, FL 326, USA
More informationAn Energy-Efficient Scan Chain Architecture to Reliable Test of VLSI Chips
An Energy-Efficient Scan Chain Architecture to Reliable Test of VLSI Chips M. Saeedmanesh 1, E. Alamdar 1, E. Ahvar 2 Abstract Scan chain (SC) is a widely used technique in recent VLSI chips to ease the
More informationSSoCC'01 4/3/01. Specific BIST Architectures. Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University
Specific BIST Architectures Gert Jervan Embedded Systems Laboratory (ESLAB) Linköping University General Concepts Test-per-scan architectures Multiple scan chains Test-per-clock architectures BIST conclusions
More informationNovel Implementation of Low Power Test Patterns for In Situ Test
Novel Implementation of Low Power Test Patterns for In Situ Test K.Ramya 1, Y.N.S.Vamsi Mohan 2, S.V.S.M.Madhulika 3 1 M.Tech Student, Department of ECE,Bonam Venkata Chalamayya Institute of Technology
More informationPattern-Directed Circuit Virtual Partitioning for Test Power Reduction
Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction Qiang Xu Dept. of Computer Science & Engineering The Chinese University of Hong Kong Shatin, N.T., Hong Kong qxu@cse.cuhk.edu.hk Dianwei
More informationA Score-Based Classification Method for Identifying Hardware-Trojans at Gate-Level Netlists
A Score-Based Classification Method for Identifying Hardware-Trojans at Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa Department of Computer Science and Communications Engineering,
More informationSoftware-Based Test Integration in a SoC Design Flow
Software-Based Test Integration in a SoC Design Flow Alexandre M. Amory, Leandro A. Oliveira, Fernando G. Moraes Faculdade de Informática - Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS)
More information298 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 35, NO. 2, FEBRUARY 2016
298 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 35, NO. 2, FEBRUARY 2016 Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation Joon-Sung
More informationA Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods
International Journal of Scientific & Engineering Research, Volume 4, Issue 4, April-2013 664 A Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods Debasmita Hazra Abstract- This
More informationDeterministic Test Vector Compression/Decompression Using an Embedded Processor and Facsimile Coding
Master s thesis Deterministic Test Vector Compression/Decompression Using an Embedded Processor and Facsimile Coding by Jon Persson LITH-IDA-EX 05/033 SE 2005-03-21 Master s thesis Deterministic Test Vector
More informationSmartScan - Hierarchical Test Compression for Pin-limited Low Power Designs
- Hierarchical Test Compression for Pin-limited Low Power Designs K. Chakravadhanula *, V. Chickermane *, D. Pearl *, A. Garg #, R. Khurana #, S. Mukherjee #, P. Nagaraj + Encounter Test R&D, Front End
More informationOn Using Twisted-Ring Counters for Test Set Embedding in BIST
JOURNAL OF ELECTRONIC TESTING: Theory and Applications 17, 529 542, 2001 c 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. On Using Twisted-Ring Counters for Test Set Embedding in BIST
More informationINTERCONNECT TESTING WITH BOUNDARY SCAN
INTERCONNECT TESTING WITH BOUNDARY SCAN Paul Wagner Honeywell, Inc. Solid State Electronics Division 12001 State Highway 55 Plymouth, Minnesota 55441 Abstract Boundary scan is a structured design technique
More informationCOEN-4730 Computer Architecture Lecture 12. Testing and Design for Testability (focus: processors)
1 COEN-4730 Computer Architecture Lecture 12 Testing and Design for Testability (focus: processors) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University 1 Outline Testing
More informationSOFTWARE-BASED TEST FOR NON PROGRAMMABLE CORES IN BUS-BASED SYSTEM-ON-CHIP ARCHITECTURES
SOFTWARE-BASED TEST FOR NON PROGRAMMABLE CORES IN BUS-BASED SYSTEM-ON-CHIP ARCHITECTURES Alexandre M. Amory\ Leandro A. Oliveira' and Fernando G. Moraes^ ^Instituto de Informdtica - Universidade Federal
More informationScalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN)
Scalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN) Abstract With increasing design complexity in modern SOC design, many memory
More informationNur A. Touba. Professor Department of Electrical and Computer Engineering The University of Texas at Austin
Nur A. Touba Professor Department of Electrical and Computer Engineering The University of Texas at Austin Education: B.S. Electrical Engineering, University of Minnesota, 9/86-6/90 M.S. Electrical Engineering,
More information6 DESIGN FOR TESTABILITY I: FROM FULL SCAN TO PARTIAL SCAN
94 Advances in Microelectronics 6 DESIGN FOR TESTABILITY I: FROM FULL SCAN TO PARTIAL SCAN Chia Yee Ooi 6.1 CONTEXT It is important to check whether the manufactured circuit has physical defects or not.
More informationImproving Logic Obfuscation via Logic Cone Analysis
Improving Logic Obfuscation via Logic Cone Analysis Yu-Wei Lee and Nur A. Touba Computer Engineering Research Center University of Texas, Austin, TX 78712 ywlee@utexas.edu, touba@utexas.edu Abstract -
More informationInternational Journal of Digital Application & Contemporary research Website: (Volume 1, Issue 7, February 2013)
Programmable FSM based MBIST Architecture Sonal Sharma sonal.sharma30@gmail.com Vishal Moyal vishalmoyal@gmail.com Abstract - SOCs comprise of wide range of memory modules so it is not possible to test
More informationChapter 9. Design for Testability
Chapter 9 Design for Testability Testability CUT = Circuit Under Test A design property that allows: cost-effective development of tests to be applied to the CUT determining the status of the CUT (normal
More informationDESIGN-FOR-TESTABILITY AND DIAGNOSIS METHODS TO TARGET UNMODELED DEFECTS IN INTEGRATED CIRCUITS AND MULTI-CHIP BOARDS
DESIGN-FOR-TESTABILITY AND DIAGNOSIS METHODS TO TARGET UNMODELED DEFECTS IN INTEGRATED CIRCUITS AND MULTI-CHIP BOARDS by Hongxia Fang Department of Electrical and Computer Engineering Duke University Date:
More informationReducing Power Dissipation During Test Using Scan Chain Disable
Reducing Power Dissipation During Test Using Scan Chain Disable Ranganathan Sankaralingam, Bahram Pouya2, and Nur A. Touba Computer Engineering Research Center Dept. of Electrical and Computer Engineering
More informationOnline Testing of Word-oriented RAMs by an Accumulator-based Compaction Scheme in Symmetric Transparent Built-In Self Test (BIST)
Online Testing of Word-oriented RAMs by an Accumulator-based Compaction Scheme in Symmetric Transparent Built-In Self Test (BIST) Sharvani Yedulapuram #1, Chakradhar Adupa *2 # Electronics and Communication
More informationTESTING OF FAULTS IN VLSI CIRCUITS USING ONLINE BIST TECHNIQUE BASED ON WINDOW OF VECTORS
TESTING OF FAULTS IN VLSI CIRCUITS USING ONLINE BIST TECHNIQUE BASED ON WINDOW OF VECTORS Navaneetha Velammal M. 1, Nirmal Kumar P. 2 and Getzie Prija A. 1 1 Department of Electronics and Communications
More informationTest Set Compaction Algorithms for Combinational Circuits
Proceedings of the International Conference on Computer-Aided Design, November 1998 Set Compaction Algorithms for Combinational Circuits Ilker Hamzaoglu and Janak H. Patel Center for Reliable & High-Performance
More informationHigh Quality, Low Cost Test
Datasheet High Quality, Low Cost Test Overview is a comprehensive synthesis-based test solution for compression and advanced design-for-test that addresses the cost challenges of testing complex designs.
More informationHigh-level Variable Selection for Partial-Scan Implementation
High-level Variable Selection for Partial-Scan Implementation FrankF.Hsu JanakH.Patel Center for Reliable & High-Performance Computing University of Illinois, Urbana, IL Abstract In this paper, we propose
More informationA novel test access mechanism for parallel testing of multi-core system
LETTER IEICE Electronics Express, Vol.11, No.6, 1 6 A novel test access mechanism for parallel testing of multi-core system Taewoo Han, Inhyuk Choi, and Sungho Kang a) Dept of Electrical and Electronic
More informationDesign and Synthesis for Test
TDTS 80 Lecture 6 Design and Synthesis for Test Zebo Peng Embedded Systems Laboratory IDA, Linköping University Testing and its Current Practice To meet user s quality requirements. Testing aims at the
More informationAN IMPLEMENTATION THAT FACILITATE ANTICIPATORY TEST FORECAST FOR IM-CHIPS
AN IMPLEMENTATION THAT FACILITATE ANTICIPATORY TEST FORECAST FOR IM-CHIPS E.S.D Gireesh Goud 1, Mrs.T.Swetha 2 PG Scholor, DIET, HYD 1, Assistant Professor, DIET, HYD 2 ABSTRACT These designs pose significant
More informationADVANCES in integrated circuit (IC) fabrication technology
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 3, MARCH 2006 533 New and Improved BIST Diagnosis Methods From Combinatorial Group Testing Theory Andrew B. Kahng,
More informationDiagnosis and Layout Aware (DLA) Scan Chain Stitching
Diagnosis and Layout Aware (DLA) Scan Chain Stitching Jing Ye 1,2, Yu Huang 3, Yu Hu 1, Wu-Tung Cheng 3, Ruifeng Guo 3, Liyang Lai 3, Ting-Pu Tai 3, Xiaowei Li 1 (yejing@ict.ac.cn; yu_huang@mentor.com;
More informationAn Efficient Method for Multiple Fault Diagnosis
An Efficient Method for Multiple Fault Diagnosis Khushboo Sheth Department of Electrical and Computer Engineering Auburn University, Auburn, AL Abstract: In this paper, failing circuits are analyzed and
More informationA Low-Cost Correction Algorithm for Transient Data Errors
A Low-Cost Correction Algorithm for Transient Data Errors Aiguo Li, Bingrong Hong School of Computer Science and Technology Harbin Institute of Technology, Harbin 150001, China liaiguo@hit.edu.cn Introduction
More informationArea/Delay Estimation for Digital Signal Processor Cores
Area/Delay Estimation for Digital Signal Processor Cores Yuichiro Miyaoka Yoshiharu Kataoka, Nozomu Togawa Masao Yanagisawa Tatsuo Ohtsuki Dept. of Electronics, Information and Communication Engineering,
More informationFault Tolerant Computing CS 530 Testing Sequential Circuits
CS 530 Testing Sequential Circuits Yashwant K. Malaiya Colorado State University 1 Why Testing Sequential Circuits is Hard To test a sequential circuit we need to Initialize it into a known state (reset
More informationExploiting Unused Spare Columns to Improve Memory ECC
2009 27th IEEE VLSI Test Symposium Exploiting Unused Spare Columns to Improve Memory ECC Rudrajit Datta and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering
More informationEvaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks Charles Stroud, Ping Chen, Srinivasa Konala, Dept. of Electrical Engineering University of Kentucky and Miron Abramovici
More informationCOMPILED CODE IN DISTRIBUTED LOGIC SIMULATION. Jun Wang Carl Tropper. School of Computer Science McGill University Montreal, Quebec, CANADA H3A2A6
Proceedings of the 2006 Winter Simulation Conference L. F. Perrone, F. P. Wieland, J. Liu, B. G. Lawson, D. M. Nicol, and R. M. Fujimoto, eds. COMPILED CODE IN DISTRIBUTED LOGIC SIMULATION Jun Wang Carl
More informationAt-Speed On-Chip Diagnosis of Board-Level Interconnect Faults
At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults Artur Jutman Tallinn University of Technology artur@pld.ttu.ee Abstract This article describes a novel approach to fault diagnosis suitable
More informationX(1) X. X(k) DFF PI1 FF PI2 PI3 PI1 FF PI2 PI3
Partial Scan Design Methods Based on Internally Balanced Structure Tomoya TAKASAKI Tomoo INOUE Hideo FUJIWARA Graduate School of Information Science, Nara Institute of Science and Technology 8916-5 Takayama-cho,
More informationA Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors Murali Jayapala 1, Francisco Barat 1, Pieter Op de Beeck 1, Francky Catthoor 2, Geert Deconinck 1 and Henk Corporaal
More informationCycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling Soheil Samii 1, Erik Larsson 1, Krishnendu Chakrabarty 2, Zebo Peng 1 1 Embedded Systems Laboratory 2 Dept of Electrical &
More informationA New Scan Chain Fault Simulation for Scan Chain Diagnosis
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO.4, DECEMBER, 2007 221 A New Scan Chain Fault Simulation for Scan Chain Diagnosis Sunghoon Chun, Taejin Kim, Eun Sei Park, and Sungho Kang Abstract
More information