A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution
|
|
- Griffin Wade
- 5 years ago
- Views:
Transcription
1 A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution Irith Pomeranz 1 and Sudhakar M. Reddy 2 School of Electrical & Computer Eng. Electrical & Computer Eng. Dept. Purdue University University of Iowa W. Lafayette, IN 47907, U.S.A. Iowa City, IA 52242, U.S.A. Abstract We describe a new type of fault dictionary called a same/different fault dictionary. The same/different fault dictionary is similar to a pass/fail fault dictionary in that it contains a single bit b i,j for every modeled fault f i and test vector t j. However, in a pass/fail fault dictionary, b i,j is determined by comparing the output vector of the faulty circuit with the output vector of the fault free circuit; while in a same/different fault dictionary, b i,j is determined by comparing the output vector of the faulty circuit with a preselected output vector called a baseline output vector. By selecting appropriately the baseline output vectors for all the test vectors, it is possible to obtain increased diagnostic resolution with a same/different fault dictionary compared to a pass/fail fault dictionary. We describe a procedure for selecting baseline output vectors and present experimental results. 1. Introduction Defect diagnosis is applied to manufactured chips, which are found to be faulty, in order to identify the locations and types of defects present in them [1]. The first step of a defect diagnosis procedure typically determines a set of candidate defect sites. The candidate sites are selected such that modeled faults (typically single stuck-at faults) at these sites produce the observed failing responses of the applied tests, or responses that match them most closely [1]-[23]. Thus, even though the final goal of any defect diagnosis procedure is to determine the location and nature of the defect (such as an open or a bridge), fault diagnosis that considers modeled faults is an important first step in defect diagnosis. There are two types of fault diagnosis procedures that differ in the way they use precomputed information. Dictionary based approaches [2]-[14], also called causeeffect procedures, use a precomputed dictionary that contains information about the responses of modeled faults to the test set applied to the circuit. The observed response of a faulty circuit is compared to the responses stored in the dictionary in order to identify the best matches, and the 1. Research supported in part by SRC Grant No TJ Research supported in part by SRC Grant No TJ best matches are used to define the candidate defect sites. Dynamic or fault simulation based approaches [15]-[23], also called effect-cause diagnosis procedures, typically do not use any precomputed information. Given the observed response of a faulty circuit, they perform fault simulations to identify the faults whose responses best match the observed response. The size of a fault dictionary is determined by the number of faults, the number of tests, and the number of outputs, and it is typically very large. However, when a fault dictionary can be stored, it reduces the fault simulation effort required for fault diagnosis compared to approaches that do not use a fault dictionary [9]. In addition, two-phase approaches that combine the use of a dictionary with dynamic diagnosis allow smaller dictionaries to be used [8], [12], [14]. Methods to compute small fault dictionaries were considered in [9]-[14]. There are two basic types of fault dictionaries that can be used alone as in cause-effect procedures, or to assist effect-cause diagnosis procedures [8], [12], [14]. The fault dictionary that contains the largest amount of information about modeled faults is the f ull fault dictionary. A full fault dictionary contains the complete output vector of every modeled fault under every test vector. It provides the highest possible diagnostic resolution, i.e., it allows us to distinguish every pair of faults that can be distinguished by the test set on which it is based. A pass /f ail fault dictionary contains a single bit b i,j for every fault and test vector. The bit for fault f i and test t j is 1 if t j detects f i, and it is 0 otherwise. Many of the methods to produce small fault dictionaries attempt to achieve the diagnostic resolution of a full fault dictionary by adding as little information as possible to a pass/fail dictionary, e.g., [9] and [12]. In this work we define a new type of dictionary called a same/different fault dictionary. A same/different fault dictionary is similar to a pass/fail fault dictionary in that it contains a single bit b i,j for every fault f i and test vector t j. However, in a pass/fail fault dictionary, the value of b i,j is determined by comparing the output vector z i,j of f i under t j to a fault free output vector z ff,j (ff stands for f ault f ree ). In a same/different fault dictionary, the value of b i,j is determined by comparing the out /DATE EDAA
2 put vector z i,j of f i under t j to a preselected output vector denoted by z bl,j. Here, bl stands for baseline, indicating that z bl,j provides a baseline for comparison, similar to the way the fault free output vector z ff,j is used in a pass/fail dictionary. In the approach described in this work, a single baseline vector z bl,j is selected for a test vector t j, considering every test vector t j in the test set applied to the circuit. The flexibility in selecting z bl,j allows us to obtain a same/different fault dictionary that has a similar size to a pass/fail fault dictionary, but has a higher resolution. We demonstrate this point in Section 2. One can select more than one baseline vector for a test vector. In this work we select only one per test vector. In Section 3 we describe a procedure for selecting the baseline output vectors for a same/different fault dictionary. Experimental results are presented in Section 4. Throughout this work we represent fault dictionaries as two-dimensional arrays. Other representations include lists of detected faults, or tree structures [1]. 2. Same/different fault dictionary To demonstrate the definition and advantages of a same/different fault dictionary, we consider four faults, f 0, f 1, f 2 and f 3, under two tests, t 0 and t 1, in a twooutput circuit. In Table 1 we show the entries corresponding to a full fault dictionary. Row ff shows the fault free output vectors z ff,j, for j = 0,1. Row f i shows the output vectors z i,j obtained for f i under t j, for i = 0,1,2,3 and j = 0,1. The full fault dictionary distinguishes between all the pairs of faults based on their output vectors. For example, f 0 and f 1 are distinguished by t 0 since z 0,0 z 1,0 ; and f 2 and f 3 are distinguished by t 1 since z 2,1 z 3,1. Table 1: A full fault dictionary t 0 t 1 ff f f f f A pass/fail fault dictionary for the same faults and tests is shown in Table 2. An output vector z i,j in the full dictionary is replaced with b i,j = 0 in the pass/fail dictionary if z i,j = z ff,j, and it is replaced with b i,j = 1 in the pass/fail dictionary if z i,j z ff,j. The pass/fail fault dictionary distinguishes between all the fault pairs except for the fault pair f 2,f 3. For example, f 0 and f 1 are distinguished by t 0 since b 0,0 b 1,0 ; however, for f 2 and f 3 we have b 2,0 = b 3,0 and b 2,1 = b 3,1. In a same/different fault dictionary we have the flexibility of selecting the baseline output vectors against which output vectors of faulty circuits will be compared. Table 2: A pass/fail fault dictionary t 0 t 1 ff f f f f A same/different fault dictionary for the faults and tests above is shown in Table 3. We use z bl,0 = 01 and z bl,1 = 10 as baseline vectors. An output vector z i,j in the full fault dictionary is replaced with b i,j = 0 in the same/different fault dictionary if z i,j = z bl,j, and it is replaced with b i,j = 1 in the same/different fault dictionary if z i,j z bl,j. The same/different fault dictionary of Table 3 distinguishes between all the pairs of faults based on their entries. For example, f 0 and f 1 are distinguished by t 1 since b 0,1 b 1,1 ; and f 2 and f 3 are distinguished by t 1 since b 2,1 b 3,1. Table 3: A same/different fault dictionary t 0 t 1 bl f f f f It can be seen that, in the example, the same/different fault dictionary provides the diagnostic resolution of a full fault dictionary. In general, by selecting appropriate baseline vectors, the diagnostic resolution of a same/different fault dictionary can be made higher than that of a pass/fail dictionary of a similar size. The need to store the baseline output vectors adds to the storage requirements. We discuss the relative sizes of the various dictionaries next. For the circuit under consideration, let the number of test vectors be k, let the number of faults be n, and let the number of outputs be m. Storing the fault free output response of the circuit requires k. m bits. We do not include this in the size of a dictionary. The size of a full dictionary for the circuit is k. n. m bits (a full dictionary contains a bit for every test vector, fault and output). The size of a pass/fail dictionary is k. n bits (a pass/fail dictionary contains a bit for every test vector and fault). The size of the proposed same/different dictionary is k. n +k. m = k. (n +m ) bits. The difference of k. m bits in the sizes of the pass/fail and same/different dictionaries is due to the need to store baseline vectors, assuming that a baseline vector is used for each test vector. For scan designs the number of outputs m is the sum of the number of scan cells and the number of primary outputs. If test response compaction is used, the number of outputs will be significantly smaller. In indus-
3 trial designs typically the number of outputs m is smaller than the number of faults n by one to two orders of magnitude. Hence, the additional memory requirement for the same/different fault dictionary relative to the pass/fail fault dictionary will be negligible. In addition, it is important to note that one may not need to use a baseline vector for every test vector. Instead, the fault free output vector may be used for some of the test vectors. This further reduces the difference in the sizes of these dictionaries. 3. Computing a fault dictionary To compute a same/different fault dictionary it is necessary to compute a baseline vector z bl,j for every test vector t j. In this section we describe a procedure for computing baseline vectors for a same/different fault dictionary. We consider a set of faults F = {f 0,f 1,...,f n 1 } and a test set T = {t 0,t 1,...,t k 1 }. We denote by z i,j the output vector of the faulty circuit in the presence of f i under t j. We denote by Z j the set of all the output vectors that may be produced by modeled faults under t j, i.e., Z j = {z i,j :0 i<n}. Since a test vector t j never detects all the faults in F, the fault free output vector z ff,j is included in Z j. We note that if z bl,j is selected such that z bl,j /Z j, we will have z i,j z bl,j, and consequently b i,j = 1, for every f i F. As a result, t j will not distinguish any pair of faults in the same/different fault dictionary. Therefore, it is only necessary to consider the vectors in Z j as candidates for z bl,j. For example, considering the output vectors of Table 1, we have Z 0 = {00, 10, 01}. If we use z bl,0 = 11, we will obtain b i,0 = 1 for every i, and t 0 will not distinguish any fault pair. Using z bl,0 = z ff,0 = 00 causes t 0 to distinguish f 0 from f 1, f 2 and f 3. Using z bl,0 = z 2,0 = 01 as in Table 3 causes t 0 to distinguish f 0 and f 1 from f 2 and f 3. We select the baseline output vectors z bl,j by considering the tests in T one at a time. During the selection process we maintain a set of target fault pairs P that need to be distinguished. Initially, P includes all the fault pairs defined based on F. After z bl,j is selected, all the fault pairs distinguished by t j are removed from P. When t j is considered, the candidates for z bl,j are the output vectors included in Z j. For every z Z j,we check how many fault pairs in P will be distinguished if z bl,j = z. We denote this number by dist (z ). Of all the vectors in Z j we select the one with the highest value of dist (z ), and we set z bl,j = z. In the example of Table 1, we have the options for z bl,0 shown in Table 4. These are all the vectors under column t 0 of Table 1. For each option we show the fault pairs that will be distinguished. We select z bl,0 = 01 since it distinguishes the highest number of fault pairs. The fault pairs distinguished are removed from consideration. Next, we consider the options for z bl,1 shown in Table 5. These are all the vectors under column t 1 of Table 1. We select z bl,1 = 10 to distinguish the remaining two fault pairs. This results in the same/different fault dictionary of Table 3. Table 4: Selection of z bl,0 z distinguished dist (z ) 00 f 0,f 1 ; f 0,f 2 ; f 0,f f 0,f 1 ; f 1,f 2 ; f 1,f f 0,f 2 ; f 0,f 3 ; f 1,f 2 ; f 1,f 3 4 Table 5: Selection of z bl,1 z distinguished dist (z ) 11 f 0,f f 0,f 1 ; f 2,f f 2,f 3 1 We observed that the highest values of dist (z ) are typically found after the first few output vectors in Z j are considered, and consideration of additional output vectors does not yield higher values of dist (z ). This allows us to avoid consideration of a large number of candidate output vectors when the number of faults is large and the number of candidate vectors in Z j is large. We implement this observation as follows. For a constant LOWER, if LOWER consecutive output vectors in Z j provide lower values of dist (z ) than the highest value obtained thus far, we do not consider any additional output vectors. We select one of the output vectors with the highest value of dist (z ) of all the output vectors in Z j for which dist (z ) was computed. The procedure described above is given next as Procedure 1. Procedure 1: Computing a same/different dictionary (1) Let F = {f 0,f 1,...,f n 1 } be the set of modeled faults, and let T = {t 0,t 1,...,t k 1 } be a given test set. Include in P every fault pair based on F. Set j = 0. (2) Set Z j = {z i,j :f i F }. Set best_dist = 1. Set lower = 0. (3) For every z Z j : (a) Find the number of fault pairs f i 1,f i 2 P such that f i 1,f i 2 will be distinguished if z bl,j = z, i.e., the number of fault pairs f i 1,f i 2 P such that z i 1,j = z and z i 2,j z, or z i 1,j z and z i 2,j = z. Let this number be dist (z ). (b) If dist (z ) > best_dist, set best_dist = dist (z ) and lower = 0. Else, if dist (z ) < best_dist, set lower = lower +1. (c) If lower = LOWER, go to Step 4.
4 (4) Select one of the vectors z Z j for which dist (z ) is the highest of all the vectors in Z j for which dist (z ) was computed. Set z bl,j = z. Remove from P every fault pair f i 1,f i 2 P such that f i 1,f i 2 are distinguished based on z bl,j, i.e., z i 1,j = z bl,j and z i 2,j z bl,j,orz i 1,j z bl,j and z i 2,j = z bl,j. (5) Set j = j +1. If j<kgo to Step 2. Procedure 1 includes all the fault pairs in the set P and considers them explicitly. It is possible to reduce the number of fault pairs considered by excluding from P fault pairs that are known to be easy-to-distinguish. In particular, if two faults cannot be detected by the same test the fault pair can be excluded from P. The order by which test vectors are considered in Procedure 1 can have a significant effect on the selection of the baseline vectors, and the number of fault pairs distinguished by the resulting same/different dictionary. Therefore, we apply Procedure 1 several times, each time with a different random order of the test vectors in T.We continue to reorder T and apply Procedure 1 until the number of distinguished fault pairs does not increase for CALLS 1 consecutive calls to Procedure 1, where CALLS 1 is a constant. We use the baseline vectors that result in the highest number of distinguished fault pairs. Starting from the baseline vectors that result in the highest number of distinguished fault pairs, we then attempt to replace individual baseline vectors with different ones. We accept a replacement if it increases the number of distinguished fault pairs. The candidates for replacing z bl,j are the vectors included in the set Z j defined earlier. The procedure for replacing baseline vectors is given next as Procedure 2. Procedure 2: Replacing baseline vectors (1) Let F = {f 0,f 1,...,f n 1 } be the set of modeled faults, and let T = {t 0,t 1,...,t k 1 } be a given test set. Include in P every fault pair based on F. Let z bl,j be the baseline vector selected for t j, for 0 j<k. (2) Find the number of fault pairs f i 1,f i 2 P that are distinguished by T with the current baseline vectors. Assign this number to BEST_DIST. (3) Set j = 0. (4) Set Z j = {z i,j :f i F }. (5) For every z Z j : (a) Set ẑ = z bl,j. Set z bl,j = z. (b) Find the number of fault pairs f i 1,f i 2 P that are distinguished by T with the current baseline vectors. Assign this number to DIST. (c) If DIST > BEST_DIST, set BEST_DIST = DIST. Else, set z bl,j = ẑ. (6) Set j = j +1. If j<kgo to Step 4. We apply Procedure 2 repeatedly as long as it is able to increase the number of distinguished fault pairs (BEST_DIST ). 4. Experimental results We applied Procedure 1 with LOWER = 10 and CALLS 1 = 100, followed by Procedure 2. We used two types of test sets for every circuit: a diagnostic test set for stuck-at faults, and a 10-detection test set for stuck-at faults. We used the set of collapsed single stuck-at faults as the set of faults F. The results are shown in Table 6. We include two rows for every circuit. In the first row we show the results obtained using a diagnostic test set. In the second row we show the results obtained using a 10-detection test set. Under column Ttype we show the type of the test set used, where diag stands for a diagnostic test set, and 10det stands for a 10-detection test set. Under column T we show the number of tests in the test set. Under column size we show the size (in bits) of the following fault dictionaries: a full fault dictionary (subcolumn f ull ), a pass/fail fault dictionary (subcolumn p/f ), and a same/different fault dictionary (subcolumn s/d). Under column indistinguished we show the number of fault pairs left indistinguished by the following fault dictionaries: a full fault dictionary (subcolumn f ull ),a pass/fail fault dictionary (subcolumn p/f ), the best same/different fault dictionary computed by Procedure 1 using several random test orders (subcolumn s /d rand ), and the same/different fault dictionary computed by Procedure 2 (subcolumn s /d repl ). We omit the entry for Procedure 2 if it does not improve the number of distinguished fault pairs compared to the same/different fault dictionary computed by Procedure 1. The following points can be seen from Table 6. The 10-detection test set is typically larger than a diagnostic test set. Nevertheless, the same/different dictionary based on the 10-detection test set is smaller than the full dictionary based on the diagnostic test set. The size of a same/different fault dictionary is close to that of a pass/fail dictionary. The diagnostic test set leaves a smaller number of indistinguished fault pairs when a full dictionary is used. For a pass/fail dictionary, the higher number of tests in a 10-detection test set is more effective in ensuring that fault pairs can be distinguished. In terms of test generation effort, diagnostic test generation is more computationally intensive than 10-detection test generation due to the number of targets that need to be considered (the number of fault pairs is significantly larger than 10 times the number of faults). Thus, each type of test set has certain advantages for fault diagnosis. In all the cases considered, a same/different fault dictionary can distinguish more fault pairs than a pass/fail
5 fault dictionary of a similar size. The difference is higher when the test set size is higher. Thus, the same/different fault dictionary is more effective as a replacement for a pass/fail dictionary when a 10-detection test set is used. This is due to the fact that the larger number of tests provides more opportunities for distinguishing fault pairs with appropriately selected baseline vectors. When a 10- detection test set is used, the same/different fault dictionary sometimes distinguishes all the fault pairs distinguished by a full dictionary. This is the best possible result. In all the cases, a same/different fault dictionary should be used instead of a pass/fail dictionary since the improvement in diagnostic resolution comes with only a small increase in dictionary size. In many cases, Procedure 1 finds a set of baseline output vectors that cannot be further improved by Procedure 2. In the case of 10-detection test sets, if Procedure 1 finds a set of baseline vectors that distinguishes all the fault pairs that can be distinguished by a full fault dictionary, Procedure 2 cannot improve the results any further. When improvements are possible, Procedure 2 finds them in several cases. 5. Concluding remarks We defined a new type of fault dictionary called a same/different fault dictionary. A same/different fault dictionary is based on a set of baseline output vectors, one for every test vector applied to the circuit. A same/different fault dictionary contains a single bit for every modeled fault and test vector. The bit is determined by comparing the output vector of the faulty circuit with the baseline output vector of the test. The bit is 0 when the vectors are the same, and 1 when they are different. By selecting baseline output vectors appropriately it is possible to obtain increased diagnostic resolution with a same/different fault dictionary compared to a pass/fail fault dictionary of a similar size. We described a procedure for selecting baseline output vectors for a given test set and set of modeled faults. The procedure was based on diagnostic fault simulation of each test with several options for its baseline output vector. Of all the options, the one that distinguished the largest number of fault pairs was selected. The selection was done in different orders to identify the one that distinguished the largest number of fault pairs overall. A procedure that modified the selection so as to distinguish additional fault pairs was also described. References [1] M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, [2] R. E. Tulloss, "Size Optimization of Fault Dictionaries", in Proc. Semiconductor Test Conf., 1978, pp [3] R. E. Tulloss, "Fault Dictionary Compression: Recognizing when a Fault May Be Unambiguously Represented by a Single Failure Detection", in Proc. Test Conf., Nov. 1980, pp [4] J. Richman and K. R. Bowden, "The Modern Fault Dictionary", in Proc. Intl. Test Conf., Sept. 1985, pp [5] V. Ratford and P. Keating, "Integrating Guided Probe and Fault Dictionary: An Enhanced Diagnostic Approach", in Proc. Intl. Test Conf., 1986, pp [6] R. C. Aitken and V. K. Agarwal, "A Diagnosis Method Using Pseudo-Random Vectors Without Intermediate Signatures", in Proc. Intl. Conf. on Computer-Aided Design, Nov. 1989, pp [7] S. D. Millman, E. J. McCluskey and J. M. Acken, "Diagnosing CMOS Bridging Faults with Stuck-at Fault Dictionaries", in Proc. Intl. Test Conf., Sept. 1990, pp [8] P. G. Ryan, S. Rawat and W. K. Fuchs, "Two-Stage Fault Location", in Proc Intl. Test Conf., Oct. 1991, pp [9] I. Pomeranz and S. M. Reddy, "On the Generation of Small Dictionaries for Fault Location", in Proc. Intl. Conf. on Computer- Aided Design, Nov. 1992, pp [10] P. G. Ryan, W. K. Fuchs and I. Pomeranz, "Fault Dictionary Compression and Equivalence Class Computation for Sequential Circuits", in Proc. Intl. Conf. on Computer-Aided Design, Nov. 1993, pp [11] I. Pomeranz, "On Pass/Fail Dictionaries for Scan Circuits", in Proc. 10th Asian Test Symp., Nov. 2001, pp [12] D. B. Lavo and T. Larrabee, "Making Cause-Effect Cost Effective: Low-Resolution Fault Dictionaries", in Proc. Intl. Test Conf., Oct. 2001, pp [13] P. Bernardi, M. Grosso, M. Rebaudengo and M. Sonza Reorda, "A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries", in Proc. VLSI Test Symposium, Apr. 2006, pp [14] W. Zou, W.-T. Cheng, S. M. Reddy and H. Tang, "Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary", in Proc. VLSI Test Symp., 2007, Paper 6B-2. [15] M. Abramovici and M. A. Breuer, "Fault Diagnosis Based on Effect-Cause Analysis: An Introduction", in Proc. 17th Design Autom. Conf, June 1980, pp [16] M. Abramovici, "A Maximal Resolution Guided-Probe Testing Algorithm", in Proc of Design Autom. Conf., June 1981, pp [17] Y. Azounamian and J. A. Waicukauski, "Fault Diagnosis in an LSSD Environment", in Proc. Intl. Test Conf., Sept. 1981, pp [18] J. Savir and J. P. Roth, "Testing for, and Distinguishing between Failures", in Proc. 12th Intl. Symp. on Fault-Tolerant Computing, June 1982, pp [19] J. A. Waicukauski, V. P. Gupta and S. T. Patel, "Diagnosis of BIST Failures by PPSFP Simulation", in Proc. Intl. Test Conf., Sept. 1987, pp [20] J. A. Waicukauski and E. Lindbloom, "Failure Diagnosis of Structured VLSI", IEEE Design and Test of Computers, Aug. 1989, pp [21] M. Marzouki, J. Laurent and B. Courtois, "Coupling Electron- Beam Probing with Knowledge-Based Fault Localization", in Proc. Intl. Test Conf., Oct. 1991, pp [22] S. Venkataraman and S. B. Drummonds, "POIROT: A Logic Fault Diagnosis Tool and its Applications", in Proc. Intl. Test Conf., Oct. 2000, pp [23] T. Bartenstein, D. Heaberlin, L. Huisman and D. Sliwinski, "Diagnosing Combinational Logic Designs Using the Single Location At-A-Time (SLAT) Paradigm", in Proc. Intl. Test Conf., 2001, pp
6 Table 6: Experimental results indistinguished size s/d circuit Ttype T full p/f s/d full p/f rand repl s208 diag s208 10det s298 diag s298 10det s344 diag s344 10det s382 diag s382 10det s386 diag s386 10det s400 diag s400 10det s420 diag s420 10det s510 diag s510 10det s526 diag s526 10det s641 diag s641 10det s820 diag s820 10det s953 diag s953 10det s1196 diag s det s1423 diag s det s5378 diag s det s9234 diag s det
On Test Generation by Input Cube Avoidance
On Test Generation by Input Cube Avoidance Irith Pomeranz 1 and Sudhakar M. Reddy 2 School of Electrical & Computer Eng. Electrical & Computer Eng. Dept. Purdue University University of Iowa W. Lafayette,
More informationFull Fault Dictionary Storage Based on Labeled Tree Encoding
Full Fault Dictionary Storage Based on Labeled Tree Encoding Vamsi Boppana, Ismed Hartanto and W. Kent Fuchs Coordinated Science Laboratory University of Illinois at UrbanaChampaign Urbana, IL 6181 Abstract
More informationREDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits *
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits * Chen Wang, Irith Pomeranz and Sudhakar M. Reddy Electrical and Computer Engineering Department
More informationScan-Based BIST Diagnosis Using an Embedded Processor
Scan-Based BIST Diagnosis Using an Embedded Processor Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas
More informationOn Test Generation for Transition Faults with Minimized Peak Power Dissipation
30.3 On Test Generation for Transition Faults with Minimized Peak Power Dissipation Wei Li Sudhakar M. Reddy Irith Pomeranz 2 Dept. of ECE School of ECE Univ. of Iowa Purdue University Iowa City, IA 52242
More informationFunctional Test Generation for Delay Faults in Combinational Circuits
Functional Test Generation for Delay Faults in Combinational Circuits Irith Pomeranz and Sudhakar M. Reddy + Electrical and Computer Engineering Department University of Iowa Iowa City, IA 52242 Abstract
More informationOutline. Definition. Targeted Defects. Motivation GOAL. Ferhani, RATS/SPRING , Center for Reliable Computing 1
RATS (Reliability and Testability Seminar) Diagnosis of Defects Introducing Voltage Dependences between Nodes By François-Fabien Ferhani 5/27/2003 Ferhani, RATS/SPRING03 Outline Introduction Problems &
More informationEfficient RT-level Fault Diagnosis Methodology
Efficient RT-level Fault Diagnosis Methodology ABSTRACT Increasing IC densities necessitate diagnosis methodologies with enhanced defect locating capabilities. Yet the computational effort expended in
More informationAdaptive Techniques for Improving Delay Fault Diagnosis
Adaptive Techniques for Improving Delay Fault Diagnosis Jayabrata Ghosh-Dastidar and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas,
More informationAn Efficient Method for Multiple Fault Diagnosis
An Efficient Method for Multiple Fault Diagnosis Khushboo Sheth Department of Electrical and Computer Engineering Auburn University, Auburn, AL Abstract: In this paper, failing circuits are analyzed and
More informationAt-Speed Scan Test with Low Switching Activity
21 28th IEEE VLSI Test Symposium At-Speed Scan Test with Low Switching Activity Elham K. Moghaddam Department of ECE, University of Iowa, Iowa City, IA 52242 ekhayatm@engineering.uiowa.edu Janusz Rajski
More informationA Diagnostic Test Generation System
A Diagnostic Test Generation System Yu Zhang and Vishwani D. Agrawal Auburn University, Department of Electrical and Computer Engineering, Auburn, AL 36849, USA yzz0009@auburn.edu, vagrawal@eng.auburn.edu
More informationDriving Toward Higher I DDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG
Driving Toward Higher I DDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG Hisashi Kondo Kwang-Ting Cheng y Kawasaki Steel Corp., LSI Division Electrical and Computer Engineering
More informationOn Using Design Partitioning To Reduce Diagnosis Memory Footprint
0 Asian Test Symposium On Using Design Partitioning To Reduce Diagnosis Memory Footprint Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng and Brady Benware. Department of ECE. Mentor Graphics,
More informationEvaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks Charles Stroud, Ping Chen, Srinivasa Konala, Dept. of Electrical Engineering University of Kentucky and Miron Abramovici
More informationResynthesis of Combinational Logic Circuits for Improved Path Delay Fault Testability Using Comparison Units
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 5, OCTOBER 2001 679 Resynthesis of Combinational Logic Circuits for Improved Path Delay Fault Testability Using Comparison
More informationScalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN)
Scalable Controller Based PMBIST Design For Memory Testability M. Kiran Kumar, G. Sai Thirumal, B. Nagaveni M.Tech (VLSI DESIGN) Abstract With increasing design complexity in modern SOC design, many memory
More informationDiagnostic Testing of Embedded Memories Using BIST
Diagnostic Testing of Embedded Memories Using BIST Timothy J. Bergfeld Dirk Niggemeyer Elizabeth M. Rudnick Center for Reliable and High-Performance Computing, University of Illinois 1308 West Main Street,
More informationGate Level Fault Diagnosis in Scan-Based BIST
Gate Level Fault Diagnosis in Scan-Based BIST Ismet Bayraktaroglu Computer Science & Engineering Department University of California, San Diego La Jolla, CA 92093 ibayrakt@csucsdedu Alex Orailoglu Computer
More informationOn Minimizing the Number of Test Points Needed to Achieve Complete Robust Path Delay Fault Testability
On Minimizing the Number of Test Points Needed to Achieve Complete Robust Path Delay Fault Testability Prasanti Uppaluri Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA
More informationInternational Journal of Digital Application & Contemporary research Website: (Volume 1, Issue 7, February 2013)
Programmable FSM based MBIST Architecture Sonal Sharma sonal.sharma30@gmail.com Vishal Moyal vishalmoyal@gmail.com Abstract - SOCs comprise of wide range of memory modules so it is not possible to test
More informationAFault Diagnosis Methodology for the UltraSPARC TM -I. Sridhar Narayanan, Rajagopalan Srinivasan, Ramachandra P. Kunda,
AFault Diagnosis Methodology for the UltraSPARC TM -I Microprocessor Sridhar Narayanan, Rajagopalan Srinivasan, Ramachandra P. Kunda, Marc E. Levitt and Saied Bozorgui-Nesbat Sun Microsystems Inc. Mountain
More informationSpecial ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST Madhavi Karkala Nur A. Touba Hans-Joachim Wunderlich Computer Engineering Research Center Computer Architecture Lab Dept. of Electrical
More informationCollapsing for Multiple Output Circuits. Diagnostic and Detection Fault. Raja K. K. R. Sandireddy. Dept. Of Electrical and Computer Engineering,
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits Raja K. K. R. Sandireddy Dept. Of Electrical and Computer Engineering, Auburn University, Auburn AL-36849 USA Outline Introduction
More informationAn Efficient Test Relaxation Technique for Synchronous Sequential Circuits
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits Aiman El-Maleh and Khaled Al-Utaibi King Fahd University of Petroleum and Minerals Dhahran 326, Saudi Arabia emails:{aimane, alutaibi}@ccse.kfupm.edu.sa
More informationIncremental Diagnosis of Multiple Open-Interconnects
Incremental Diagnosis of Multiple Open-Interconnects J Brandon Liu, Andreas Veneris University of Toronto, Department of ECE Toronto, ON M5S 3G4, Canada {liuji, veneris}@eecgutorontoca Hiroshi Takahashi
More informationTESTING OF FAULTS IN VLSI CIRCUITS USING ONLINE BIST TECHNIQUE BASED ON WINDOW OF VECTORS
TESTING OF FAULTS IN VLSI CIRCUITS USING ONLINE BIST TECHNIQUE BASED ON WINDOW OF VECTORS Navaneetha Velammal M. 1, Nirmal Kumar P. 2 and Getzie Prija A. 1 1 Department of Electronics and Communications
More informationN-Model Tests for VLSI Circuits
40th Southeastern Symposium on System Theory University of New Orleans New Orleans, LA, USA, March 16-18, 2008 MC3.6 N-Model Tests for VLSI Circuits Nitin Yogi and Vishwani D. Agrawal Auburn University,
More informationAN EFFICIENT LOGIC FAULT DIAGNOSIS FRAMEWORK BASED ON EFFECT-CAUSE APPROACH. A Dissertation LEI WU
AN EFFICIENT LOGIC FAULT DIAGNOSIS FRAMEWORK BASED ON EFFECT-CAUSE APPROACH A Dissertation by LEI WU Submitted to the Office of Graduate Studies of Texas A&M University in partial fulfillment of the requirements
More informationA New Optimal State Assignment Technique for Partial Scan Designs
A New Optimal State Assignment Technique for Partial Scan Designs Sungju Park, Saeyang Yang and Sangwook Cho The state assignment for a finite state machine greatly affects the delay, area, and testabilities
More informationDiagnostic Test Vectors for Combinational and Sequential
Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi and Yuzo Takamatsu(Ehime University) Kewal K. Saluja
More informationUsing Scan-Dump Values to Improve Functional-Diagnosis Methodology
Using Scan-Dump Values to Improve Functional-Diagnosis Methodology Vishnu C Vimjam 1 M Enamul Amyeen 2 Ruifeng Guo 3 Srikanth Venkataraman 2 Michael Hsiao 1 Kai Yang 4 1 ECE Dept, Virginia Tech, Blacksburg,
More informationDiagnostic Test Set Minimization and Full-Response Fault Dictionary
J Electron Test (2012) 28:177 187 DOI 10.1007/s10836-012-5286-3 Diagnostic Test Set Minimization and Full-Response Fault Dictionary Mohammed Ashfaq Shukoor Vishwani D. Agrawal Received: 13 November 2009
More informationFault Testing of CMOS Integrated Circuits Using Signature Analysis Method
Fault Testing of CMOS Integrated Circuits Using Signature Analysis Method Prof. R.H. Khade 1 and Mr. Swapnil Gourkar 2 1 Associate Professor, Department of Electronics Engineering, Pillai Institute of
More informationChapter 7. Logic Diagnosis. VLSI EE141 Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. 1
Chapter 7 Logic Diagnosis VLSI EE4 Test Principles and Architectures Ch. 7 - Logic Diagnosis - P. Outline Introduction Combinational Logic Diagnosis Scan Chain Diagnosis Logic BIST Diagnosis Conclusion
More informationBuilt-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs
Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs Sudheer Vemula, Student Member, IEEE, and Charles Stroud, Fellow, IEEE Abstract The first Built-In Self-Test (BIST) approach for the programmable
More informationComputer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis
Computer-Aided Fault to Defect Mapping (CAFDM) for Defect Diagnosis Zoran Stanojevic Dept. of Electrical Engineering Texas A&M University College Station TX 77843-3124 Tel: (979) 862-6610 Fax: (979) 847-8578
More informationFigure 1.1. ROAR architecture. Memory. Reconfigurable Coprocessor. Multithreaded Processor. Interface Bus. I/O system
NON-SELF-TESTABLE FAULTS IN DUPLEX SYSTEMS Subhasish Mitra, Nirmal R. Saxena and Edward J. McCluskey Center for Reliable Computing (http://crc.stanford.edu) Departments of Electrical Engineering and Computer
More informationBit-Fixing in Pseudorandom Sequences for Scan BIST
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 4, APRIL 2001 545 Bit-Fixing in Pseudorandom Sequences for Scan BIST Nur A. Touba, Member, IEEE, and Edward J.
More informationOn Efficient Error Diagnosis of Digital Circuits
On Efficient Error Diagnosis of Digital Circuits Nandini Sridhar Michael S. Hsiao Intel Corporation Bradley Dept. of ECE, Virginia Tech Dupont, WA 98327Blacksburg, VA 246 nandini.sridhar@intel.com mhsiao@vt.edu
More informationVLSI System Testing. Fault Simulation
ECE 538 VLSI System Testing Krish Chakrabarty Fault Simulation ECE 538 Krish Chakrabarty Fault Simulation Problem and motivation Fault simulation algorithms Serial Parallel Deductive Concurrent Random
More informationEfficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering
Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering Aiman El-Maleh, Saqib Khurshid King Fahd University of Petroleum and Minerals Dhahran, Saudi Arabia
More informationReducing Control Bit Overhead for X-Masking/X-Canceling Hybrid Architecture via Pattern Partitioning
Reducing Control Bit Overhead for X-Masking/X-Canceling Hybrid Architecture via Pattern Partitioning Jin-Hyun Kang Semiconductor Systems Department Sungkyunkwan University Suwon, Korea, 16419 kangjin13@skku.edu
More informationTwo Pattern Test Cubes for Transition Path Delay Faults Test for ISCAS-85 C432
Two Pattern Test Cubes for Transition Path Delay Faults Test for ISCAS-85 C432 T.Vishnu Murty 1, G.Seetha Mahalakshmi 2 M.Tech, Asst. Professor, Dept of Electronics & Communication Engineering, Pragati
More informationALTERING A PSEUDO-RANDOM BIT SEQUENCE FOR SCAN-BASED BIST
ALTERING A PSEUDO-RANDOM BIT SEQUENCE FOR SCAN-BASED BIST Nur A. Touba* and Edward J. McCluskey Center for Reliable Computing Departments of Electrical Engineering and Computer Science Stanford University
More informationOn-Chip Diagnosis for Early-Life and Wear-Out Failures
2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising
More informationFunctional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG Andreas Veneris, Robert Chang Magdy. Abadir ep eyedi Abstract Fault equivalence is an
More informationEfficient Algorithm for Test Vector Decompression Using an Embedded Processor
Efficient Algorithm for Test Vector Decompression Using an Embedded Processor Kamran Saleem and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University
More informationDefect Localization Using Physical Design and Electrical Test Information
Defect Localization Using Physical Design and Electrical Test Information Zoran Stanojevic Dept. of Electrical Engineering Texas A&M University College Station TX 77843 Tel: (979) 862-6610 Fax: (979) 847-8578
More informationSingle Stuck-At Fault Diagnosing Circuit of Reed-Muller Canonical Exclusive-Or Sum of Product Boolean Expressions
Journal of Computer Science 2 (7): 595-599, 2006 ISSN 1549-3636 2006 Science Publications Single Stuck-At Fault Diagnosing Circuit of Reed-Muller Canonical Exclusive-Or Sum of Product Boolean Expressions
More informationA New Scan Chain Fault Simulation for Scan Chain Diagnosis
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO.4, DECEMBER, 2007 221 A New Scan Chain Fault Simulation for Scan Chain Diagnosis Sunghoon Chun, Taejin Kim, Eun Sei Park, and Sungho Kang Abstract
More informationSRAM Delay Fault Modeling and Test Algorithm Development
SRAM Delay Fault Modeling and Test Algorithm Development Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, and Cheng-Wen Wu Laboratory for Reliable Computing (LaRC) Department of Electrical Engineering National
More informationA Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis Chunsheng Liu and Krishnendu Chakrabarty Department of Electrical & Computer
More informationTransition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation of Functional Broadside Tests
Purdue University Purdue e-pubs Open Access Dissertations Theses and Dissertations Fall 2013 Transition Faults and Transition Path Delay Faults: Test Generation, Path Selection, and Built-In Generation
More informationSoft-Core Embedded Processor-Based Built-In Self- Test of FPGAs: A Case Study
Soft-Core Embedded Processor-Based Built-In Self- Test of FPGAs: A Case Study Bradley F. Dutton, Graduate Student Member, IEEE, and Charles E. Stroud, Fellow, IEEE Dept. of Electrical and Computer Engineering
More informationTailoring Tests for Functional Binning of Integrated Circuits
2012 IEEE 21st Asian Test Symposium Tailoring Tests for Functional Binning of Integrated Circuits Suraj Sindia Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, Alabama,
More informationAN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS
International Journal of Engineering Inventions ISSN: 2278-7461, www.ijeijournal.com Volume 1, Issue 8 (October2012) PP: 76-80 AN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS B.Prathap Reddy
More informationMultiple Fault Models Using Concurrent Simulation 1
Multiple Fault Models Using Concurrent Simulation 1 Evan Weststrate and Karen Panetta Tufts University Department of Electrical Engineering and Computer Science 161 College Avenue Medford, MA 02155 Email:
More informationBuilt-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs Shyue-Kung Lu and Shih-Chang Huang Department of Electronic Engineering Fu Jen Catholic University Hsinchuang, Taipei, Taiwan 242, R.O.C.
More information298 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 35, NO. 2, FEBRUARY 2016
298 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 35, NO. 2, FEBRUARY 2016 Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation Joon-Sung
More informationExact Functional Fault Collapsing in Combinational Logic Circuits
xact Functional Fault Collapsing in Combinational Logic Circuits Robert Chang, ep eyedi, Andreas Veneris Magdy. Abadir University of Toronto Motorola Dept C 77 W. Parmer Toronto, ON M5 3G4 Austin, TX 78729
More informationReconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center University of Texas at Austin {kjbala,touba}@ece.utexas.edu
More informationEfficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition
Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector Decomposition Jinkyu Lee and Nur A. Touba Computer Engineering Research Center University of Teas, Austin, TX 7872 {jlee2, touba}@ece.uteas.edu
More informationDelay Test with Embedded Test Pattern Generator *
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 29, 545-556 (2013) Delay Test with Embedded Test Pattern Generator * Department of Computer Science National Chung Hsing University Taichung, 402 Taiwan A
More informationGeneration of Compact Test Sets with High Defect Coverage
Generation of Compact Test Sets with High Defect Coverage Xrysovalantis Kavousianos Krishnendu Chakrabarty * Dept. of Computer Science, University of Ioannina Dept. of Electrical & Computer Engineering,
More informationImproving Encoding Efficiency for Linear Decompressors Using Scan Inversion
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion Kedarnath J. Balakrishnan and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering
More informationWITH integrated circuits, especially system-on-chip
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006 1227 Improving Linear Test Data Compression Kedarnath J. Balakrishnan, Member, IEEE, and Nur A. Touba, Senior
More informationFaults. Abstract. 1. Introduction. * Nur A. Touba is now with the Department of Electrical and Computer Engineering, University of Texas, Austin, TX
s Abstract While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo-random testing of bridging faults and describes a means for achieving high fault coverage
More informationTest/Repair Area Overhead Reduction for Small Embedded SRAMs
Test/Repair Area Overhead Reduction for Small Embedded SRAMs Baosheng Wang and Qiang Xu ATI Technologies Inc., 1 Commerce Valley Drive East, Markham, ON, Canada L3T 7X6, bawang@ati.com Dept. of Computer
More informationDeterministic BIST ABSTRACT. II. DBIST Schemes Based On Reseeding of PRPG (LFSR) I. INTRODUCTION
Deterministic BIST Amiri Amir Mohammad Ecole Polytechnique, Montreal, December 2004 ABSTRACT This paper studies some of the various techniques of DBIST. Normal BIST structures use a PRPG (LFSR) to randomly
More informationSYNTHESIS OF MAPPING LOGIC FOR GENERATI TRANSFORMED PSEUDO-RANDOM PATTERNS FOR
SYNTHESIS OF MAPPING LOGIC FOR GENERATI TRANSFORMED PSEUDO-RANDOM PATTERNS FOR Nur A. Touba and Edward J. McCluskey Center for Reliable Computing Departments of Electrical Engineering and Computer Science
More informationTIMING-INDEPENDENT TESTING OF CROSSTALK IN THE PRESENCE OF DELAY PRODUCING DEFECTS USING SURROGATE FAULT MODELS *
TIMING-INDEPENDENT TESTING OF CROSSTALK IN THE PRESENCE OF DELAY PRODUCING DEFECTS USING SURROGATE FAULT MODELS * Shahdad Irajpour Sandeep K. Gupta Melvin A. Breuer Department of EE Systems, University
More informationX(1) X. X(k) DFF PI1 FF PI2 PI3 PI1 FF PI2 PI3
Partial Scan Design Methods Based on Internally Balanced Structure Tomoya TAKASAKI Tomoo INOUE Hideo FUJIWARA Graduate School of Information Science, Nara Institute of Science and Technology 8916-5 Takayama-cho,
More informationAn enhanced barrel shifter based BIST scheme for word organized RAMs (EBBSR).
An enhanced barrel shifter based BIST scheme for word organized RAMs (EBBSR). M.leela vinoth krishnan Depatment of Electronics and Communication, CEG-Anna university, Chennai, INDIA. Krishnan7_ece@yahoo.co.in.
More informationParallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 35, NO. 7, JULY 2016 1219 Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores Taewoo
More informationFault diagnosis of VLSI designs: cell internal faults and volume diagnosis throughput
University of Iowa Iowa Research Online Theses and Dissertations Fall 2012 Fault diagnosis of VLSI designs: cell internal faults and volume diagnosis throughput Xiaoxin Fan University of Iowa Copyright
More informationMULTIPLE FAULT DIAGNOSIS FOR HIGH SPEED HYBRID MEMORY ARCHITECTURE
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 2, Issue. 5, May 2013, pg.33
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 10 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Content Manufacturing Defects Wafer defects Chip defects Board defects system defects
More informationDesign for Test of Digital Systems TDDC33
Course Outline Design for Test of Digital Systems TDDC33 Erik Larsson Department of Computer Science Introduction; Manufacturing, Wafer sort, Final test, Board and System Test, Defects, and Faults Test
More informationTesting Digital Systems I
Testing Digital Systems I Lecture 6: Fault Simulation Instructor: M. Tahoori Copyright 2, M. Tahoori TDS I: Lecture 6 Definition Fault Simulator A program that models a design with fault present Inputs:
More informationBIST-Based Test and Diagnosis of FPGA Logic Blocks
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRUARY 2001 159 BIST-Based Test and Diagnosis of FPGA Logic Blocks Miron Abramovici, Fellow, IEEE, and Charles E. Stroud,
More informationENG04057 Teste de Sistema Integrados. Prof. Eric Ericson Fabris (Marcelo Lubaszewski)
ENG04057 Teste de Sistema Integrados Prof. Eric Ericson Fabris (Marcelo Lubaszewski) Março 2011 Slides adapted from ABRAMOVICI, M.; BREUER, M.; FRIEDMAN, A. Digital Systems Testing and Testable Design.
More informationContents 1 Basic of Test and Role of HDLs 2 Verilog HDL for Design and Test
1 Basic of Test and Role of HDLs... 1.1 Design and Test... 1.1.1 RTL Design Process... 1.1.2 Postmanufacturing Test... 1.2 Test Concerns... 1.2.1 Test Methods... 1.2.2 Testability Methods... 1.2.3 Testing
More informationTest Set Compaction Algorithms for Combinational Circuits
Proceedings of the International Conference on Computer-Aided Design, November 1998 Set Compaction Algorithms for Combinational Circuits Ilker Hamzaoglu and Janak H. Patel Center for Reliable & High-Performance
More informationA Universal Test Pattern Generator for DDR SDRAM *
A Universal Test Pattern Generator for DDR SDRAM * Wei-Lun Wang ( ) Department of Electronic Engineering Cheng Shiu Institute of Technology Kaohsiung, Taiwan, R.O.C. wlwang@cc.csit.edu.tw used to detect
More informationUse of Hierarchy in Fault Collapsing
Use of Hierarchy in Fault Collapsing Raja K. K. R. Sandireddy Intel Corporation Hillsboro, OR 9724, USA srkkreddy@gmail.com Vishwani D. Agrawal Auburn University Auburn, AL 36849, USA vagrawal@eng.auburn.edu
More informationAn Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy
An Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy A. Sharone Michael.1 #1, K.Sivanna.2 #2 #1. M.tech student Dept of Electronics and Communication,
More informationRTL Scan Design for Skewed-Load At-Speed Test under Power Constraints
RTL Scan Design for Skewed-Load At-Speed Test under Power Constraints Ho Fai Ko and Nicola Nicolici Department of Electrical and Computer Engineering McMaster University, Hamilton, ON, L8S 4K1, Canada
More informationVLSI Architecture to Detect/Correct Errors in Motion Estimation Using Biresidue Codes
VLSI Architecture to Detect/Correct Errors in Motion Estimation Using Biresidue Codes Harsha Priya. M 1, Jyothi Kamatam 2, Y. Aruna Suhasini Devi 3 1,2 Assistant Professor, 3 Associate Professor, Department
More informationHardware Sharing Design for Programmable Memory Built-In Self Test
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 10, Issue 6 (June 2014), PP.77-83 Hardware Sharing Design for Programmable Memory
More informationEvaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor M. Enamul Amyeen Srikanth Venkataraman Ajay Ojha Sangbong Lee Intel Corporation, Hillsboro, OR (md.e.amyeen srikanth.venkataraman
More informationFACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis Vivekananda M. Vedula and Jacob A. Abraham Computer Engineering Research Center The University of Texas at Austin
More informationA Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods
International Journal of Scientific & Engineering Research, Volume 4, Issue 4, April-2013 664 A Study on the Testing of VLSI Systems Using Reduced Power Consumption Methods Debasmita Hazra Abstract- This
More informationAt-Speed On-Chip Diagnosis of Board-Level Interconnect Faults
At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults Artur Jutman Tallinn University of Technology artur@pld.ttu.ee Abstract This article describes a novel approach to fault diagnosis suitable
More informationLow-Power Weighted Pseudo-Random BIST Using Special Scan Cells
Low-Power Weighted Pseudo-Random BIST Using Special Scan Cells Shalini Ghosh 1, Eric MacDonald 2, Sugato Basu 3, and Nur A Touba 1 1 Dept of Electrical & Computer Engg University of Texas at Austin Austin,
More informationChapter 9. Design for Testability
Chapter 9 Design for Testability Testability CUT = Circuit Under Test A design property that allows: cost-effective development of tests to be applied to the CUT determining the status of the CUT (normal
More informationSelf-Repair for Robust System Design. Yanjing Li Intel Labs Stanford University
Self-Repair for Robust System Design Yanjing Li Intel Labs Stanford University 1 Hardware Failures: Major Concern Permanent: our focus Temporary 2 Tolerating Permanent Hardware Failures Detection Diagnosis
More informationConflict Driven Techniques for Improving Deterministic Test Pattern Generation
Conflict Driven Techniques for Improving Deterministic Test Pattern Generation Chen Wang & Sudhakar M. Reddy. Elec. & Comp. Eng. Department University of Iowa, Iowa City, IA ~rith ~omeranz~ School of Elec.
More informationE-LEARNING TOOLS FOR DIGITAL TEST. S. Devadze, R. Gorjachev, A. Jutman, E. Orasson, V. Rosin, R. Ubar. Tallinn Technical University, Tallinn, Estonia
E-LEARNING TOOLS FOR DIGITAL TEST S. Devadze, R. Gorjachev, A. Jutman, E. Orasson, V. Rosin, R. Ubar Tallinn Technical University, Tallinn, Estonia Abstract This paper describes tools used in an e-learning
More informationAn Area-Efficient BIRA With 1-D Spare Segments
206 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 26, NO. 1, JANUARY 2018 An Area-Efficient BIRA With 1-D Spare Segments Donghyun Kim, Hayoung Lee, and Sungho Kang Abstract The
More information