International Journal of Scientific & Engineering Research, Volume 4, Issue 10, October ISSN

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1 International Journal of Scientific & Engineering Research, Volue 4, Issue 0, October Design an Encoding Technique Using Forbidden Transition free Algorith to Reduce Cross-Talk for On-Chip VLSI Interconnect Souvik Singha, G.K. Mahanti Abstract - In this work, we propose a CODEC design for the forbidden transition free crosstalk avoidance CODEC. Our apping and coding schee is based on the binary nuber syste. In this paper we investigate and propose a bus forbidden transition free CODECs for reducing bus delay and our experiental results shows that the proposed CODEC coplexity is orders of agnitude better copared to the existing techniques. We used the concept of binary Fibonacci representation of integers and gave a siple recursive procedure to generate crosstalk delay code. Based on the idea, we now give a coding technique by considering a variant of binary Fibonacci representation. Here we use a variant of binary Fibonacci representation by considering the Fibonacci nuber {F, F 2, F 3, F 4 } as the basis eleents of binary Fibonacci nuber syste. By considering F as one of the basis eleents of the binary Fibonacci nuber syste, we can eliinate the possibility of siultaneous opposite transaction on adjacent lines, thus crosstalk delay can be prevented. We use the notation F to represent the set of -bit crosstalk delay free binary Fibonacci code words where the weight of i th bit is the value of i th Fibonacci nuber i.e. F i, i, in the sequence {,,2,3,5}. Now here our apping and coding schee is based on the Fibonacci nuber syste and the atheatical analysis shows that all nubers can be represented by forbidden transition free (FTF) vectors in the Fibonacci nueral syste (FSN). Crosstalk induced delay and power consuption have becoe a ajor deterinant of the syste perforances. Reducing crosstalk can greatly boost the syste perforance. So the design is highly efficient, odular and can be easily cobined with a bus partitioning technique. Index Ters- Bus Encdoing, Cross-talk, Delay, Fibonacci Nuber,Transition Free Algorith. perforance near identical and both ethods approach the INTRODUCTION theoretical lower bound. The FPF is slightly better, but by Crosstalk induced delay and power consuption have no ore than one wire. becoe a ajor deterinant of the syste perforance. Due to the non-linear nature of these codes, Reducing crosstalk can greatly boost the syste researchers have struggled to find a apping schee that perforance. is atheatically systeatic and efficient to ipleent. Bus encoding Schees can achieve the sae Since its coplexity grows exponentially with the bus size aount of bus delay iproveent as passive shielding [6] [7, 9]. with a uch lower area overhead. This code is coonly We have recently proposed systeatic apping referred to as Crosstalk Avoidance Codes (CACs). CACs schees in this work and we focus on the code design for can be eory less [4, 7, 8] or eory based [7]. Meory the FTF-CAC. We give the atheatical analysis of the based coding approaches generate a code word based on apping schee and the coding algorith based on the the previously transitted code and the current data word apping schee []. We also investigate ipleentation to be transitted. So this type of codes needs fewer issues and copare the coplexity of the code with the additional bus wires. The eory-less coding approaches, codes for FPF-CACs which we developed. But the on the other hand, use a fixed code book to generate a coparison shows that the existing FPF-CAC CODEC in codeword, norally it is solely based on the current input sipler and faster and our algorith based approach is data. The ost efficient eory-less code are forbidden also sipler and faster and both coplexity in sae. So the pattern-free (FPF) CACs and FTF- CACs. Their overhead proposed CODEC is also easier to use in conjunction with bus partitioning. The key contributions of this paper are: the presentation of a atheatical forula based on the Souvik Singha is doing his research work in National Institute of FNS which introduces an elegant and efficient apping Technology, Durgapur, India, PH E-ail: singha.souvik@gail.co between data words and code words. G. K. Mahanti is presently a professor in the departent of Electronics and Counication Engineering, NIT, Durgapur, India, PH E- ail: gautaahanti@yahoo.co 203

2 International Journal of Scientific & Engineering Research, Volue 4, Issue 0, October DELAY ESTIMATION FOR ON- CHIP BUS CROSS-TALK An interconnect delay is in proportion to the product of resistance and capacitance of the interconnect wire. The capacitance of the interconnection consists of CL, which is capacitance between the wire and the substrate, and CI, which is the capacitance between adjacent wires. In conventional LSI, vertical capacitance is usually larger than horizontal capacitance, because of large space between adjacent wires and low aspect ratio of cross- section of a etal wire. In present and future VLSI inter- wire coupling capacitance CI becoe doinant because horizontal shrink progress leaving vertical shrink not to cause resistance increase. So the large horizontal capacitance akes crosstalk interference between adjacent wires a serious proble in VLSI design. The crosstalk is a noise caused by inter- wire coupling capacitance between adjacent wires, and causes logic alfunctions and delay fault. C I Coonly used nueral systes include decial, binary, hexadecial. The Fibonacci-based nueral syste N(F{0,}) is the nueral syste that uses Fibonacci sequence as the base. In FNS, a nuber v is representing as the suation of soe Fibonacci nubers and defined as, v = k = d k. f k Where dk ϵ{0, } and fk is the k th Fibonacci nuber defined in previous (). The Fibonacci-based nueral syste is coplete but abiguous; therefore any nuber has at least one, but possibly ore than one representation in FNS. Now we give a very iportant identity of the Fibonacci sequence is 2 k = 0 f = f k + So we see that range of an -bit Fibonacci vector is [0, f+2] (2) (3) 3 FORBIDDEN PATTERN FREE CACS A forbidden pattern free code is a set of code words which do not contain forbidden patterns on any 3 adjacent bus bits. Forbidden patterns are defined as the two 3-bit patterns 00 and 0. So the axiu cardinality of FPF codeword is 2f +; where f is the th eleent in the Fibonacci sequence defined as f C L SUBSTRATE 0 = f where the iniu value 0 corresponds to all the bits dk being. Therefore a total of f = 2 distinct values can be represented by -bit Fibonacci vectors. 5 MAPING SCHEME THEOREM : Let dd- d2d= v, dd- d2d Fig : Scale- down Coupling Capacitance ϵ N {F (0, )} and dd- d2d is forbidden transition free code, v ϵ[0, f+2-]. Now we have seen that any data words can be represented at the code words, so the Theore states that for any nuber v [0, f+2], there exits at least one -bit Fibonacci vector d d -.. d2d = v. which represent this nuber and satisfies the forbidden transaction free property. if = 0 if = 0 + f 2 if 2 4 FIBONACCI- BASED NUMER SYSTEM A nuerical syste is a fraework where nubers are represented by nuerals in a consistent anner [0]. () In other words, a nuber of any values in the range of [0,f+2] can be apped to an bit FTF code word in the FNS space. Proof: let us first define V00 as the set of all the k-bit Fibonacci vectors which the two ost significant bits (MSBs) of 00, we have V00 ϵ [0, f k] based on (3). Siilarly, we define set V0, V0 and V. V0 ϵ[f k-, fk+], V0 ϵ [fk, 2fk] and V ϵ[fk+, fk+2]. This is also shown in figure. We can see fro Figure that the ranges of these four sets 203

3 International Journal of Scientific & Engineering Research, Volue 4, Issue 0, October of vectors overlap. For any vector v V0, we can add an equivalent vector in V00 and dk- is coded as d k- = 0 if v < f k+, Fig 2: Range of the vectors with MSBs of 00, 0, 0 and or V0. Siilarly, any vector v V0 can be replaced by an equivalent vector in V0 or V. Now for a given nuber v, we can add an bit vector Vin = dd-...d2d in FNS that represents this value (based on the copleteness of FNS). Now assuing 0 to be the prohibited pattern at dkdk-, we can replace dkdk-...d with an equivalent k bit vector in V00 or V0 to produce a new bit vector Veq that is equivalent to Vin. Veq has no prohibited pattern at dkdk-. Also since 0 is the prohibited pattern at dkdk-, the prohibited pattern at dk+dk and dk-dk-2 is 0. We know that The first condition guarantees that the anipulations do not introduce a prohibited pattern into d.dk. The second condition guarantees that further anipulation does not destroy the pattern in dkdk-. 6 CROSSTALK AVOIDANCE CODE DESIGN To design a coding algorith that aps each input value to FTF code words in the FNS, we observe that in Figure, if dk is coded as, the 0 is eliinated on dkdk-. Conversely, if dk, is coded as, and dk- coded as 0 if v < f k-, d k- = 0 is eliinated on dkdk-. Based on the above observations, the coding algorith is straightforward. Algorith generates FTF code words with 0 prohibited at d2k+d2k and 0 prohibited at d2kd2k-. If Vin does not have the prohibited pattern, Veq does not have the prohibited pattern either since Algorith FTF encoding algorith the anipulation cause the kth bit value to either FTF (V, ) change fro 0 to or no change.. r+ = V an 2. Repeat 3 to 4 while k 2 Veq does not have the prohibited pattern at dk-dk-2 3. If ( rk+ F2 k/2 +) then dk since dk- in Veq is 0. = 0 else dk = 4. rk = rk+ fk.dk, k - -; 5. d = r2 0 if v < f k+, The encoding is carried out sequentially in - stages, siilar to a division operation. Starting fro the MSB, each stage copares the input to a Fibonacci nuber and produces a coded bit as well as a reainder. The reainder fro one stage becoes the input to the next stage. 0 if v < f k, 203

4 International Journal of Scientific & Engineering Research, Volue 4, Issue 0, October Algorith FTF encoding algorith Input V r+ = V For k = down to 2 do If ( rk+ F2 k/2 +) then dk = 0 else dk = end If rk = r k+ fk.dk end For d = r Algorith shows that an - bit FTF vector is generated in stages. Each stage outputs one bit of the output vector (dk) and the reainder (rk) that is the input to the following stage. In the kth stage, the input rk+ is copared to two Fibonacci nubers fk+ and f k. If rk+ F2 k/2 +, dk is coded as ; If rk+ < fk, dk is coded as 0; If the value rk+ is in between, dk is coded to the sae value as dk+. It encodes d by coparing the input v with only one Fibonacci nuber f+. The correctness of Algorith can be proven by showing that if after the k th stage, the partially generated output vector d,,dk+ dk is FTF, adding the output of (k-) th stage, dk- will not introduce a forbidden pattern. Now we see the total coplexity of above algorith is O () as sae as that of []. Now the equation is: Here each stage produces a single bit dk and a reainder rk. The encoder stages ipleent the arithetic function given in (4). Each stage produces a single bit dk and a reainder rk. For the MSB stage, the input rk+ is the input data to be encoded. For other stages, rk+ is the reainder of the preceding stage. If is even, the ipleentation requires one coparator, one adder and one 2: MUX. If is odd, the ipleentation only needs one adder and one MUX since the adder (subtraction) also functions as a coparator. Assuing the resources required for a coparator are sae as an adder, the total resources required for an bit bus encoder is 3/2 adders and MUXs. The nuber of bits reduces onotonically fro the MSB stage to the LSB stage. Reference [] shows that to reduced the cross-talk both Algoriths and get sae coplexity. So we have introduces one ore Algorith that is two bit pattern which is given below. If we cobine every two stages in the encoder properly, the logic can be further siplified. Let 0 be the prohibited pattern for dkd k-. So the two-bit encoder stage ipleents the following: 7 IMPLEMENTATION AND RESULTS 00 if r k+ < f k, A direct ipleentation of the encoder and decoder based d k d k- = 0 if r k+ < f k+, on algorith and equation 2 is illustrated. The encoder, which converts an n bit binary vector v = bn.b to an (5) bit vector dd-.d, consists of - stages. The r k+ if r k+ < f k, decoder converts the bus code words back to the original n bit binary vector. r k- = r k+ - f k if r k+ < f k+, Now we have applied an arbitrary decial r k+ f k+ nuber 9 that can be represented a crosstalk forbidden Equation (5) can be ipleented using two adders and transition free vector that is (000) and (000). two MUXs. Since the single-bit stage ipleentation Already as we have entioned in our introduction requires three adders and two MUXes to encode two bits, part that if a forbidden sequence present into our code this two-bit stage ipleentation is sipler. We should word then it increase the cross-talk. So on the above work point out that this siplification is only achieved when 0 we have proposed one Algorith by the help of [], in is the prohibited pattern. We can not reduce the which the forbidden transition will not be occurs in the ipleentation coplexity if 0 is the prohibited pattern code word, so whatever the code word will be fored that in the two bit ipleentation. So the algorith is will be forbidden transition free and in this way we can reduced the cross-talk. For clarity, we refer to a vector in the binary nuerical syste as a binary vector or binary code and a vector in the Fibonacci nueral syste as a Fibonacci vector or Fibonacci code. rk = rk+ fk. dk 0 if r k < f 2[k/2]+, (4) 203

5 International Journal of Scientific & Engineering Research, Volue 4, Issue 0, October Algorith 2 FTF encoding algorith Input V: R + =V; For k = down to 2 IF ( r k+ < f k ) then dk dk- = 00 Else IF ( r k+ < f k+) then dk dk- = 0 Else dk dk- = End IF IF (r k+ < fk ) then r k- = r k + Else IF (r k+ < f k+) then r k- = r k+ f k Else r k- = r k+ f k+ End if End for d = r 2 ; [2] C. Duan, V. Cordero and S. P. Khatri, Efficient On-Chip Crosstalk Avoidance CODEC Design, IEEETransactions on VLSI Systes, to appear. [3] Madhu Mutya, Preventing Crosstalk Delay using Fibonacci Representation, Intl Conf. on VLSI Design, 2004, pp [4] Bret Victor and K. Keutzer, Bus Encoding to Prevent Crosstalk Delay, ICCAD, 200, pp [5] C. Duan and S. P. Khatri, Exploiting Crosstalk to Speed up Onchip busses, DATE 2004, pp [6] M. Mutya, ACM Transactions on Design Autoation of Electronic Systes, Vol. 4, No. 3, pp. Article 43, pp. -20, 2009 [7] C. Duan, K. Gulati and S.P. Khatri, Meory-based Cross-talk Canceling CODECs for On-chip busses, ISCAS 2006, pp 4-9. [8] C. Duan, A.Tiruala and S.P.Khatri, Analysis and Avoidance of Cross-talk in On-chip Bus, HotInterconnects, 200,pp [9] S.R. Sridhara, A. Ahed, and N. R. Shanbhag, Area and Energy- Efficient Crosstalk Avoidance Codes for On-Chip busses, Proc. of ICCD, 2004, pp 2-7. [0] Wikipedia, Nueral Syste, Now the overall coplexity in encoding approach we get O (). By help of above algorith we will get the codeword with Forbidden transition free and its coplexity in coparison to Algorith is twice. CONCLUSION The Fibonacci based nuber syste is coplete but abiguous; therefore, any nuber has at least one, but possibly ore than one representation in FNS. In this work, we present a code design for the FTF- CAC based on the Fibonacci nueral syste. Here we develop the forbidden pattern free algorith and copare to existing algorith we get the sae coplexity that is roughly O() and we given the input that is v = 9, we get the result 000 and it is Forbidden Transition Free vector. Our analysis show that all nubers can represented by FTF vectors in Fibonacci nueral syste. Copared to the CODEC for the FTF-CAC, the arithetic operations are less coplicated, results in further coplexity reduction in ipleentation. REFERENCES [] C.Duan, C.Zhu, S.P.Khatri, Forbidden Transition Free Crosstalk Avoidance CODEC Design DAC 2008, June 8-3, 2008, Anahei, California, USA, pp