A Fast Multi-Objective Genetic Algorithm for Hardware-Software Partitioning In Embedded System Design

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1 A Fast Multi-Obective Genetic Algorith for Hardware-Software Partitioning In Ebedded Syste Design 1 M.Jagadeeswari, 2 M.C.Bhuvaneswari 1 Research Scholar, P.S.G College of Technology, Coibatore, India 2 Departent of EEE, P.S.G College of Technology, Coibatore, India eail: agadee_ra@rediffail.co Abstract This paper proposes a novel Multi-Obective Evolutionary Algorith for hardware software partitioning of ebedded systes. Custoized genetic algoriths (GA) have been effectively used for solving coplex optiization probles (NP Hard) but are ainly applied to optiize a particular solution with respect to a single obective. Many real world probles in ebedded systes have ultiple obective functions like area, perforance, power, latency etc., which are to be axiized or iniized at the early stage of the design process. Hardware- software partitioning of ebedded systes involves partitioning the syste specification into hardware and software ipleentations with the goal to find a set of ipleentations that satisfy a nuber of constraints on cost and perforance. In this paper a novel ultiobective algorith called elitist non-doinated sorting genetic algorith (NSGA-II) is applied to search for ultiple optial solutions, the knowledge of which helps the designer to copare and choose a coproised optial solution for which hardware/software design can be ipleented. The algorith was ipleented in C prograing language. The application and adaptation of the NSGA-II algorith and Weighted-Su genetic Algorith (WSGA) was analyzed for a well known 8- point FFT algorith which can also be extended for 16-point FFT etc. Fro the siulation results NSGA-II was found to perfor better than WSGA. Keywords: Hardware-Software Partitioning, Ebedded Systes, Genetic algorith, NSGA-II, Pareto-optial solutions. 1. Introduction Today s coputer systes consists of both hardware and software coponents. For instance, in an ebedded signal processing application it is coon to use both application-specific hardware accelerator circuits and general-purpose, prograable units with the appropriate software. This is beneficial since application-specific hardware is usually uch faster than software but it is also significantly ore expensive. Software on the other hand is cheaper to create and to aintain, but is slow. Therefore perforance-critical coponents of the syste should be realized in hardware and non-critical coponents in software. This way good trade-off between cost and perforance can be achieved. Hence Hardwaresoftware partitioning is an iportant proble in all aspects of design and genetic algoriths are used for solving NPcoplete probles. One of the ost crucial design steps in Hardware-software partitioning is to decide which coponents of the syste should be realized in hardware and which ones in software. The effectiveness of a HW-SW design in ters of syste execution tie, area, power consuption, etc, are priarily influenced by partitioning decisions. The ebedded systes are often developed with off-the-shelf icroprocessors/ digital signal processors/ icro controllers/ ASICs and FPGAs with an ai to iniize the obectives like developent tie and area of any application. Genetic algorith approach to ulti-obective optiization proble has a nuber of obective functions that are to be axiized or iniized. Multi-obective evolutionary algoriths are the best choice because of the population-based approach. The attractive feature of ulti-obective evolutionary algoriths is their ability to find a wide range of non-doinated solutions close to the true pareto-optial solutions. All non-doinated solutions discovered by a ulti-obective Genetic algorith are considered as elite solutions. Elitist echanis does not allow an already found pareto-optial solution to be deleted in the entire population. However, ipleentation of elitis in ulti-obective optiization is not as easy as in singleobective optiization ainly due to large nuber of possible elitist solutions. Elitist ulti-obective evolutionary algoriths are faster and better than other algoriths. In this paper a novel fast elitist non-doinated sorting genetic algorith based approach used for functional partitioning proble is discussed which ais to iniize dual obectives while eeting both constraints. Functional partitioning has several advantages that ake it a good technique for Hardware Software Codesign as it is possible 1

2 to obtain software solutions as well as hardware ipleentations copared to structural partitioning which results in hardware ipleentations only. The odularity and scalability of the two algoriths naely NSGA-II and WSGA for an industrial application: an FFT engine was analyzed. Hardware/Software ipleentation was effectively obtained. The outline of this paper is as follows. Section 2 reviews related partitioning algoriths and application of genetic algoriths to partitioning proble. Section 3 odels partitioning as ulti-obective proble. Section 4 presents the ethod of optiization through NSGA-II algorith. Analysis and the Siulation results of FFT engine are presented in section 5 and the conclusion is presented in section Related Works In Reference [1] the essential criteria needed for partitioning was described with no specific algoriths for partitioning. Ernst in [2] presented a softwareoriented approach. Siulated annealing was used to find out the optiized cobination of hardwarerealized and software-realized functions to get axiu perforance under the given syste cost constraint yielding a long run tie. In Reference [3] certain partitioning issues without specific algorith are discussed. In [4] a hardware/software algorith was proposed which finds a feasible hardware/software partition, which leads to the iniu hardware cost design. Firstly whole functions were ipleented by software then gradually oved to hardware to find a reduced syste hardware cost. A coparison between the coon heuristic-based algoriths like Tabu search, Siulated annealing and Genetic algorith is reported in [4].In [5] a binary-constraint search algorith is used for iniizing the hardware. Hardware Software codesign for DSP applications are discussed in [6]. Plenty of algoriths based on heuristic approach like Global critically local phase (GCLP) [7], Kernighan/Lin (KL), also known as incut graph partitioning heuristic [8], and the iterative algorith in [9,10]. All of the above citations ai to optiize only one obective [11, 12]. [13] Reviews the ethod for generating pareto optial solutions in bilateral negotiations. The ethod of ulti obective optiization for ebedded syste explained in [12] was used. The FFT algorith used as a case study in [14] was used for optiizing dual obectives like area cost and developent tie (Processing Tie). 3. Partitioning Proble An ebedded syste represented in the for of a Directed Acyclic Graph is taken for analysis shown in Fig. 1. A Directed Acyclic Graph (DAG) or a task graph [1], G (V, E), where V is the set of tasks (nodes) and the edge E, representing the data dependency between the two tasks with V {v 1, v 2, v i } and E {e 1, e 2, e i }, which describes the data exchange between the nodes Figure. 1. Data Flow Graph & Input File The Chroosoes are ade up of units called genes. Individuals for a population. The individual is characterized by a chroosoe with an aount of genes equal to the nuber of functional blocks, with each gene representing a block in the syste. These nodes (blocks) are apped to either software or hardware by partitioning algoriths that search large nuber of solutions. Binary encoding schee is eployed. Chroosoe which characterizes an individual is defined as {b 1, b 2, b 3, b 4...b n ), bi {1, 0}, i {1, 2..n}, where n is the nuber of blocks in the ebedded syste. If b i = 1 the corresponding block can be ipleented in hardware and If b i = 0 the corresponding block can be ipleented in software as shown in Fig.2. SW gene 0 6 HW gene Chroosoe Chroosoe Chroosoe Population 1 Population 2 Figure 2: GA chroosoes for partitioning proble. Each Vertex (node) in the graph G is a block or coponent of an architecture associated with four non-negative nubers with t H as Hardware-execution tie i, i.e, the tie required to execute the function on the hardware unit, t S as the Softwareexecution tie i, i.e, the tie required to execute the function corresponding to v i on the processor, the hardware ipleentation of the function requires area C H on the hardware unit, the Software ipleentation of the function requires eory Cost C S on the Software unit and the Counication Costs. Counication costs are considered only when the coponents of the syste have different ipleentations (Hardware or Software). In this exaple the software cost is neglected as it is assued that there is sufficient eory for prograing and each node are also assued to be a coarse-grain task. 2

3 These algoriths ipleented in [4] are guided by estiators, which evaluate the cost function for each partitioning. The saller the value of the function, the better is the ipleentation. The aor drawback is that the population tends to converge to solutions that are very superior in one obective, but very poor at others. Thus ulti-obective genetic algorith is applied to this proble to iniize ore than one obective when the functional units are apped to hardware or software. 3.1 Multi Obective Genetic algorith: Weighted Su Approach (WSGA) Being a population based approach, GA are well suited to solve ulti-obective optiization probles. A generic single-obective GA can be easily odified to find a set of ultiple non-doinated solutions in a single run. The initial population P 0 is created randoly with chroosoe individuals as depicted by the ethod in figure2. The Obective function is calculated as follows: Minz= w 1 z 1 (x) + w 2 z 2 (x) +... w k z k (x) Where z i (x) is the noralized obective function and w i =1. In this optiization proble, each solution x i in the population uses a different weight vector w i = {w 1, w 2,.,W k } in the calculation of the obective function. Weight vector w i is ebedded within the chroosoe of solution x i. Hence ultiple solutions (Obectives) can be siultaneously searched in a single run. In addition weight vectors can be adusted to proote diversity of the population. Crossover and utation are done to create next generation population fro the parent population. Genetic algorith uses two operators to generate new solutions fro existing ones: crossover and utation. The crossover operator is the ost iportant operator of GA. In cross over, generally two chroosoes, called parents are cobined together to for new chroosoes called offspring. The parents are selected aong the existing chroosoes in the population with preference towards fitness so that the offspring is expected to inherit good genes which ake the parents fitter. By iteratively applying the crossover operator, genes of good chroosoes are expected to appear ore frequently in the population, eventually leading to convergence to an overall good solution. The type of crossover used in this proble is single point crossover. The utation operator introduces rando changes into characteristics of the chroosoes by flipping any one bit in the chroosoe if the utation probability is satisfied. Mutation is generally applied at the gene level. In typical GA ipleentations, the utation rate is very sall, typically less than 1%. Therefore, the new chroosoe produced by utation will not be very different fro the original one. Mutation plays a crucial role in GA. It reintroduces genetic diversity back into the population and assists the search escape fro local optia. Figure 5 depicts the process of bit utation on individuals. In this exaple bit 3, 5 and 6 are utated by siply flipping the bits fro 1 to 0 and vice versa. Hence these offspring s are used to for the new population P t+1. The procedure is repeated until the nubers of specified generations are reached. The Crossover Probability of 0.9 and utation probability of 0.01 is used Figure.3. Before Single Point Cross Over Single point crossover is depicted in figure 4 and 5. The bit strings after the crossover point are interchanged Figure 4. After Crossover Figure 5. Mutation Parent 1 Parent 2 Offspring 1 Offspring 2 Offspring 1 Offspring 2 A well known FFT algorith is used for verification. The DAG of 8-point FFT algorith is presented in figure6. This algorith is chosen in the sense of the extendibility of the proble size. It can be extended fro 8-point to 16-point FFT and even beyond by using the sae paraeterisable butterfly node. Nodes 1, 2, 3 are used for arranging input data, tasks 4 to 15 are butterfly coputation nodes. The rest of the nodes are duy nodes for inputting and outputting data and they are ipleented in software. The data s required for processing in the proposed algorith is obtained fro [13]. The counication costs for the above exaple is considered negligible and the software cost is assued to be zero considering that there is enough eory in the processing syste. The two obectives used to guide the algorith are (i) Developent Tie T i (ii) Area cost C i which are to be iniized [4]. The fitness function used is defined by expression T = ( t Hi * gene + t Si * gene ) C = ( C Hi * gene + C Si * gene + Counication Costs). 4. Optiization using NSGA II Genetic algoriths are capable of sapling large and coplex search spaces for ultiple pareto-optial solutions in parallel. For a ulti-obective optiization proble siple GA will not work because these algoriths can suit better only for single obective optiizations and hence ulti-obective evolutionary algorith (called NSGA-II) Proposed by Deb [8] was used for the proble analysis. Elitist Non-doinated GA differs fro siple GA ainly by two ethods (i) Selection: Non-doinated Sorting of individuals in the population Rt (ii) Fitness assignent 3

4 Procedure: Generation of parent and offspring population by crowding tournaent selection operator Source duy node Butterfly node a w N k b Sink duy nodes Figure.6. DAG for 8-point FFT Algorith A =a+bw K N B=a-bw K N 4.1 Non-doinated sorting of Individuals NSGA-II In NSGA-II, the offspring population Q t is first created using a randoly generated parent population P t. A non-doinated sorting is used to classify the entire population Rt to identify which solutions enter the next generation. This allows a global non-doination check aong the offspring and parent solutions. The algorith for ipleenting the sorting procedure is given below. Algorith For i=1 to 2N do For =1 to 2N do If (!=i) then Copare Population (i) and Population () for all M obectives If for any Population (i) is doinated by Population () ark Population (i) as doinated. endif endif The solutions, which are not arked, are called nondoinated solutions, which for the first nondoinated front in the population. The process is repeated for other higher non-doination fronts until all the populations are classified into different fronts. 4.2 Fitness Assignent procedures Fitness assignent in NSGA-II is done by two ethods. (i) Identify the different nondoination fronts f i, i=1, 2, etc. (ii) Apply Crowding Strategy to generate next generation population. Given a set of n k solutions in the k th nondoinated front the crowding sort procedure described in [8] is perfored in the following way for each solution i=1,2,3 n k Step1: Let the nuber of non-doinated fronts be denoted as l= F. For each i in the set assign d i =0. Step2: For each obective function =1, 2,..M, sort the indices vector I = sort (F,>). Step3: For =1, 2 M (Nuber of Obectives) assign large distance to the boundary solutions i.e., di 1 = di l =, and for all other solutions =2 to l-1, assign ( I 1) ( I + 1) f _ f di = di + (1) ax in f f Step4: The next generation parent population P t+1 are filled after sorting the crowding distance values di in descending order. Step5: The next generation offspring population Q t+1 is generated by crowding tournaent selection procedure and by cross over and utation. Step6: Repeat fro step 1 (the non-doinated sorting procedure) and the whole process is continued till the required generations are reached. Index I denotes the solution of th eber in the sorted list. The second ter in the equation (1) is the difference in the obective function values between two neighboring solutions on either side of solution I. Hence for any solution I the solutions (i+1) and (i-1) need not be neighbors in all obectives, ainly for large values of M. The paraeters f ax and f in can be set as the th obective function value when all the blocks are ipleented in hardware or software and vice versa respectively. The overall process proposed for hardware software functional partitioning of ebedded systes is given by the flow diagra as in figure Siulation results The ai of the NSGA-II algorith is to generate ultiple pareto-optial solutions, which the designer can use at the early stage of the design process to copare and choose the optial partitions required. Siulation was carried out in a Pentiu IV processor using C prograing language in Linux environent. The DAG shown in figure 6 is used. Population size of 50 was used with a single point crossover probability and utation probability of 0.9 and (one by chroosoe length) respectively. To assess the results of NSGA-II algorith, WSGA algorith and an exhaustive search was ipleented and copared. Saple rando population of the offspring Q t (Size N) was created fro the initial parent population P t (Size N) and they are cobined to for a new population R t (Size 2N). Then a non-doinated sorting is perfored to classify the entire population (Size 2N) into different non-doination fronts as indicated in Table1. Though this ethod requires ore coputation effort, it allows a global non-doination check between the parent and offspring solutions. The fronts with lesser nuber (front 1) are better non-doinated fronts and are assigned higher fitness value copared to the one with larger nuber (front 2). The populations corresponding to the higher fitness value are best fit to enter into next generation. To obtain the new parent population, for the next generation, the new population is filled by solutions of the different nondoinated 4

5 Populat ion Rt=Pt U Qt Gen = Gen +1 t=t+1 Start Generate Parent Population Pt Pt=Rt Gen =0 Deterine the Obective functions for each individual Perfor the nondoinated sorting to Rt Perfor crowding sort to obtain new population Is cond et? Display Results Select the ating pool Cross over and Mutate Generate new children population Qt Figure7. Flowchart for the Proposed Process Table 1: Non-doinated Sorting of given population Esti Area Saple Binary Value ated Cost Tie Front Id Parent Population Pop Pop Pop Pop Pop Offspring Population Pop A Pop B Pop C Pop D Pop E front s one at a tie. The filling begins with Front 1, and then Front 2, followed by Front 3 and so on. As the entire population size of Rt is 2N, not all the fronts can be accoodated in the N slots available in the new parent population. The fronts, which cannot be accoodated, are deleted. When the last allowed front is considered, there ay be ore solutions in the last front than the reaining slots to be filled in the new population. Instead of randoly discarding soe solutions fro the last front, a niching strategy or crowding strategy is used to include the solutions of the last front that are present in the least crowded region (Larger Distance) in that front. Table 2: Fitness Assignent Front 1 Sorting Crowding Pop Cost Tie Cost Tie Distance IX I VII III VIII II VI IV A III VII B II VIII C I IX D V V E IV VI The crowding distance of individuals in the population of front1 in Table 1 is calculated using equation (1) and is indicated in Table2. The individuals are filled in the new population in the ascending order of the crowding distance. Accordingly pop {1, C, B, 3, 2} are selected fro front 1 to enter into new parent population for next generation. After the new parent population (P t+1 ) is identified then tournaent selection is done to select the ating pool, followed by crossover and utation to obtain next generation offspring (Q t+1 ). Then the process is repeated for required nuber of generations. NSGA-II, WSGA algoriths was siulated and the results obtained were plotted as shown in Figure 8. Fro the figure it can be seen that the plot of NSGA-II algorith coes closer to the pareto optial obtained using the exhaustive search ethodology. Soe of the solutions obtained by WBGA are away fro the pareto optial set. The solutions obtained by siulation of the two algoriths are given in Table 3 and 4. Table 3 shows the final solutions obtained by NSGA-II within 5 generations. Each solution represents the nodes to be ipleented in hardware or software with its cost and tie of ipleentation. Table 4 shows the final solutions obtained by WSGA after 100 generations. Finally the perforance etrics evaluating closeness of the obtained solutions to the pareto-optial front naely Error Ratio (ER), Generational Distance (GD), Maxiu Pareto- Optial Front Error (MFE), Spread ( ), and Weighted Metric (W), which cobines both the converging ability (GD) and diversity-preserving ability ( ), was deterined [12] and the obtained values are tabulated in Table 5. It is seen that ulti obective genetic algorith based on Weighted Su approach has difficulty in finding solutions uniforly distributed over the search space. In addition not all pareto-optial solutions can be investigated resulting in a higher error ratio. The etric ER takes a value between zero to one. Saller this value eans ore nuber of solutions are eber of pareto-optial front. The etric GD finds the average distance of obtained solutions fro the pareto-optial front. The algorith having a sall value of GD is better. MFE coputes the worst distance aong all the ebers of the solutions obtained. This gives a conservative easure of convergence. An algorith finding a saller value of the Spread etric is able to find better diverse set of nondoinated solutions. It was found that NSGA-II perfored better in all etrics copared to WSGA. The less value of ER, GD, MFE, and W indicates that the solutions obtained by NSGA-II are closer to true pareto optial solutions than WSGA. The algorith which has an overall sall value of weighted etric (w) eans that it is good in both the converging ability and diversity-preserving ability. 5

6 Output Table 3: Optial Solutions Optial Solution by NSGA-II ( 5 Generations ) Node Estiat Area Ipleentation ed Cost Process in HW Tie Solution Solution Solution Solution Solution Solution Solution Solution Solution Solution Output Table 4: Optial Solutions Optial Solution by WSGA (100 Generations) Node Ipleentation Area Cost Estiated Tie process in HW Solution A Solution B Solution C Solution D Solution E Solution F Solution G Solution H Solution I Solution J Solution K Solution L Solution M Solution N Solution O Table 5. Perforance Metrics Method ER GD(γ) MFE W NSGA-II Weighted Su GA(WSGA) Conclusion In this paper a novel-partitioning algorith based on Elitist Non-doinated Sorting Genetic Algorith (NSGA-II or ENGA) for the hardware/software partitioning of ebedded systes is proposed and copared with Weighted-Su genetic algorith (WSGA or WBGA). The siulation results obtained shows that the proposed NSGA-II algorith is an efficient way to search for optiu solutions very fast. Multi-optial solutions for the functional partitioning of ebedded systes were achieved with in few generations (5 generations) when copared to WSGA (100 generations). The closeness to pareto optial solutions are deterined by calculating the perforance etrics. The cobined Converging Ability and Diversity-Preserving Ability calculated using the weighted etric was also iproved (23.34) for the proposed NSGA-II algorith. The sae algorith can be extended for functional partitioning of ebedded systes with larger nuber of functional blocks (50, 100, 200 etc.). Further this algorith can also be used for optiizing ore than two obectives (like power, latency etc.) by slightly changing the Obective or Fitness function. Figure 8: Siulation Results References [1] D.Thoas, J.Adas and H.Schitt,, A Model and Methodology for Hardware/software Codesign, IEEE design and test of coputers, pp 6-15, [2] J.Ernst, J.Henkel, T.Benner, Hardware Software Cosynthesis for Microcontrollers, IEEE Design and Test of Coputers, pp , [3] Sung Joo Yoo, Jinhwan Jeon, Seang Soo Hong, Kiyoung Choi, Hardware Software Codesign of Resourceconstrained Real-tie Systes, Proceedings of the IEE, [4] J. I. Hidalgo and J. Lanchares, Functional partitioning for hardware-software codesign using genetic algoriths, Proceedings of the IEEE, pp , [5] Frank Vahid, ie Gong and Daniel D.Gaski, A Binary Constraint Search Algorith for Miniizing Hardware during Hardware/Software partitioning, ACM transactions, pp , [6] A Kalavade and E.Lee, A hardware/software Codesign Methodology for DSP applications, IEEE design and test of coputers, [7] A.Kalavade and E. Lee, A global critically/local phase driven algorith for the constrained hardware/software partitioning proble, Hardware/Software Codesign, pp.42-48, [8] B.W.Kernighan ans S. Lin, An efficient heuristic procedure for partitioning graphs, Bell Syste Technical Journal, pp , [9] K.S.Chatha and R.Veuri, An iterative algorith for partitioning and scheduling of area constrained HW-SW systes, IEEE International Workshop on Rapid syste Prototyping, pp , [10] K.S.Chatha and R.Veuri, An iterative algorith for hardware-software partitioning, hardware Design space exploration and Scheduling, Journal of Design Autoation for Ebedded Systes, vol.5, pp , [11] Goldberg, D.E., Genetic algoriths for search, optiization and achine learning, Pearson Education Asia Pte Ltd, [12] Kalyanoy Deb, Multi-obective Optiization using Evolutionary Algoriths, John Wiley and Sons Ltd, [13] Zichen Yang and Bo Meng, AMulti-Obective Genetic Algoriths Method for Generating Pareto Solutiopns in 6

7 Bilateral Negotiations, Proceedings of 4 th World Congress on Intelligent Control and Autoation, pp , [14] Theerayod Wiangtong, Hardware/Software partitioning and scheduling for Reconfigurable Systes, Ph.D thesis, Iperial College, London, M.Jagadeeswari received her B.E Electronics and Counication Engineering fro Governent College of Technology, Coibatore and ME (Applied Electronics) fro P.S.G College of Technology, Coibatore in the year 1992 and 1999 respectively. She is presently working as Assistant Professor in the departent of Electronics and Counication Engineering at Sri Raakrishna Engineering College, Coibatore. She is currently pursuing her Ph.D fro Anna University, Chennai and is a research scholar at P.S.G Tech Coibatore. She has published 5 research papers in the National & International Journals/ Conferences. Her research interests are VLSI design, Hardware Software codesign, Coputer architecture and Genetic algoriths. Dr.M.C.Bhuvaneswari is a faculty in the departent of Electrical and Electronics Engineering, P.S.G College of Technology, Coibatore. She has copleted her B.E in Electronics and Counication Engineering in 1986, fro Governent College of Technology, Coibatore. She has obtained her Doctoral degree in the area of VLSI Design and Testing, fro P.S.G College of Technology, affiliated to Bharathiar University in She has published 26 research papers in National & International Journals / Conferences. Her areas of interest are VLSI Design and Testing, Coputer Architecture, Genetic Algoriths and Fuzzy Logic. 7