RECONFIGURABLE AND MODULAR BASED SYNTHESIS OF CYCLIC DSP DATA FLOW GRAPHS

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1 RECONFIGURABLE AND MODULAR BASED SYNTHESIS OF CYCLIC DSP DATA FLOW GRAPHS AWNI ITRADAT Assistant Professor, Departent of Coputer Engineering, Faculty of Engineering, Hasheite University, P.O. Box 15459, Zarqa 13115, Jordan E-ail: ABSTRACT The conventional high level synthesis techniques target DSP algoriths onto architectures using basic functional units such as adders or ultipliers. In this paper, a schee for the partitioning of the data flow graph of a DSP application for a high-level synthesis aied at a design using ulti-odules is proposed. In the propose schee, the regularity characteristics of DSP application are exploited. Moreover, in order to reduce the nuber of distinct odules, the near-isoorphis sub-graphs represents the odules are erged together by ultiplexing the in tie to produce a single adaptable odule. This erging process enables the reuse of the adaptable odules by partially reconfiguring the at run tie to realize different odules during the running of the DSP data flow graph. Furtherore, a novel reconfigurable ultiplier ultiplier is incorporated in the proposed synthesis technique. It is seen that a sall overhead in ters of the architecture s controller is needed by the odules in order for the to be adapted to perfor different coputations (ulti-odes). Keywords: Architectural Synthesis; Reconfigurable Multiodule; Tie Scheduling, Reconfigurable Processing Units 1. INTRODUCTION Soe of the applications that need a high-level synthesis are digital signal processing (DSP), counications, and iage processing. These applications are aong the ost iportant applications that deand high coputational power, and ust be executed at a very high speed to enable real-tie processing. Due to the parallelis within the DSP applications, parallel processing architectures are a natural choice for the synthesis of these applications. Moreover, the need to reduce the design tie of digital systes, and thus, the tie to arket is increasingly crucial factor to have a copetitive edge. Such an advantage can be achieved if there are efficient techniques to reduce the tie taken by each of the individual steps of the design process. The design cycle of a digital syste is coposed of three aor steps: RTL design, Physical ipleentation and Verification or Validation at various levels of design and ipleentation. A ulti-odule design could be an attractive platfor to reduce the overall design tie by reducing the tie of the steps of the design cycle following the step at which the odularity is introduced. There exist a variety of architectural synthesis techniques, ost of which target DSP algoriths onto ultiprocessor architecture using basic functional units such as adders or ultipliers [1][2]. This however results in inferior ipleentation of DSP applications, since the regularity feature of DSP application are not exploited. Furtherore, hardware flexibility is a crucial factor in today s syste design. However, such flexibility ust not be gained at the expense of perforance and area, as is the case with generalpurpose reconfigurable fabrics such as field prograable gate-arrays (FPGAs) [3]. Hybrid FPGAs and reconfigurable cores provide hardware flexibility, their coarse integration of fixed logic and reconfigurable fabric results in perforance, area and power penalties [4]. New techniques have therefore been explored to add flexibility to individual hardware coponents without the penalties associated with FPGAs. To overcoe the latter penalties, sall-scale reconfiguration would iniizes the area and delay penalties by inserting into fixed-logic only the iniu aount of reconfigurable logic and interconnect and by reusing the ain part of the available logic and by changing the status of a few control signals to achieve the desired coponent functionality. In this paper, a schee for the architectural synthesis of DSP applications based on adaptable ulti-odules is proposed. The regularity characteristics of DSP applications are identified by eploying the so called regularity extraction. Then, 443

2 those near-isoorphis odules (sub-graphs) are erged together by ultiplexing the on tie. The original data flow graph (DFG) represents the DSP application is reconstructed by using the extracted and erged odules. Scheduling and allocation techniques are proposed to ap the DSP application onto reconfigurable ulti-odule structure. The proposed architectural synthesis technique operating on the cyclic ulti-odule based DFG of a DSP algorith is designed to deterine the relative firing ties of the nodes by using Floyd-Warshall's longest path algorith [5] so that the throughput is aied to be axiized and the nuber of distinct odule resources is aied to be iniized. 2. SCHEME FOR MULTI-MODULE SYNTHESIS The data flow graph (DFG) is proven to be an efficient representation of the syste specification due to its ability to expose the hidden concurrency between the operations of the underlying algorith. Since DSP applications are known for their inherent parallelis, the DFG odel is suitable for the DSP applications. Moreover, regularity is an inherent feature of several VLSI systes, especially those we find in signal processing applications. Data flow graph representations is an efficient to exploit such regular characteristics of such applications. Unfortunately, ost of architectural synthesis algoriths proposed to-date ai to provide a generalized approach to synthesis, without usually uch regard to the special characteristics of the syste being synthesized. An efficient work on regularity extraction could be found in [6]. We present in this paper an approach to highlevel synthesis (specifically, scheduling and odule allocation) that is aied to exploit the inherent characteristics of DSP circuits. We assue here that the designer has the behaviour of the filter in ters of its dataflow graph. We propose that such behavioural data-flow graphs can be abstracted as a collection of identical or near-identical odules (sub-graphs), each of which represents a part of the behaviour. The flow graph of these odule is the one on which we perfor the scheduling and odule allocation. Thus, hardware sharing is now done on the odule (sub-graph), rather than on individual functional units like adders and ultipliers. Once each of the odule teplates is fully characterized, we are left with the task of having to schedule the ulti-odule based graph. The overall synthesis schee involves the following steps. 1. Identification of coon odule structures: The coputation odule structures can be identified by using regularity extraction algorith [6]. 2. Reconstruction of the data flow graph representing the DSP application using the newly identified odule structures. 3. Deterination of the coputational delay of each odule. This is done by the synthesis of the internal odule coputations. 4. Scheduling of the newly constructed cyclic data flow graph (the odule-based DFG). 5. Allocation of odules onto ulti-odule structures. 6. Synthesis of control structures: In this step the control signals specifies the data flow of the algorith are retargeted for synthesising the base odule structures. 3. TIME SCHEDULING AND ALLOCATION OF MULTI- MODULE FLOW GRAPH After the extraction of the regular odules of a DFG, this original DFG is reconstructed by clustering those coputations having isoorphis with the extracted odules. Those coputations which are not covered by any odule because they don t have an isoorphis with any extracted odule are considered as if they are separate odules. A odule-based graph G can be represented by the pair (M, E), where M is a set of nodes (odules), and E is a set of eleents called edges. Each edge is associated with a pair of odules. The sybols 1, 2,... n 1, n are used to represent the odules, and the sybols e 1, e2,... are used to represent the edges of a graph. A direct path P is a finite sequence of distinct odules k, 1,..., k and distinct edges such that the edge ( i, i+ 1) is present in the pathp. If k = k then this path is called a directed circuit or loop. Each loop in a DSP graph ust contain at least one ideal delay eleent for the graph to be coputable. The data flow graph that contains at least one directed circuit is called the cyclic graph, otherwise it is acyclic. In order to find the best assignent of the odules in a odule-based DFG, the allocation process needs to know the tie schedule for the nodes or odules. For this purpose, in this section a tie schedule is built. An iterative procedure based on the node obility is eployed. The earliest and the latest firing ties (EFT and LFT) at which each odule can be scheduled to fire are iteratively 444

3 calculated. The odule obility is equal to the difference between its calculated latest and earliest firing ties. These earliest and the latest firing ties are found relative to a reference node. Given a odule-based data flow graph of a DSP application, the tie scheduling can be built using the longest path atrix Q f [5]. The entries of this atrix represent the length of the longest path between each pair of odules ( i ) which is given by f Q i = ax len[ P [ i (1) all P i The earliest firing tie and the latest firing tie for a odule relative to that of a reference odule i are, respectively, given by EFT LFT f = FT ( ) + Q (2) i i f = FT ( ) Q (3) i where FT ( i ) is the firing tie of odule i. To find the earliest and the latest firing ties of node i, the axiu earliest firing tie and the iniu latest firing tie of the odule ust be found relative to all previously scheduled odules. Thus, EFT and LFT of node are, respectively, given by EFT( ) = ax EFT( all i< i i i ) i (4) reconfiguration. Due to the new firing tie of the odule, the tie schedule of other non-scheduled odules ay be affected. This odule is chosen to be the new reference-odule and the rest of all the earliest and latest firing ties for the rest of the non-scheduled odules are calculated. A new odule is chosen for scheduling and the process is iteratively repeated. 3.2 Choosing the firing tie We defined the level of a control step to be the nuber of odules which will eventually occupy this control step. This level deterines the nuber of odule structures required in the ipleentation of the final syste. The chosen odule is scheduled to fire at a control step that would results in a iniu nuber of functional odules required. We defined the level of a control step to be the suation of sub-levels of the different types of operations and given by level = level type 1 + leveltype The choosing of the best firing tie is done by exaining all the control steps within its obility such that total nuber of odule per cycle is iniized, rather than individual odule concurrency. More specifically, find the control step having the iniu total level as a priary key or the iniu sublevel ( level type ) as a secondary key. 3.3 Scheduling algorith The scheduling algorith involves the following steps. LFT( ) = in LFT( all i< ) i (5) Algorith 1 Tie schedule A valid schedule range specifies a valid way to schedule the odule for a given the precedence relations. Thus, the obility is given M v = LFT EFT. as ( ) ( ) ( ) 3.1 The tie schedule The tie schedule is built by selecting a reference-odule and by calculating the obility of all non-scheduled odules with respect to this reference odule. All the non-scheduled odules are put in a list. The odule with the iniu obility calculated thus far is chosen for scheduling first and then reoved fro the list. When choosing between equal obility odules, the selection is ade such that individual odules concurrency is equalized with the previous step. This is to increase the probability that a odule unit would be reused by dynaically reconfiguration a few control signals or even without any 1. Calculate the iniu iteration period. Find the longest path atrix. 2. Take the input odule as the reference and schedule it first to fire at the control step zero. 3. Calculate the earliest and latest firing ties of all the reaining odules with respect to the input odule. 4. Calculate the current schedule range or obility for each of the reaining nonscheduled odules. 5. Schedule all the odules that have zero obility to fire at the only control step in their obility. (Note: There is no need to update the earliest and latest firing ties of the reaining odules after scheduling such a zero-obility odule) 445

4 6. Based on the current obility for each non-scheduled odule, choose one odule as the target odule for the scheduling according to the following priority: a. A odule that has the iniu current obility. If ore than one odule has iniu current obility, chose fro these odules the one that is a predecessor or successor to the current reference odule. b. A odule that is longest coputational tie and a predecessor or successor of any scheduled odule. c. Any first available odule. 7. Within the scheduling range of the target odule, find the best firing tie position as the control step that has the iniu level. If ore than one control step results in the sae iniu possible level, chose iniu sublevel. Set the best firing tie position found as the tie schedule of the target odule. 9. Set the target odule to be the new reference node. Update the earliest and latest firing ties of all the reaining non-scheduled odules. 1. Go to Step 4 until all the odules have been scheduled. 3.4 Multi-odule allocation A straight forward allocating the odules in the data flow graph onto ulti-odule structure fro a tie schedule can be carried out by using an allocation algorith siilar to the one presented in [7]. 4. MERGING OF NEAR-ISOMORPHISM MODULES In order to reduce the nuber of distinct odules in the ulti-odule structure, the subgraphs represent each selected odule are erged together, synthesizing a single reconfigurable odule structure for the near-isoorphis odules. The data-flow graph erging process enables the reuse of hardware blocks and interconnections by identifying siilarities aong the DFGs representing the odules, and produces a single odule structure that can be partially reconfigured at run-tie by setting soe control signals specifically for each odule (sub-graph). Efficient erging techniques can be found in [8] and [9]. In addition to odularity, this erging process results in a data-path having a few and siple hardware blocks (odule units and registers) and interconnections (ultiplexers and wires), which in turn, reduces its cost, area, and power consuption. Achieving such an ai is possible if hardware blocks and interconnections be reused across the application as uch as possible. The odule allocation that is used in the previous section has also a great ipact in reducing the syste reconfiguration overhead, both in tie and space. An exaple of odule erging is shown in Fig. 1. c = Merged = G1 c = 1 Merged = G2 Fig 1: Merging of two odules (sub-graphs) 5. EXAMPLES In this section, we consider two exaples of DSP filters, a fourth-order Jauann filter and fourth-order lattice All-pole filter, in order to deonstrate the proposed synthesis schee. In the two benchark probles, the coputational delays of the addition and ultiplication nodes are assued to be 1 and 5 cycles, respectively. Moreover, the delay of ultiplexer is assued to be equal to that of the adder, i.e., 1 cycle. 5.1 Fourth-order Jauann wave filter The DFG of the fourth-order Jauann wave filter is shown in Fig. 2(a). Fig. 2(b) shows extracted regular odule for this filter. A latency of 8 cycles for this odule is calculated based on its critical path fro input to output. The tie schedule and odule allocation obtained for the ulti-odule based DFG (Fig. 2(c)) by using the proposed technique are given in Fig. 3. It is seen, that the iteration period obtained for this filter using ultiodule structure is 16 cycles which is equal to that using individual hardware functional units. Hence, odularity is gained without penalties in ters of delay or throughput. 5.2 Fourth-order all-pole lattice filter The DFG of the all-pole lattice filter is shown in Fig. 4(a). Fig. 2(b) shows extracted regular odule for this filter. Near-isoorphis odules are identified and then erged by ultiplexing the in tie. So that, this odule structure can be reused for all the odules fro which it is obtained. A c 446

5 latency of 8 cycles for this odule is calculated based on its critical path, i.e. (+, *, MUX, +). The tie schedule and odule allocation obtained for the ulti-odule based DFG are given in Fig. 5. Fig. 6 shows the status of the reconfiguration control signals that are dynaically changed each iteration of execution. Fully-regular and reconfigurable ulti-odule structure is obtained, but associated with a penalty of 2 cycles in ters of iteration period. out out1 in in 1 4 Fig 2: (A) Data Flow Graph Of Fourth-Order Jauann Wave Filter (B) Module Structure (C) Modular Structure Of The Jauann Wave Filter Fig 3: Tie Schedule Of Multi-Module Based Fourth-Order Jauann Filter 447

6 in out c out 1 in 1 c 1 Fig 4: (A) Data Flow Graph Of Fourth-Order All-Pole Filter (B) Module Structure (C) Modular Structure Of The All-Pole Filter Fig 5: Tie schedule of ulti-odule based fourth-order all-pole filter C = C = 1 C 1 = C 1 = 1 C = 1 C = 1 C 1 = 1 C 1 = 1 Fig 6: Reconfiguration Control Signals Of Each Adaptable Module 6. INCORPORATION OF RECONFIGURABLE PROCESSING UNIT We incorporate dynaically reconfigurable functional units [1][11] in the extracted odules in order to increase regularity and optiize the area of each odule. The reconfigurable ultiplier is eployed in the proposed schee since it is capable of ipleenting both ultiplication and addition (in fact, it can perfor two or ore data-independent additions in parallel) with the sae delay as a fixed 448 logic ultiplier and with very sall area overhead. Given the regularity occurrence of MAC operations in DSP algoriths, such dynaically reconfigurable functional unit provides significant benefits for DSP applications. The goal of the proposed technique is to ake use of this orphable ultiplier in a hybrid library of functional units coposed both operation-specific and reconfigurable functional units supporting sets of different operators. Figure 7 (a and b) gives an exaple of the use of reconfiguarable functional units in building the RTL odules.

7 c c (a) c c Fig 7: (A) A Module With Basic FU (B) A Module With Reconfigurable FU Incorporated (b) Fig 8: Iteration Period Obtained For DSP Applications Targeting Modular Architectures With And Without Reconfigurable Processing Units 7. INCORPORATION THE PROPOSED SCHEME IN MULTI-MODE ARCHITECTURES DSP APPLICATIONS The schees proposed in [12] and [13] address the design of ulti-ode architectures for digital signal processing applications. The ulti-ode or ulticonfiguration architectures are specifically designed for a set of tie-wise utually exclusive applications (ulti-standard applications) [12]. One of the goals of ulti-ode architecture design is to iniize the area reusing the resources effectively aong the different odes. The proposed schee is very uch suitable for such applications. Hence, we have incorporated our proposed schee of odular and reconfigurable synthesis into such ulti-ode DSP application. 449

8 Fig 9: Modular Synthesis Results In Ters Of Area For Four Set Of Multi-Mode DSP Applications With And Without Reconfigurable Processing Units 8. EXPERIMENTAL RESULTS We have carried out several experients with soe well-known set of DSP applications coonly used in the literature of architectural synthesis. Moreover, we have used the Synopsys Design Copiler (DC) synthesis tool, which perfors different levels of optiization, i.e., architectural, logic- and gate-level optiization to synthesize the obtained odular RTL structures. The reconfigurable orphable ultiplier shown in [11] is eployed. It is shown in [11] that an extra area is required to be added in order to introduce ode2 (reconfiguration to adder) to a fixed ultiplier. For exaple, an additional area overhead of 1.5% is required to ipleent one 32-bit Adder in a reconfigurable 16x16-bit orphable ultiplier RC- PM 1 A. If ode2 has two adders (RC-PM 2 A ), the area overhead is pushed up significantly to be 11.4%. Noralized to the area of 32-bit Adder X: The area of the fixed 16x16-bit pipelined ultiplier is 4.77X, of the fixed ultiple-operation (ALU) is 6.1X, and of the reconfigurable pipelined ultipliers RC-PM 1A and RC-PM 2 A, are 4.84X and 5.32X, respectively. Figure 8 suarizes the synthesis results of schedules obtained for 4 DSP filters in the two cases: (a) only operation-specific functional units (b) hybrid library of functional units. It is seen that iteration period obtained for the tie schedule targeting odular architectures with reconfigurable functional units in reduced copared to that obtained using only operationspecific functional. Another experient is carried out. We choose four sets of DSP applications for our experient, naely, set1: HOUGH-TRNS, BIQUAD, FFT, PFILTER, set2: FIR19, FIR15, FIR11, FIR7, set3: LMS16, FIR16, set4: FIR64, FIR32, FIR16. Figures 9 shows the synthesis results obtained in ters of area. It is seen that a significant reduction in ters of the area is achieved by using the proposed schee for odular architecture with reconfigurable processing units in ulti-ode DSP applications. 9. CONCLUSION In this paper, we have iproved the schee proposed in [14] for odular synthesis in which the high level synthesis of DSP applications apped onto dynaically reconfigurable and odular architecture has been introduced. We have incorporated reconfigurable processing units into the proposed schee. Furtherore, it has been applied to ulti-ode DSP applications. The regularity characteristics of DSP application have been exploited. Near-isoorphis sub-graphs have been erged together by ultiplexing the in tie. The DFG of the DSP application is reconstructed based on the extracted odules. Scheduling and ulti-odule allocation techniques have been proposed. The proposed techniques have been used to obtain the tie schedule and ulti-odule structures for DSP applications. The proposed 45

9 technique has been applied to well-known benchark probles of Digital filters showing that a dynaically reconfigurable ulti-odule architecture brings about a trade-off between the odularity, throughput, and area. REFERENCES [1] Y.-N. Chang, C.-Y. Wang, and K. K. Parhi. Loop-list scheduling for heterogeneous functional units, in Proc.6th Great Lakes Syposiu on VLSI, pp. 2 7, March [2] Z. Shao, Q. Zhuge, C. Xue, and E.H.-M. Sha Efficient assignent and scheduling for heterogeneous DSP systes, IEEE Tran. on Parallel and Distributed Systes vol. 16, pp , June 25. [3] K. Copton and S. Hauck. Reconfigurable coputing: A survey of systes and software, ACM Coputing Surveys, vol 34, no. 2, 22, pp [4] R. Tessier and W. Burleson., Reconfigurable Coputing for Digital Signal Processing: A Survey, Journal of VLSI Signal Processing, vol 28, no. 1, pp.7 27, 22. [5] R. W. Floyd, "Algorith 97: shortest path," Counications of ACM, vol. 5, no. 6, pp. 345, [6] D. Sreenivasa Rao and F. J. Kurdahi, Partitioning by regularity extraction, in Proc. 29th DAC, June 1992, pp [7] A. Itradat, M.O. Ahad, and A. Shatnawi, Scheduling of DSP algoriths onto heterogeneous ultiprocessors with interprocessor counication, in Proc of 3rd International IEEE-NEWCAS, June 25, pp [8] N. Shirazi, W. Luk, and P. Cheung, Autoating production of runtie reconfigurable designs, in Proc. 6th Syp. FCCM, Apr. 1998, pp [9] Z. Huang and S. Malik, Managing dynaic reconfiguration overhead in systes-on-a-chip design using reconfigurable datapaths and optiized interconnection networks, in Proc. Design Autoation Test Eur. Conf., 21, pp [1] A. Itradat, M.O. Ahad, A. Shatnawi, Architectural synthesis of DSP applications with dynaically reconfigurable functional units, in Proc. of the International Syposiu on Circuits and Systes. ISCAS 27, New Orleans, USA, 27-3 May 27, pp [11] S. M. S. A. Chiricescu, M. A. Schuette, R. Glinton, and H. schit, Morphable ultipliers, in Proc. of 12th International Conference on Field Prograable Logic and Applications (FLP 2),, Montpellier, France, Septeber 22, pp [12] Cyrille Chavet, Caaliph Andriaisaina, Philippe Coussy, Eanuel Casseau, Eanuel Juin, Pascal Urard, Eric Martin, "A design flow dedicated to ulti-ode architectures for DSP applications", in proc. of the 27 IEEE/ACM international conference on Coputer-aided design, Noveber 5-8, 27, San Jose, California. [13] A. Itradat, T. Hayaneh, and A. Qatoo, "Mapping of ultiple data Flow graphs of DSP applications onto ASIC/Reconfigurable architectures," in International Journal of Science and Applied Inforation Technology(IJSAIT), Vol. 2, No. 2, pp , 213. [14] A. Itradat, M.O. Ahad, and A. Shatnawi, Dynaically reconfigurable adaptable ultiodule based synthesis of DSP data flow graphs. In proc. 2th Canadian Conference on Electrical and Coputer Engineering. pp. 1515{1518. IEEE (27) 451