Evolutionary On-line Synthesis of Hardware Accelerators for Software Modules in Reconfigurable Embedded Systems

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1 Evolutionary On-line Synthesis of Hardware Accelerators for Software Modules in Reconfigurable Embedded Systems Roland Dobai Faculty of Information Technology Brno University of Technology Brno, Czech Republic Abstract High-level synthesis ensures that a program code written in a programming language can be easily transferred into a hardware description language and thereby makes the design process faster and less demanding. However, professional synthesis tools are very complex and not well suited for deployment in embedded systems with limited resources. Evolutionary on-line synthesis is proposed in this paper which represents a new way to exploit evolutionary design. The program code is deployed into the processor of a reconfigurable embedded platform and the evolutionary design framework into its programmable logic. The functionality is transferred from software into hardware online, during runtime. The proposed approach serves essentially the same purpose as high-level synthesis but the synthesis can be performed by a simple embedded computational platform and on-line. The approach can offer higher flexibility in contrast with similar conventional approaches because it can develop solutions for unexpected situations. The proposed approach has the advantage over previous evolutionary design systems because no separated training phase is required and the softwarebased (correct) implementation is always available which can be exploited for monitoring and re-evolving the solution if this is necessary. The proposed evolutionary on-line synthesis was evaluated on the problem of image filter design. The achieved results indicate that the automated on-line synthesis based on evolution is possible and it can provide even better results than conventional implementations in specific application domains. I. INTRODUCTION High-level synthesis [1] ensures that a program code written in a programming language can be easily transferred into a hardware description language and thereby it makes the design process faster and less demanding. Professional synthesis tools are very complex and not well suited for deployment in embedded systems with limited resources. An embedded system can rely on high-level synthesis only when all the possible situations which can occur during operation can be predicted in design time (a system or to be more specific, a reconfiguration bitstream must be prepared for each such situation). The system requirements of high-level synthesis does not allow to employ such tools in embedded systems. An evolutionary design framework can be implemented relatively easily in reconfigurable embedded systems [2]. Although it must be designed for a specific application domain but it can ensure adaptive behavior (in the domain) by evolving new solutions (the change of the training data can guide the evolution toward the implementation of a solution for the altered specification). Evolutionary on-line synthesis is proposed in this paper which represents a new way of exploiting evolutionary design. The Zynq-7000 all programmable (AP) system-on-chip (SoC) is used. The program code is deployed into one of the processors available in the platform and the evolutionary design framework into its programmable logic (PL). The functionality is transferred from software into hardware on-line (during runtime). This transfer is guided by the evolutionary algorithm (EA) running in the second processor of the platform. The proposed approach was developed essentially for the same purpose as high-level synthesis but (1) the synthesis can be performed by a simple embedded computational platform, (2) is utilized on-line, and (3) can offer higher flexibility (adaptability) in contrast with similar conventional approaches because it can develop solutions for unexpected situations. The proposed approach has the advantage over previous evolutionary design frameworks because (1) no separated training phase is required (training is performed on-line, during operation) and (2) the software-based (correct) implementation is always available which can be exploited for monitoring and evolving new solutions if this is necessary (previous methods can guarantee a successful evolution only with a certain probability; in the proposed approach the softwarebased implementation is available and can be relied on if the evolution may fail). The rest of the paper is organized as follows. Section II contains the related work. The proposed evolutionary synthesis of hardware accelerators is described in Section III and evaluated by image filter design in Section IV. Section V discusses the achieved results and Section VI concludes the paper. II. RELATED WORK Evolutionary design frameworks implemented in field programmable gate arrays (FPGAs) are usually based on Cartesian genetic programming [2] with two dimensional array of processing elements (PEs). The selected operations of PEs

2 i0 i1 PE1 PE2 PE3 i2 y0 PE4 PE5 PE6 i3 y1 i4 i5 PE7 PE8 PE9 Figure 1. A digital circuit implemented by an interconnected array of PEs PL Inputs 3 TI TI FIFO CPU SWI 5 TI TO 6 RAM RAM 8 10 HWI 9 FU 7 11 Outputs TO 4 TO FIFO and the interconnections define a digital circuit with a given function. An example is shown in Figure 1, where i0,..., i5 are inputs and y0, y1 are outputs. The interconnections are implemented by multiplexers not shown in the figure. It should be noted that not all PEs are used necessarily. For example, PE3 and PE7 do not participate in the implementation of the output functions. The PE can implement operations based on a predefined set ranging from single- to multi-bit and from simple logic to complex arithmetic operations. The possibilities offered by the PE array define the space in which the search for the solution with the required functionality will be performed. An EA is used for performing the search. Several candidate solutions are generated during the search by bio-inspired operators (e.g. mutation). The candidate solution is represented by a chromosome which is a direct encoding of the PE array. All candidate solutions are established in the PE array; training inputs (TIs) are applied to the inputs and the outputs are observed. The outputs are compared with the training outputs (TOs), i.e. the intended (reference) outputs, and the fitness is computed. The fitness represents how close is the functionality of the candidate solution from the desired one and provides the guidance for the EA. New generation of solutions are based with higher probability on candidate solutions with higher fitness. A well tuned EA will perform the search toward candidate solutions with better fitness and the design goal may be achieved with a certain probability (the search is nondeterministic because random decisions are made). In order to ensure a successful search, the parameters of EA need to be tuned for the given application domain [2]. Depending on the used EA, this for example can mean the desired mutation rate (number of random changes in new candidate solutions), size of population, required number of generations. The software-based implementation of EAs can be effectively executed by hard-core processors of FPGAs [3]. The computation of fitness for all candidate solutions is usually a time-expensive operation for which programmable resources of FPGAs can be employed [4]. The latest evolutionary design frameworks utilize dynamic partial reconfiguration (DPR) for establishment of candidate solutions [5] [8]. Several methods were proposed for effective implementation of candidate solutions by programmable resources [9] [11]. CPU 2 EA Figure 2. Software module SWI running in CPU 1 while hardware module HWI is synthesized in parallel by the EA running in CPU 2 III. PROPOSED EVOLUTIONARY SYNTHESIS The proposed approach exploits evolutionary design frameworks for a new purpose: on-line synthesis of hardware accelerators. Firstly, the most time consuming part of the programming code which could be accelerated by hardware is identified. Secondly, an evolutionary design framework is assembled with an array of PEs. The size of the array and the available PE operations are selected based on the expected size of the solution and the application domain. It should be noted that the design of such a system is much trivial than of an (even the simplest) conventional deterministic method [2] (not even considering complex methods with the ability of mapping into reconfigurable resources, and finding the routing for the desired timing constraints). The proposed approach is able to develop hardware-based accelerators in embedded systems with limited resources. Furthermore, the evolved solutions in these accelerators can be even better than those designed by conventional methods because in some cases there is no known optimal specification of the desired behavior (EAs are more successful in these areas). Examples include hashing functions, image filters, classifiers, predictors [2]. The proposed approach shown in Figure 2 can be deployed in a Zynq-7000 AP SoC which contains two central processing units (CPUs) and a reconfigurable PL. The software implementation (SWI) running in CPU 1 is the code selected for acceleration. It transforms some inputs into outputs at a speed determined by the implementation and the performance of CPU 1 (steps 1 and 2 in the figure). A subset of the inputs and outputs (TI and TO) which will be used for training is sent into the PL and stored in first-in first-out (FIFO) memories (3, 4). These inputs and outputs are transferred into randomaccess memories (RAMs) after the whole subset is available in the FIFOs (5, 6). The EA generates a candidate solution and establishes it in the PL (7). The established candidate solution is a hardware implementation (HWI) embodied by an array

3 Table I 8-BIT OPERATIONS OVER OPERANDS a, b IMPLEMENTED BY PES Code Operation Description constant 1 a identity a inversion 3 a 1 right shift by 1 4 a 2 right shift by 2 5 a + b addition 6 a + s b addition with saturation 7 (a + b) 1 average 8 max(a, b) maximum 9 min(a, b) minimum 10 a > 127? b : a conditional selection 11 a b absolute difference Fitness A C B frame 1 frame 2 frame 3 D E Generation Figure 3. Fitness during filter evolution with changing video frames of PEs. The training inputs (TIs) are applied to the inputs of this solution (8) and the outputs are observed (9). The outputs are compared with the expected (training) outputs (10) and the fitness is computed by the fitness unit (FU). The fitness is used by the EA for guiding the search (11). The evaluation of new candidate solutions are performed repeatedly from step 7 to 11. The EA can be implemented very efficiently in CPU 2 (only simple operations are used, e.g. random number generation, change of bit-values). The most time-consuming part of the evolution (evaluation and fitness computation) is executed relatively fast in the PL. Therefore, the evolution can generate and evaluate several generations of candidate solutions while CPU 1 produces only one set of TIs and TOs. This difference in speed is transparent for both CPUs because of the asynchronous FIFOs. The new training set can be stored in the RAMs (5, 6) in parallel with the read (8, 10) and no clock cycles are wasted for waiting. IV. CASE STUDY: IMAGE FILTERING Image filtering is a good domain for evolutionary design because no optimal specification is known for filtering functions and an EA can evolve better solutions than any conventional method following non-optimal specifications [2]. The proposed method is evaluated by evolution of image filters. A filter with 3 3 kernel is used, i.e. the pixel and the eight neighbors are considered in order to determine the new pixel value. All pixels are assumed to have 8-bit precision. The video frame is processed sequentially (one pixel-neighbor at the time). The filter is implemented by a PE array with eight columns and four rows. This size was determined by taking into account the size of other conventional filters (the array is always larger than the expected size but not all PEs are active for all filters). Table I shows the set of operations a PE can implement. This set was influenced by operations frequently used in conventional filters. A simple loss function is used as the fitness, and the EA is set to minimize it. Each filtered pixel is compared with the pixel in the TO reference video frame and the absolute difference is computed. The fitness is given as the sum of these differences determined for all the video frame pixels. The TO reference frame is produced by the software-based (conventional) implementation. Evolutionary strategy is used as the EA. The elite (candidate solution with the best fitness) survives always and becomes a member of the new generation. Therefore, the fitness value has a non-decreasing development (but only while the training video frames are not replaced). This is demonstrated by Figure 3 where approximately 60 generations of candidate filters are generated and evaluated while one training frame is prepared by the other CPU. The best fitness of the generation can remain the same during several generations (between A and B in the figure) and improve (decrease) only occasionally. However, there can be a significant change (even increase) when the video frames are replaced (C, D, E). V. EXPERIMENTAL RESULTS The proposed evolutionary on-line synthesis was evaluated on the problem of image filter design. An XC7Z020 Xilinx Zynq-7000 AP SoC device was used for implementation. The underlying architecture for evolutionary design was adopted from [10] and extended for evaluation of six filters in parallel without degrading the speed of filter evaluation (the previous implementation evaluated filters sequentially). The architecture including the PEs were synthesized by commercial design tools. The PE functions are established by DPR and the interconnections by multiplexers controlled by control registers. It should be noted, that the proposed on-line synthesis is not restricted to the selected architecture for evolutionary design and other architectures could be used also. All the source codes, hardware descriptions and software utilities are available [12]. Two types of image filters were evolved: noise filters and edge detectors. Salt & pepper noise was used during the experiments. Median filter implemented as sorting network and Sobel operator was considered as reference noise filter and edge detector, respectively. The first 3500 video frames from the free movie Big Buck Bunny [13] were applied to the filters after the frames were scaled and transformed to

4 Table II SPEED OF EVOLUTION time [s] frames/s gen/s filt/s gen/frame median Sobel Table III RESOURCE UTILIZATION IN XC7Z020 Site type Used Available Utilization [%] slice look-up tables slice registers block RAM tile resolution and 8-bit gray scale, respectively. The middle area of pixels of the frames were used for training. The size of training images was previously proved to be sufficient for evolving good filters [2], [10]. The experiments were aimed at confirming that evolutionary design platforms can be successfully used for a new purpose: on-line synthesis of hardware accelerators for software modules. Evolutionary strategy (1 + 5) with four mutations was adopted which is a good choice for the given architecture according to previous experiments [10]. Usually, the elite (parent) is not re-evaluated with the new population because the training data does not change (i.e. the fitness of the elite remain valid). The proposed evolutionary synthesis requires the elite to be re-evaluated always because it is not possible to predict when the training data will change (the fitness of the elite need to be valid for the current training set in order to ensure reliable selection based on comparison of fitness values). A. Speed of evolution Table II contains the results concerning the speed of evolution for both noise filtering (median) and edge detection (Sobel). The time column shows the amount of time necessary to process the prepared video frames of the given resolution by CPU 1. These values are different because the speed of software-based implementation depends on the used operations (which are obviously not the same for different software modules). These processing speeds imply 6 7 frames per second and it is obvious that a hardware-based filter implementation could be beneficial. The evolution controlled by CPU 2 is able to process more than 1500 generations per second (creation and evaluation of six filters in all generations mean approximately 9500 filters in each second). As the results indicate, the evolutionary design framework processes more than 200 generations while the software-based implementation processes only one frame (i.e. the frame in the evolutionary design framework is applied more than 200 times to more than 200 new generations of filters). This huge speed difference allows to generate and evaluate an adequate number of filters and consequently, find very good ones. The scaling of the video frames would further improve the quality of evolved solutions. The processing of larger frames takes longer by CPU 1 which means that CPU 2 will be able to generate and evaluate more filters (the size of the training set remains the same). The evolution can be stopped at any time and the evolved filter can be deployed as a hardware-based accelerator. Six filters (all able to work at 300 MHz) can process a video of resolution at the speed of frames per second which is considerable faster than 6 7 frames of the software-based approach. Furthermore, the software-based implementation could exploit various filters at the same time with multiple passes which would provide even better training data for the evolution and the speed of the hardware-based implementation would remain the same. B. Resource utilization Table III shows the resource utilization in XC7Z020 Zynq AP SoC. Less than half of the device is used but the resources are distributed along the chip in order to achieve 300 MHz operational frequency. The implementation supports the deployment of six filters at the time. More filters could be implemented in the given device only at the cost of lower operational frequency. The block RAM tiles are used to implement FIFOs and memories for the training data. Two video frames (reference TI and TO) of size and precision of 8 bits are stored in memories and used for training. The capacity of FIFOs allows to store four video frames (2 TIs and 2 TOs) which ensures that CPU 1 will not need to wait while the evolution for the current frame finishes and the next frame is transferred out from the FIFO for the consequent evolution. C. Quality of the evolved solutions Figure 4 compares the software-based implementation with the evolved hardware-based implementation for two selected video frames. It should be noted that the original frames are shown in the figure for comparison and are not available in the evolutionary design system. The frames were scaled down to 40%. Peak signal-to-noise ratios (PSNRs) are indicated in parentheses. As it can be observed, the evolved solutions (indicated as evolved noise) result in clearer images (for example the details of the grass and trees are more dominant) and produce also better (higher) PSNRs than the softwarebased implementation (shown as median in the figure). The evolution of edge detectors was similarly successful. The evolved solutions (indicated as evolved edge) are acceptable in comparison with the software-based edge detector (Sobel). The evolution starts with random initial population and the search can be characterized as non-deterministic [2]. However, the results are almost of the same quality in all runs thanks to the well tuned EA [10]. This is demonstrated by Figure 5 which contains the lower and upper quartiles of fitness values measured during 30 independent runs. It should be noted that the fitness values are shown only for the best filters of the population (elite) when the video frames change (i.e. moments A, C, D, E in the example in Figure 3). The fitness in the

5 original salt & pepper (17.75 db) median (28.45 db) evolved noise (28.88 db) Sobel evolved edge original salt & pepper (17.89 db) median (32.38 db) evolved noise (33.63 db) Sobel evolved edge Figure 4. Results of video filtering. The filter is continuously evolved without a separated training phase. Original video frames are licensed: (c) copyright 2008, Blender Foundation / figure does not (and need not) progress toward lower values because the training data changes (the non-decreasing property of EAs with elitism can be observed only while the evolution is performed on the same frame).

6 Fitness Frame Figure 5. Lower and upper quartiles of the fitness measured when the video frame changes (30 independent runs are considered; evolution is performed on-line without a separated training phase) The interquartile range (difference between the upper and lower quartiles) is very small which indicates filters of approximately the same quality. VI. CONCLUSIONS Evolutionary on-line synthesis of hardware accelerators for software modules was proposed in this paper which represents a new way for exploiting evolutionary design frameworks. The proposed approach offers similar functionality as highlevel synthesis but the synthesis can be performed by a simple embedded platform. This allows to on-line re-design the system after it was deployed into an environment where subsequent human intervention is not possible. The approach can offer higher flexibility in contrast with similar conventional approaches because it can develop solutions for unexpected situations. Approaches based on EAs usually do not guarantee that an acceptable solution will be found. In the proposed approach the software-based (always correct) implementation is available and can be used while the hardware implementation is under development. And after the hardware implementation is already functional, the software implementation can monitor it and continue the evolution if the hardware implementation does not meet the desired functionality or quality. The proposed evolutionary on-line synthesis was evaluated on the problem of image filter design. The achieved results indicate that the automated on-line synthesis is possible and in specific application domains can provide even better results than conventional implementations. The achieved results can be easily reproduced by the available source codes and hardware descriptions [12]. This work was supported by The European Social Fund (ESF) under the project Excellent Young Researchers at BUT (CZ.1.07/2.3.00/ ) and the Czech science foundation under the project Advanced Methods for Evolutionary Design of Complex Digital Circuits ( S). REFERENCES [1] G. Martin and G. Smith, High-level synthesis: Past, present, and future, IEEE Des. Test. Comput., vol. 26, no. 4, pp , 2009, doi: /MDT [2] L. Sekanina, Evolvable hardware, in Handbook of Natural Computing. Springer Verlag, 2012, pp , doi: / [3] R. Dobai and L. Sekanina, Towards evolvable systems based on the Xilinx Zynq platform, in 2013 IEEE International Conference on Evolvable Systems (ICES), 2013, pp , doi: /ICES [4] L. Sekanina, Virtual reconfigurable circuits for real-world applications of evolvable hardware, in Evolvable Systems: From Biology to Hardware, ser. Lecture Notes in Computer Science, vol Springer Berlin Heidelberg, 2003, pp , doi: / _17. [5] A. Upegui and E. Sanchez, Evolving hardware by dynamically reconfiguring Xilinx FPGAs, in Evolvable Systems: From Biology to Hardware, ser. Lecture Notes in Computer Science, vol. 3637, 2005, pp , doi: / _6. [6] R. Salvador, A. Otero, J. Mora, E. de la Torre, T. Riesgo, and L. Sekanina, Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support, in Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011, pp , doi: /AHS [7] R. Dobai and L. Sekanina, Image filter evolution on the Xilinx Zynq platform, in NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), 2013, pp , doi: /AHS [8] F. Cancare, M. D. Santambrogio, and D. Sciuto, A direct bitstream manipulation approach for Virtex4-based evolvable systems, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp , doi: /ISCAS [9] K. Glette, J. Torresen, and M. Hovin, Intermediate level FPGA reconfiguration for an online EHW pattern recognition system, in NASA/ESA Conference on Adaptive Hardware and Systems, ser. AHS 2009, 2009, pp , doi: /AHS [10] R. Dobai and L. Sekanina, Low-level flexible architecture with hybrid reconfiguration for evolvable hardware, ACM Trans. Reconfigurable Technol. Syst., 2014, doi: (under third review). [11] D. B. Bartolini, M. Carminati, F. Cancare, M. D. Santambrogio, and D. Sciuto, Hera project s holistic evolutionary framework, in Proceedings of the 2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2013, pp , doi: /IPDPSW [12] ZyEHW: Evolvable hardware in the Zynq FPGA platform, dobairoland/zyehw [Online, accessed: ]. [13] Big buck bunny, Blender Foundation, 2008, org [Online, accessed: ].