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1 Florida State University Libraries Electronic Theses, Treatises and Dissertations The Graduate School 2004 A Design Methodology for the Implementation of Fuzzy Logic Traffic Controller Using Field Programmable Gate Array Mandar Shriram Ambre Follow this and additional works at the FSU Digital Library. For more information, please contact lib-ir@fsu.edu

2 THE FLORIDA STATE UNIVERSITY COLLEGE OF ENGINEERING A Design Methodology for the Implementation of Fuzzy Logic Traffic Controller Using Field Programmable Gate Array By Mandar Ambre A Thesis submitted to the Department of Electrical and Computer Engineering in partial fulfillment of the requirements for the degree of Master of Science Degree Awarded: Spring Semester, 2004

3 The members of the Committee approve the thesis of Mandar Ambre defended on April 2, Bing Kwan Professor Directing Thesis Uwe Meyer-Baese Committee Member Simon Foo Committee Member Approved: Reginald Perry, Chairperson, Department of Electrical & Computer Engineering Ching-Jen Chen, Dean, FAMU-FSU College of Engineering The Office of Graduate Studies has verified and approved the above named committee members ii

4 TABLE OF CONTENTS List of Tables...iv List of Figures...v Abstract...vi 1. INTRODUCTION Introduction Fuzzy Logic Traffic Signal System Design Choices FUZZY LOGIC CONTROLLER Introduction to Fuzzy Logic Fuzzy Systems Fuzzy Traffic Controller Fuzzy Implementation Representation of Fuzzy system with N-membership functions MATLAB SIMULATION Introduction Matlab simulation for one-input fuzzy system Matlab simulation for two-input fuzzy system Generating Contents of ROM using Matlab HARDWARE IMPLEMENTATION VHDL Implementation FPGA Implementation VHDL Simulation Waveforms Circuit Implementation using UP 1 Education Board Printed Circuit Board design of the system CONCLUSION Conclusion Future Scope APPENDIX A...66 iii

5 APPENDIX B REFERENCES BIOGRAPHICAL SKETCH iv

6 LIST OF TABLES 1. Table Table Table Table Table v

7 LIST OF FIGURES 1. Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure vi

8 ABSTRACT In this thesis, an approach is proposed for the design and implementation of fuzzy traffic controllers using Field Programmable Gate Arrays (FPGAs).The focus of this study is to develop an effective traffic signaling strategy to be implemented at a typical intersection with four approaches. Adaptive traffic control using fuzzy principles has been demonstrated and reported by the authors in the literature. Here a high-level design approach is suggested, which involves VHDL-based logic synthesis and the use of state diagrams with a VHDL backend for graphical design description. The operations of the fuzzifier and the defuzzifier of the fuzzy controller are described in VHDL. The fuzzy rule base for the controller is described using the state diagrams. Specifically, the fuzzy inference based on the fuzzy rules is implemented using MATLAB code. The output of the MATLAB program is stored in a ROM for use in the VHDL code. Once VHDL code is obtained then the hardware is implemented using the UP1 Education board. After the design was tested by using UP1 board the next step was to design a printed circuit board for this system. This was done by using Protel Design Explorer where the input to the circuit board comes from traffic sensors in the field and the output of the circuit board is given to the traffic controller. vii

9 CHAPTER 1 INTRODUCTION 1.1 Introduction The most desired factor in a traffic controller at an intersection is that it should be adaptive to any changes in the traffic flow. In case of the traffic controllers that are normally used, the relative durations of the red and green phases are determined by computer programming based on the traffic pattern at an intersection. But these traffic controllers are not adaptive because the settings can only be altered manually or by computer commands sent by the traffic control center. This problem is solved by using a fuzzy traffic controller, which is capable of signaling adaptively at an intersection. The intent of this study is to propose a design methodology for modeling fuzzy controllers. In recent years, the interest in implementing fuzzy logic controllers using FPGA and ASIC technologies has been steadily increasing. There have been attempts to combine VHDL for design capture and VHDL-based logic synthesis for designing complex hardware. This thesis suggests the use of state diagrams for capturing a rule base of a fuzzy control system. The advantage of using this high-level approach is that the design time is reduced significantly and different ways of designing a rule base can be explored. The fuzzifier and defuzzifier components of the fuzzy system are described using VHDL code as it involves considerable amount of mathematical computations. A rule base for the controller is described using the state diagrams and this rule base is obtained by using matlab code. The output of matlab code is stored 1

10 in ROM which is used in VHDL code. A complete description of the system is assembled in VHDL and is synthesized using VHDL-based logic synthesis. Once VHDL code is obtained then the hardware is implemented using UP1 Education board. VHDL program is transported from MAX+PLUS II software to FLEX 10K20 FPGA chip on the board using Byte Blaster Parallel Port Download Cable. The input pins on the board can be adjusted to get the desired output that is indicated by LEDs on the board. Once the design was tested by using UP1 board the next step was to design a printed circuit board for this system. This was done by using Protel Design Explorer where the input to the circuit board comes from traffic sensors in the field and the output of the circuit board is given to the traffic controller. 1.2 Fuzzy Logic Fuzzy logic refers to a logical system that generalizes the classical two-value logic for reasoning under uncertainty. It is a system of computing and approximate reasoning based on a collection of theories and technologies that employ fuzzy sets, which are classes of objects without sharp boundaries. More specifically, fuzzy logic generalizes the crisp true-and-false (or black-and-white) concept fundamental to classical logic to a matter of degree. The two key features of fuzzy logic include: (a) A mathematical formalism for representing human knowledge involving vague concepts, and (b) a natural but effective mechanism for systematically formulating cost-effective solutions to complex problems characterized by uncertainty or imprecise information A natural question is why fuzzy logic is effective for traffic control. The answer is simple and has two aspects, both of which stem from the two features described above. The first aspect is that fuzzy logic is well suited for controlling a process or system that is too nonlinear or too poorly understood to use conventional control designs. The second aspect is that fuzzy logic enables control engineers to systematically implement control strategies used by human operators with experience and expertise. 2

11 1.3 Traffic Signal System Traffic Signal Cycle A complete traffic signal cycle in a standard signalized intersection consists of the red phase, the green phase, and the amber (or yellow) phase, which are activated or turned on sequentially in time to control traffic. Only the cars facing an activated green signal have the right of way to cross the intersection moving straightforward, turning left, or turning right. The cars facing an activated red signal do not have the right of way and are forbidden to pass through the intersection. However, it is not uncommon that cars are allowed to make right turns with the red signal on, provided they do not interfere with those cars having the right of way to cross the intersection. The amber phase is activated to signal the transition from the green phase to the red phase. Typically, the amber phase is fixed in duration. The durations of the red and green phases are determined by the prevailing traffic conditions over a large coordinated area Four-way Intersection Figure 1.1 A four-way intersection allowing forward-going, right-turn, and left turn traffic in any approach 3

12 In the development of the fuzzy traffic controller, a four-way intersection of full capacity is considered (refer to Figure 1.1). The key features of the intersection and the associated constraints are noted as follows: (a) The intersection consists of four ways: Approaches 1, 2, 3, and 4, correspond to the northbound, eastbound, southbound, and westbound traffic, respectively. (b) For any approach, the green signals give the left-turn, forward-going, and right-turn traffic the right of way to cross the intersection. In order to avoid conflict, two nonoverlapping time cycles of the green signal are used for the left-turn and forward-going traffic. They are separated by an amber time cycle. Cars are not allowed to enter the intersection when the red signal is on, except that cars are permitted to make right turn when there exists reasonably safe separating distance from the traffic about to enter the intersection with the right of way. (c) For each of the four approaches, two vehicle detectors are assumed to have been installed at appropriate locations to register the number of vehicles queuing up to cross the intersection. (d) The traffic flow rates for the four approaches are random and mutually independent Traffic Control Strategy It has been observed that a very effective control strategy stems from the notion of balanced traffic flow. The principle is straightforward as well as sensible: The cars in an approach with heavier traffic flow is given the right of way to cross the intersection for a time interval longer than an approach with lighter traffic flow. When the traffic flow is about equal in two or more approaches, their corresponding time intervals for passing through the intersection should be about equal. In other words, the objective is to make the number of cars waiting in queue at the intersection about the same in the four approaches. 1.4 Design Choices We have implemented a dedicated fuzzy chip, capable of performing stand alone operations, rather then to extend some general purpose processor with fuzzy instructions. Our decision is influenced by several facts: A dedicated chip offers the highest execution speed 4

13 Design time is short, due to the usage of synthesis and high-level design tools Low cost of real-estate. For designing a rule base of a controller, we have used a high-level modeling approach instead of encoding it directly in VHDL. The reasons for this choice are: A high-level design approach reduces the design time Design functionality is evaluated in a short time Different design choices are quickly explored The design is represented graphically in a natural and understandable way. In describing a fuzzy controller in VHDL, the most time consuming process is writing a synthesizable VHDL description at the register transfer level. The usage of high-level design tools reduces these efforts. 5

14 CHAPTER 2 FUZZY TRAFFIC CONTROLLER 2.1 Introduction to Fuzzy Logic For many engineering-related problems, information can be classified into numerical and linguistic information. Specifically, Numerical Information refers to the objective information that is obtained from mathematical models, physical laws or numerical data collected by sensors from physical processes. Linguistic Information refers to the subjective information that is represented by the rules or linguistic terms based on the experience and knowledge collected form experts. A fuzzy logic system provides the approximation mechanism by which these two forms of information can be incorporated in a systematic manner. A fuzzy logic system is knowledge or rule based system. Fuzzy logic is a convenient way to map an input space into an output space. In essence, a fuzzy system is capable of simultaneously handling numerical data and linguistic knowledge via non-linear maps linking linguistic information and numbers. Fuzzy set theory and Fuzzy Logic establish the specifics of this non-linear mapping Fuzzy logic for traffic control The most desired factor in a traffic controller at an intersection is that it should be adaptive to any changes in the traffic flow. In case of the traffic controllers that are normally used, the relative durations of the red and green phases are determined by computer 6

15 programming based on the traffic pattern at an intersection. But these traffic controllers are not adaptive because the settings can only be altered manually or by computer commands sent by the traffic control center. This problem is solved by using a fuzzy traffic controller, which is capable of signaling adaptively at an intersection. In a narrow sense, fuzzy logic refers to a logical system that generalizes the classical two-value logic for reasoning under uncertainty. In broader terms, fuzzy logic refers to a collection of theories and technologies that employ fuzzy sets, which are classes of objects without sharp boundaries. To contrast, fuzzy logic generalizes the crisp true-and-false (or blackand-white) concept fundamental to classical logic to a matter of degree. The distinct advantages brought forth by fuzzy logic are: (a) The ease of describing human knowledge involving vague concepts, and (b) the enhanced ability to develop cost-effective solutions to practical problems. The two attractive features that motivate the application of fuzzy logic to traffic control are: 1. Fuzzy logic is inherently equipped to work in both the qualitative and numeric domains. 2. Fuzzy logic provides the tools for handling and processing vague concepts described qualitatively by linguistic terms from a natural language. These two features enable fuzzy logic uniquely suited for bridging the gap between the quantitative world and the qualitative world. Hence, these abilities set fuzzy logic distinctly different from other technologies. In addition to providing a cost-effective mechanism to model a complex system involving numeric variables, fuzzy logic offers a qualitative description of such a system that is easy to comprehend. A natural question is why fuzzy logic is effective for traffic control. The answer is simple and has two aspects, both of which stem from the two features described above. In general terms, the first aspect is fuzzy logic is well suited for controlling a process or system that is too nonlinear or too poorly understood to use conventional control designs. The second aspect is that fuzzy logic enables control engineers to systematically implement control strategies used by human operator. More specifically, traffic flow in the roadway system of a city represents a highly nonlinear and complex system, which is not well understood by traffic engineers. Attempts to model traffic flow in a city thus far have not been satisfactory. There still exist a plenty of room for improvement over various control strategies currently deployed. In real-world situations, traffic control strategies used by traffic police officers human operators are considered 7

16 significantly more effective than the automated traffic signal systems installed at intersections. This explains why police officers are called to direct traffic during special events, such as moving traffic efficiently before and after football games. In directing heavy traffic, human operators formulate their control strategies based on imprecise information described in linguistic terms. No processing of quantitative information is involved. In addition, the decisions made by a human operator are solely based on the traffic conditions at that particular intersection. The traffic conditions at other intersections have no bearing on the manner he/she directs traffic. This common practice illustrates two key facts: 1. Human operators are more intelligent than computerized machines. Effective control strategies can be formulated based on the qualitative and imprecise linguistic terms without requiring precise quantitative information. 2. Effective traffic control can be implemented using the decentralized system concept instead of the conventional centralized control system. The conclusion one can reach is that an effective traffic control strategy should include human expert knowledge. Precisely because of this reason fuzzy logic for traffic control is the focus of this study as fuzzy logic allows the integration of human knowledge in the control design process. Linguistic variables A linguistic variable refers to variable assuming words in natural language as its values. In other words, linguistic variables are linguistic terms that take no numerical values and are vaguely described by words. Words such as very small, small, medium, young, and old are examples of linguistic variables used in daily life. Linguistic variable values give rise to the notion of fuzzy sets. Definition: A linguistic variable X is a mapping from the Universe of discourse U to a subset R X of the real line R, X : U R R (2.1.1) X 8

17 2.1.2 Fuzzy sets and membership functions A classical set or crisp set is a set with boundary. Crisp applications are adequate for various applications and an important tool in Mathematics and science. However they do not conform to human nature and thoughts, which are abstract and imprecise. In contrast to crisp set, a fuzzy set is a set without a crisp boundary. This signifies the transition from belong to set and not belong to set is gradual. This smooth transition is characterized by membership functions that give flexibility in modeling linguistic expressions. Definition: If X is the universe of discourse (or universal set) consisting of all elements x of concern in a particular context or application, then a fuzzy set A in X is defined as the set of ordered pairs. { x, ( x) x A X } A = µ A (2. 1.2) where µ A (x) is called the membership function of fuzzy set A. Typically a normalized µ A (.) maps each element x of A to a membership grade in the unit interval [ 0, 1] µ A : x ε A [ 0, 1] (2.1.3) This concept provides a mathematical way of characterizing the fuzzy set. The membership function of an object specifies the degree of similarity with the fuzzy set. Example Figure 2.1 shows the membership functions µ pos (x), µ zero (x), µ neg (x), of three fuzzy sets positive, zero and negative numbers respectively. In this case the universe of discourse represents a set of real numbers. The fuzzy set of positive numbers can be analytically expressed as 9

18 µ pos ( x) 1 if x 1 = 2 0 x 3 if 1 x < 3 otherwise (2.1.4) NEG 1.0 µ( x ) POS ZERO Figure 2.1. Membership functions of positive, zero and negative numbers. The bell-shaped, trapezoidal and triangular functions represent the most commonly used membership functions. In figure 2.1 an instance of trapezoidal and triangular membership functions are displayed. Operations on Fuzzy sets Equality: A B µ ( x) = ( x) = A µ B x RX (2.1.5) Containment: A B µ ( x) ( x) A µ B x RX (2.1.6) Fuzzy Union: A B µ ( x) = max[ µ ( x), ( x) ] A B A µ B (2.1.7) Intersection: A B µ ( x) = min[ µ ( x), ( x) ] A B A µ B x RX (2.1.8) Fuzzy Complement: A µ ( x) = ( x) A 1 µ A (2.1.9) Both the law of contradiction and law of excluded middle do not hold for the fuzzy sets Fuzzy IF-THEN RULE In fuzzy control systems human knowledge is represented in terms of fuzzy IF-THEN rules. A fuzzy IF-THEN rule is a conditional statement expressed as IF < fuzzy proposition> THEN <fuzzy proposition> 10

19 Fuzzy Propositions: Atomic fuzzy propositions An atomic fuzzy proposition is a single statement X is A where X is a linguistic variable and A is linguistic value of X (fuzzy set). Compound fuzzy proposition A compound fuzzy proposition is a composition of atomic fuzzy propositions using the connectives and, or, and not which represent the fuzzy intersection, union and complement respectively. Examples of compound propositions are X is A or X is not A X is not A and Y is B X is A and Y is not B or Z is C where X, Y and Z are linguistic variables, and A, B and C are linguistic values (fuzzy sets) of X, Y and Z respectively. Compound fuzzy propositions are fuzzy relations. Implication: In classical logic relationships are represented by truth tables. Fuzzy logic uses the same principles for interpreting relations. However the logic operators are replaced by the fuzzy operators AND, OR and NOT. Specifically a fuzzy if then rule maybe viewed as a fuzzy proposition or relation of the form Q = (not p) or q Q = p q (2.1.10) Specifically let p is a fuzzy relation (proposition) defined in U = U1 U2... Um and q is a fuzzy relation (proposition) defined in V = V1 V2... Vn. Further let X and Y be linguistic variables in U and V respectively. The expression IF p THEN q is interpreted as a fuzzy relation Q in U V with the membership function µ Q ( x,y). Since there are a wide variety of fuzzy union, complement and intersection operators, different interpretations of fuzzy rules exist. The various fuzzy IF-THEN rules proposed in the literature include: 11

20 Dienes-Rescher implication { } ( x,y) max ( x), ( y) µ µ QD = 1 p µ (2.1.11) q Lukasiewicz implication { } ( x, y) = min, 1 µ ( x) ( y) µ + QL 1 p µ (2.1.12) q Zadeh implication { [ ], ( x) } ( x,y) max min µ ( x), µ ( y) µ QZ = p q 1 µ p Godel implication (2.1.13) µ QG ( x,y) 1 if = µ q ( y) Mamdani implication. µ p ( x) µ ( y) otherwise q (2.1.14) { } ( x, y) min µ ( x), ( y) µ = (Using min for ) (2.1.15) QMM p µ q ( x,y) µ ( x). ( y) µ QMM = p µ q (Using algebraic product for ) (2.1.16) 2.2 Fuzzy Systems Fuzzy Inference is the process of mapping from a given input to an output using fuzzy logic. The mapping then provides a basis from which decisions can be made or patterns discerned. The process of fuzzy inference involves all of the concepts membership functions, if then rules and fuzzy operators. The essential components of a fuzzy system are the fuzzy inference engine, fuzzy rule base and defuzzifier. The following definitions explain the blocks used in the fuzzy system shown in Figure

21 Fuzzy Rule Base x in U Fuzzifier Defuzzifier y in V fuzzy sets in U Fuzzy Inference Engine fuzzy sets in V Figure 2.2 General model of a Fuzzy system Fuzzifier The fuzzifier is defined as a mapping from a real-valued point * n x U U 2... U n = U R 1 to a fuzzy set A U. The general form of a fuzzifier is a trapezoidal fuzzifier. This means that x is mapped to a fuzzy set A with trapezoidal membership function. The criteria in designing a fuzzifier are: 1. The fuzzy set A should have a large membership value at x. 2. The fuzzifier should simplify the computations involved in the fuzzy inference engine Fuzzy Rule Base A fuzzy rule base is comprised of canonical fuzzy IF-THEN rules of the form where l = 1, 2, IF x1 is A1..., M Ai ( l) X i and ( l) Y x = T (, x,..., ) X x 2 ( l) and... and x is A ( l) THEN y is B( l) B are fuzzy sets n n 1 x n and y Y are input and output linguistic variables. A set of fuzzy rules exhibits the following properties: 13

22 Completeness A set of fuzzy rules is complete if for any x = (, x,..., ) X T x1 2 x n, there exists at least one rule in the fuzzy rule base that fires. Specifically there exists at least one integer in { 1,,..., M} l 2 ( l )( xi ) 0 such that µ A For all i = 1, 2,..., n i Consistency A set of fuzzy IF-THEN rules is consistent if there are no rules in the rule base with same IF parts but different THEN parts. Continuity A set of fuzzy IF-THEN rules is continuous if the fuzzy sets in the THEN parts from neighboring rules have nonempty intersection Fuzzy Inference Engine The fuzzy inference engine is responsible for combining and evaluating the fuzzy IF- THEN rules found in the fuzzy rule base. The IF-THEN rules are formulated by human experts. All other components are of the fuzzy system are used to implement these rules in a reasonable and efficient manner. In the fuzzy inference engine the IF-THEN rules are combined to realize a mapping from fuzzy sets in the input space n U = U1 U 2... U n = U R to fuzzy sets in the output space V R. There is a database associated with the fuzzy inference engine defining the membership functions used in the fuzzy rules. Combining the fuzzy IF-THEN rules can be considered as a mapping from a fuzzy set A U to a fuzzy set B V. In many practical applications the fuzzy rule base comprises of more than one rule. The key question is how to infer with a set of rules. There are two ways to infer with a set of rules: Composition based inference and individual-rule based inference. In composition-based inference, all rules in a fuzzy rule based are combined into a single fuzzy relation inu V. In Individual-rule based inference each rule in the rule base determines an output fuzzy set. The output of the whole fuzzy inference engine is the combination of M individual fuzzy sets by Union or Intersection operations. 14

23 Mamdani Fuzzy model The Mamdani fuzzy inference system employs the individual rule based inference scheme. Figure 2.3 illustrates how a single rule Mamdani fuzzy inference system derives the output y when subjected to a crisp input x. A particular case of figure 2.3 is used to solve the traffic controller problem. A stepwise procedure to implement the single rule model with single antecedent is described in section 2.4. min µ A A µ B B X Y Figure 2.3 Fuzzy reasoning for single rule with single antecedent. Premise 1 (fact): x is A (fuzzy set A X) Premise 2 (rule): IF x is A THEN y is B. (Fuzzy relation A B in X Y) Conclusion: y is B (fuzzy set B Y) The inferred fuzzy set can be expressed as (using fig 2.3) where, B' = A'? { [ ]} ( A B) ( y) = max min ( x), ( x,y) µ B' µ A' µ A B (2.2.1) µ It follows that [ ] ( x,y) = min µ ( x), ( y) A B A µ B µ B' is effectively computed as [ ] ( ) ( y) min { max µ ( x), µ ( x), y } µ B ' = A' A µ B (2.2.2) 15

24 2.2.4 Defuzzifier Defuzzifier is defined as a mapping from fuzzy set B V to a crisp point y * V. Defuzzification refers to the method by which a crisp value is extracted from a fuzzy set as a representative value. Conceptually the task of a defuzzifier is to specify a single point that best represents a fuzzy set. This is similar to the mean value of a random variable. Several defuzzification schemes are available. They are Smallest of Maximum. Largest of Maximum. Centroid of area. Bisector of Area Mean of maximum. 2.3 Fuzzy Traffic Controller In this section, we discuss the fuzzy traffic controller and various steps involved in designing one for a fully featured four-way intersection. It is assumed that the forward-going, right-turn, and left-turn traffic are allowed in any approach Traffic Control Strategy It has been observed that a very effective control strategy stems from the notion of balanced traffic flow. The principle is straightforward as well as sensible: The cars in an approach with heavier traffic flow is given the right of way to cross the intersection for a time interval longer than an approach with lighter traffic flow. When the traffic flow is about equal in two or more approaches, their corresponding time intervals for passing through the intersection should be about equal. In other words, the objective is to make the number of cars waiting in queue at the intersection about the same in the four approaches Basic Structure of Controller As shown in Figure 2.4, the fuzzy traffic controller has four crisp input values: d i, i = 1, 2, 3, 4, representing the northbound, eastbound, southbound, and westbound traffic flow conditions, respectively. The outputs of the maximum operators are time- multiplexed (MUX) before entering the membership function circuit (MFC), which 16

25 generates pertinent fuzzy sets required for the fuzzy reasoning operations in the fuzzy inference engine. The overall consequent fuzzy set resulted from fuzzy inference is then defuzzified to produce the crisp output. d 1 Northbound Southbound max{ d 1, d 3 } Fuzzy Rule Base Memory d 3 d 2 Eastbound Westbound max{ d 2, d 4 } MUX Counter MFC Fuzzy Inference Engine d 4 Defuzzifier Crisp Inputs Fuzzifier Crisp Output Figure 2.4. Basic configuration of the fuzzy logic traffic controller It is important to note that the four key components of the fuzzy traffic controller or an arbitrary fuzzy inference system are: (a) Fuzzifier Since the inputs in most applications are real numbers, the fuzzifier serves as the proper interface between the fuzzy inference engine and the physical world. A fuzzifier may be viewed as a mapping from a point n x R to a fuzzy set A in the universe of discourse U. A very common fuzzifier is a singleton fuzzifier, which maps a crisp input x to a fuzzy singleton in U. Other commonly used fuzzifiers include the Gaussian fuzzifier and the triangular fuzzifier. In the case of the traffic controller, the crisp inputs are the traffic flow conditions in the four approaches. For simplicity, a singleton fuzzifier is assumed in this study. (b) Fuzzy rule base It consists of a set of fuzzy IF-THEN rules, constituting the 17

26 heart of a fuzzy inference system. The fuzzy IF-THEN rules are formulated by human experts. All other components of a fuzzy system are used to implement these rules in a reasonable and efficient manner. In general, the rule base comprises of M canonical fuzzy IF-THEN rules of the form: m Rule m: IF p1 AND K AND p n THEN C, 0 m M The expressions pi, i m = 1, 2, K, n, and C are fuzzy propositions. (c) Fuzzy inference engine In a fuzzy inference engine, fuzzy logic principles are used to combine the fuzzy IF-THEN rules in the fuzzy rule base into a mapping from a fuzzy set A in an n-dimensional universe of discourse X to a fuzzy set C ' in a one-dimensional universe of discourse Y. A number of fuzzy implications have been proposed to represent a fuzzy IF-THEN rule when it is interpreted as a fuzzy relation in the input-output product space X Y. In particular, if the fuzzy rule base consists of only a single rule, then the generalized modus ponens specifies the mapping from fuzzy set A to fuzzy set C '. We the Mamdani inference model in the design of the fuzzy controller. (d) Defuzzifier Defuzzification refers to the process by which a crisp value is extracted from a fuzzy set as a representative value. Mathematically, the defuzzifier is defined as a mapping from a fuzzy set C ' to a crisp point y Y. There are several commonly used defuzzification schemes, such as centroid of area, center average, mean of maximum, largest of maximum, smallest of maximum, and bisector of area. The method of equivalent moment [5] is adopted for this study. Its definition is introduced later Membership Functions To describe the framework based on VHDL descriptions for the design of fuzzy logic controllers, it suffices to consider fuzzy controllers that involve a small number of fuzzy sets with simple membership functions. Specifically, we undertake the design of a fuzzy traffic controller to handle traffic flow characterized by three types of conditions: Light, medium, and high. In a natural manner, the fuzzy sets of traffic flow are labeled as Light, Medium, and Heavy. The selected membership functions for the fuzzy sets, Light, Medium, and Heavy, are shown in Figure 2.5(a). 18

27 Figure 2.5 (a) Membership functions for the fuzzy sets, Light, Medium, and Heavy, which are induced by the traffic-queue deviations. (b) Membership functions for fuzzy sets, Short, Medium, and Long, which label the green phase duration. In a similar fashion, the fuzzy sets Short, Medium, and Long can be viewed as the values associated with the linguistic variable green phase duration. The corresponding membership functions are depicted in Figure 2.5(b). The two identical sets of membership functions are used for the sake of simplicity as well as efficient implementation Fuzzy Rule Base Tabulated in Table 1 is the entire IF-THEN rule base set representing human knowledge. These rules are used for fuzzy reasoning by the fuzzy traffic controller. For example, the fuzzy logic control strategy applied to the traffic flow conditions specified in the shaded column of Table 2.1 has the form: IF (NS-bound traffic is Medium) THEN (NS green phase duration is Medium) IF (EW-bound traffic is Light) THEN (EW green phase duration is Short) 19

28 Table 2.1 Fuzzy IF-THEN rules for traffic control Traffic Flow Condition NS-bound traffic Light Light Light Med Med Med Heavy Heavy Heavy EW-bound traffic Light Med Heavy Light Med Heavy Light Med Heavy NS green phase Short Short Short Med Med Med Long Long Long EW green phase Short Med Long Short Med Long Short Med Long Duration 2.4 Fuzzy Implementation The actual implementation of the fuzzy controller in the simulation is discussed in this section. Here a general procedure is evolved to analytically implement the controller in traffic simulation Fuzzify inputs The first step is to determine the degree to which the inputs are members of the appropriate fuzzy sets. The input value is always crisp and limited to the universe of discourse. The output is a fuzzy degree of membership in the qualifying linguistic set. Fuzzification of the input amounts to a table lookup or function evaluation. In this case we have considered three rules. A fuzzy controller with large number of fuzzy rules increases computation.hence three symmetric membership functions with values Low, Medium and High are used. Each of the rules depends on resolving the inputs into a number of different fuzzy linguistic sets. Before the rules can be evaluated the inputs must be fuzzified according to each of the linguistic sets. Hence a particular difference is resolved into Low, Medium and High with a degree of membership. In this way fuzzification is achieved. The fuzzy rules in this case have one antecedent hence as explained before the inputs directly map to fuzzy values. A general representation of the fuzzy membership functions is illustrated by figure 2.5 in previous section. 20

29 2.4.2 Apply Implication Generally fuzzy rules have unequal weights. In this case since symmetric functions are used to simplify Mamdani method the weights are equal. On applying the implication method a consequent to the rule is obtained. A consequent is a fuzzy set represented by the membership function that weights the linguistic characteristics appropriately. The consequent is reshaped by the function associated with the antecedent, and output is a fuzzy set. Implication is implemented for each rule in the form of an AND operation. In the Mamdani approach, minimum, which truncates the output set, and product, which scales the output set, is used. In this case the minimum function that truncates the output set is used Aggregation Since decisions are based on testing all the rules in the fuzzy system, the rules must be combined to make a decision. Aggregation is the process by which the fuzzy sets that represent the outputs of each rule are combined into a single fuzzy set. The input for aggregation is thus the list of all truncated blocks returned by the implication. It is a process of geometrically combining various pieces. Hence the aggregation method is commutative. The most commonly used form of aggregation is the max scheme. In this case the maximum value of any two overlapping points is taken to represent a single point when subjected to a crisp input. On aggregation a polygon in the form of a modified trapezium is formed. 21

30 µ µ a X Z µ µ b X Z µ µ c X Z µ MAX d Z Figure 2.6 Three-rule Mamdani inference system 22

31 2.4.4 Defuzzification The input for the defuzzification process is a fuzzy set and the output is a single crisp number. The final desired output for each variable is generally a single number. Conceptually defuzzification aims to represent a single number as a representative of a fuzzy set. This task can be accomplished by several methods. A common method is the center of area or centroid. This involves determining the centroid of the fuzzy set. The ordinate or the X co-ordinate value of the centroid represents the crisp value. Consider five points A, B, C, D, and E where 0<A<B<C<D<E<1. A general representation of fuzzy membership functions is illustrated in figure 2.5. The fuzzy membership is in the Y - axis and actual values are in X-axis. The general form of the X co-ordinate value of the centroid is given by Z COA = Z Z µ A µ A ( z) ( z) zdz dz = n k = 1 n k = 1 µ A µ A ( z ) k ( z ) k zk (2.4.1) This method is simple in the case of symmetric fuzzy membership functions as shown above. However since the task requires integration this becomes complex for a series of disparate fuzzy rules. A moments method is proposed as another form of defuzzification. This scheme weights the individual fuzzy sets with the respective areas. The ordinate values of the center of the fuzzy sets are used as the moments. The moments of the membership functions result in a crisp value. The following figures describe the moments method. The general form of the X co-ordinate value of the centroid or the fuzzy lengths are given by Z MA = n i= 1 n i= 1 A i Z Z i i (2.4.2) 23

32 (2.4.6) when applied to the membership functions used in figure 2.4 yield the following results for the ordinate value of the centroid. For clarity these expressions are shown with the corresponding blocks. µ µ h A B C X A B p x C A 1 Z Figure 2.7 Shaded area A 1 and center of area c 1 A 1 = h ( C A) + h 2 ( B C ) 2 (2.4.3) 5p pc 11Ap AC C 1 = where p = h + 6 ( p + C 2A) ( b c) c (2.4.4) µ µ h A 2 B C D x X B C D p p1 2 Z Figure 2.8 Shaded area A 2 and center of area C 2 24

33 2 ( D B) + h ( C B) A2 = h (2.4.5) C 2 b + d = (2.4.6) 2 µ A 3 C x D E C p D E X Z Figure 2.9 Shaded area A 3 and center of area C 3 A 3 ( C D) 2 h = h( E C ) + (2.4.7) 2 5p pc 11Ep EC C 3 = where p = h + 6 ( p + C 2E) ( d c) c (2.4.8) We apply the shaded areas and center of areas obtained in for the inputs lying in the intervals described in figure 2.5. Thus we have the ordinate values of moments Z MA using as follows: x 1 = c 1 if A < x < B (2.4.9) A c + A c x = if B < x < C A + A (2.4.10) 1 2 A2c2 + A3 c3 x 3 = if C < x < D A + A (2.4.11) 2 3 x 4 = c 3 if D < x < E (2.4.12) where x 1, x 2, x 3 and x 4 represent the ordinate values of the moments. 25

34 These X co-ordinate values obtained from the above equations can be scaled to obtain the appropriate light extension values. 2.5 Representation of Fuzzy system with N-membership functions Now that we have seen how fuzzy logic system with three membership functions is represented we can design a system with N-membership functions and derive the formulae for Area and Centroid for various fuzzy sets. A fuzzy system with n-fuzzy sets is shown below in figure Figure 2.10 A fuzzy system with n fuzzy sets In the figure 2.10 above µ stands for degree of membership, fuzzy sets 1 to n represent various membership functions and 0=A1<A2<..An+2=1. For n-fuzzy system indicated above, A1 = 0, A2 = 1/ (n+1), A3 = 2 (1/n+1), A4 = 3(1/n+1) and so on. From this we can infer that An = (n-1) (1/n+1), An+1 = n (1/n+1) & An+2 = (n+1) (1/n+1). Thus in general for an i th fuzzy set, Ai = (i-1) (1/n+1) Defuzzification The moments method is used to obtain crisp output just like in the case of three fuzzy set system. This scheme weights the individual fuzzy sets with the respective areas and the ordinate values of the center of the fuzzy sets are used as the moments. When moments method is applied to n-fuzzy set system then the results obtained are as follows 26

35 µ µ A1 A2 A3 X A1 x h A 1 c 1 A2 p A3 Z Figure 2.11 Shaded area A 1 and center of area C 1 for n-fuzzy set system A 1 = h ( A3 A1 ) h + 2 ( A2 A3) 2 (2.5.1) 5 p p. A3 11A1. p A1. A3 C 1 = where p = h( A2 A3) + A3 (2.5.2) 6 ( p + A3 2. A1 ) All the fuzzy sets from 2 to n-1 are identical, so these fuzzy sets can be represented in general as follows µ µ h C i A i Ai Ai + 1 Ai + 2 x X Ai Ai + 1 Ai + 2 p1 p2 Z Figure 2.12 Shaded area A i and center of area C i for i th -fuzzy set Where i ranges from 2 to n-1 A 2 ( Ai + Ai) + h ( Ai 1 Ai) i = h + 2 (2.5.3) 27

36 Ai + Ai + 2 C i = (2.5.4) 2 µ An x n + 1 A An + 2 n An + 1 An + 2 X A p c n An Z Figure 2.13 Shaded area A n and center of area C n for n th -fuzzy set A n C = h ( An + 2 An) 5p + 7 p. A 6 h A ( An An + 1) 2. p A 2 n n + 2 n + 2 n n = where p = h + + ( p + An 2. An + 2). A ( An 1 An) An (2.5.5) (2.5.6) Thus we have the ordinate values of moments 1 C1 if A1 < x A2 Z MA using as follows x = < (2.5.7) A C + A C i 1 i 1 i i x i = if Ai < x < Ai + 1 (2.5.8) Ai 1 + Ai x (2.5.9) n+ 1 = Cn if An + 1 < x < An + 2 where x 1, x 2, x 3.. x n+1 represent the ordinate values of the moments. 28

37 CHAPTER 3 MATLAB SIMULATION 3.1 Introduction The simulation of the fuzzy logic traffic controller represented in figure 2.4 in previous chapter was first obtained by using Matlab and the matlab output was used to get VHDL simulation. Graphical representation of fuzzy system with three fuzzy sets is initially obtained by using Matlab Fuzzy Logic Toolbox. Then the matlab simulations are obtained for one-input and two-input fuzzy system and these results are compared with the graphs obtained from Fuzzy Logic Toolbox Representation of Fuzzy Logic System using Matlab Fuzzy Logic Toolbox Matlab Fuzzy Logic Toolbox is used to initially obtain the simulation for fuzzy logic traffic controller. The Fuzzy Logic Toolbox supports the design and analysis of fuzzy logic based systems. Specialized GUIs for graphically manipulating systems and interactively viewing and analyzing results. Fuzzy inference is a method that interprets the values in the input vector and, based on user-defined rules, assigns values to the output vector. The Fuzzy Logic Toolbox provides a set of GUI editors that let you build a Fuzzy Inference System (FIS). 29

38 The FIS Editor displays general information about a fuzzy inference system. The Membership Function Editor lets you display and edit the membership functions associated with the input and output variables. The Rule Editor constructs the rule statements The Rule Viewer displays an The Surface Viewer generates a 3-D overview of the fuzzy inference process output depending on the inputs Figure 3.1 Fuzzy Inference System GUIs for Two-Input Fuzzy System 30

39 Graphical User Interfaces The GUIs in the Fuzzy Logic Toolbox let you build two types of system: a Fuzzy Inference System (FIS) and an Adaptive Neuro-Fuzzy Inference System (ANFIS). A separate GUI provides functions for fuzzy clustering. Fuzzy Inference System GUIs Fuzzy inference is a method that interprets the values in the input vector and, based on userdefined rules, assigns values to the output vector. The Fuzzy Logic Toolbox provides a set of GUI editors that let you build a FIS.The editors and viewers shown in figure 3.1 are used to build the rules set, define the membership functions, and analyze the behavior of the FIS.The Rule viewer and the surface viewer shown in figure 3.1 are for 1-input fuzzy system i.e. when we consider traffic flow in only one direction (either North-South or East-West Direction).However when we consider traffic flow in both the directions then a two-input fuzzy system is used. In this case the rule viewer and the surface viewer are as shown in figure 3.2. The FIS Editor Figure 3.2 The FIS Editor 31

40 The FIS Editor displays general information about a fuzzy inference system. The figure 3.2 at the top that shows the names of each input variable and each output variable. The sample membership functions shown in the boxes are just icons and do not represent the shapes of the actual membership functions. Below the diagram is the name of the system and the type of inference used. The default, Mamdani-style inference, is the fuzzy inference system used. Below the name, on the left side of the figure, are the pop-up menus that allow you to modify the various pieces of the inference process. On the right side at the bottom of the figure is the area that displays the names of the input and output variables. Below that are the Help and Close buttons that call up on-line help and dismiss the window, respectively, and finally, at the bottom is a status line that relays information about the system from time to time. The Membership Function Editor Figure 3.3 The Membership Function Editor 32

41 The Membership Function Editor shares some features with the FIS Editor. In fact, all of the five basic GUI tools have similar menu options, status lines, and Help and Close buttons. The Membership Function Editor is the tool that lets you display and edit all of the membership functions for the entire fuzzy inference system, including both input and output variables. The names for the input membership functions are: Light, Medium and Heavy and that for the output membership functions are: Short, Medium and Long. Now that the variables have been named, and the membership functions have appropriate shapes and names, the rules can de discussed. The Rule Editor Figure 3.4 The Rule Editor The Rule Editor contains a large editable text field for displaying and editing rules. It also has landmarks similar to those in the FIS Editor and the Membership Function Editor, including the 33

42 menu bar and the status line. There is a menu below the text area which has input membership functions on the left side of the screen and output membership functions out the right side of the screen. By selecting various combinations of the input and output membership functions different rules are defined which are displayed in the text area. Now the system has been completely defined: we ve got the variables, membership functions, and rules necessary to calculate tips. It would be nice, at this point, to look at a fuzzy inference diagram and verify that everything is behaving the way we think it should. This is exactly the purpose of the Rule Viewer, the next of the GUI tools we ll look at. The Rule Viewer Figure 3.5 The Rule Viewer The Rule Viewer displays a roadmap of the whole fuzzy inference process. It s based on the fuzzy rules described in the previous section. The four plots across the top of the figure represent 34

43 the antecedent and consequent of the first rule. Each rule is a row of plots, and each column is a variable. So the first two columns of plots (the nine yellow plots) show the membership functions referenced by the antecedent, or if-part, of each rule. The next two columns of plots (the nine blue plots) shows the membership functions referenced by the consequent, or then-part of each rule. If you click once on a rule number, the corresponding rule will be displayed at the bottom of the figure. There is a red index line across the input variables plot that you can move left and right by clicking and dragging with the mouse. This changes the input values. When you release the line, a new calculation is performed, and you can see the whole fuzzy inference process take place before your eyes. Lets consider rule 2 where the index line representing NSTraffic crosses the membership function line NSTraffic is Light and the index line representing EWTraffic crosses the membership function line EWTraffic is Heavy in the first two columns will determine the degree to which rule one is activated. A yellow patch of color under the actual membership functions curve is used to make the fuzzy membership value visually apparent. If we follow rule 1 across the top of the diagram, we can see the two consequents NSTraffic is Short and EWTraffic is Long have been truncated depending upon the antecedents this is the implication process in action. Finally the aggregation occurs down the last two columns, and the resultant aggregate plot is shown in the two plots to be found in the lower right corner of the plot field. The defuzzified output values are shown by the thick line passing through the aggregate fuzzy sets. The Rule Viewer is very good, for example, at showing how the shape of certain membership functions is influencing the overall result. The Rule Viewer shows one calculation at a time and in great detail. In this sense, it presents a sort of micro view of the fuzzy inference system. If you want to see the entire output surface of your system, that is the entire span of the output set based on the entire span of the input set, you need to open up the Surface Viewer. 35

44 The Surface Viewer Figure 3.6 The Surface Viewer The Surface Viewer has a special capability that is very helpful in cases with two (or more) inputs and one output: you can actually grab the axes and reposition them to get a different threedimensional view on the data. The Reference Input field is used in situations when there are more inputs required by the system than are currently being varied. The Surface Viewer can generate a three-dimensional output surface where two of the inputs vary. The Surface Viewer is equipped with pop-up menus that let you select any two inputs and any one output for plotting. Just below the pop-up menus are two text input fields that let you determine how many X-axis and Y-axis grid lines you want to include. This allows you to keep the calculation time reasonable for complex problems. 36

45 3.2 Matlab simulation for one-input fuzzy system Initially a one- input fuzzy system is considered where the input is traffic flow in either North- South direction or East-West direction. In this project a fuzzy system with three fuzzy sets is considered and a plot of Traffic Flow vs Green Phase Duration is obtained as shown in figure 3.3 below Figure 3.7 Input-Output Characteristics of Fuzzy Traffic Controller with Three Input Fuzzy Sets As seen from the graph the green phase duration is constant initially and then gradually increases with increase in the traffic flow until it becomes constant again. This shows that the green phase duration is constant when the traffic flow is very low or very high. Similarly we can obtain this graph for fuzzy system with different number of fuzzy sets. Various graphs obtained are as shown in figure 3.4 below 37

46 Figure 3.8 Input-Output Characteristics of Fuzzy Traffic Controller using Ni Input Fuzzy Sets 38

47 From the figure 3.4 it can be concluded that as the number of fuzzy sets increase, the initial value of green phase duration (i.e. when Traffic Flow = 0) decreases and the maximum range of green phase duration (i.e. the green phase duration between Traffic Flow = 0 & Traffic Flow = 1) increases. Also the initial and final range of traffic flow when the green phase duration is constant decreases with the increase in number of fuzzy sets. Thus we can conclude that as the number of fuzzy sets increase the precision of the system increases. 3.3 Matlab simulation for two-input fuzzy system Now that we have seen how one-input fuzzy system works lets consider a two-input fuzzy system. In this case one of the inputs is traffic flow in the North-South direction while the other input is traffic flow in the East-West direction. Again in this project a fuzzy system with three fuzzy sets is considered and a plot of Traffic Flow vs. Green Phase Duration is obtained as shown in figure 3.5. The characteristic of this plot is similar to that of one-input fuzzy system such that the green phase duration is constant initially and then gradually increases with increase in the traffic flow until it becomes constant again. 39

48 Figure 3.9 Surface Plot for Fuzzy Traffic Controller using Three Input Fuzzy Sets 40

49 Figure 3.10 Surface Plot for Fuzzy Traffic Controller using Ni Input Fuzzy Sets 41

50 3.4 Generating Contents of ROM using Matlab Matlab program is used to implement the fuzzification, mamdani inference engine and defuzzification for two input fuzzy system with three fuzzy sets. Mamdani inference engine makes use of the three fuzzy rules which are defined by matlab. The output of the Matlab program is the green phase duration for traffic signals as given by figure 3.5. These output values are then stored in a ROM in the form of Memory Initialization File (mif), which can be accessed by Hardware Description Language (i.e. VHDL). 42

51 CHAPTER 4 HARDWARE IMPLEMENTATION 4.1 VHDL Implementation As discussed in later part of chapter 3 Matlab program is used to implement two input fuzzy system with three fuzzy sets. The output of the Matlab program is then stored in a ROM in the form of Memory Initialization File (mif), which can be accessed by Hardware Description Language (i.e. VHDL).In this case ROM is nothing but a truth table where the two inputs to the VHDL program act as inputs of the truth table. Depending on these inputs one of the address values of the ROM is selected and the data stored at this address is given at the output port of VHDL code. This data is nothing but the green phase duration for traffic signals. 4.2 FPGA Implementation Once VHDL code is obtained then the next step is to create and design digital logic design for the system. For this purpose the University Program Design Laboratory Package is used which consists of state-of-the-art development tools and programmable logic devices (PLD).This package includes following features: MAX+PLUS II version 7.21 student edition development software. UP 1 Education Board o EPM7128S device in an 84-pin plastic J-lead chip carrier (PLCC) package. o EPF10K20 device in a 240-pin power quad flat pack package. ByteBlaster Parallel Port Download Cable. MAX+PLUS II Version 7.21 Student Edition Software The MAX+PLUS II version 7.21 Student Edition Software contains many of the features available in the commercial version of MAX+PLUS II, including a completely integrated design 43

52 flow and intuitive graphical user interface. This software supports schematic capture and textbased hardware description language design entry, including the Altera Hardware Description Language (AHDL) and VHDL. It also provides design programming, compilation, and verification support for the EPM7128S and EPF10K20 devices. UP1 Education Board The UP1 Education Board is a stand-alone experiment board based on two of Altera s leading device families: MAX 7000 and FLEX 10K. Its simple design, when used with MAX+PLUS II software, provides a superior platform for learning digital logic design using high-level development tools and PLDs.The UP1 Board is shown in figure 4.1. The UP1 Education Board was designed to meet the needs of the educator and the design laboratory environment. The UP1 Education Board supports both product-terms based and lookup table based (LUT)-based architectures and includes two PLDs. The EPM7128S device can be programmed in-system with the ByteBlaster download cable. The EPF10K20 device can be configured in-system with either the ByteBlaster download cable or an EPC1 Configuration EPROM. EPM7128S Device The EPM7128S device, a mid-density member of the high-density, high-performance MAX7000S family, is based on EEPROM elements. The EPM7128S device comes in a socketmounted 84-pin PLCC package and has 128 macrocells. Each macrocell has a programmable- AND/fixed-OR array as well as configurable register with independently programmable clock, clock enable, clear, and preset functions. With a capacity of 2,500 gates and a simple architecture, the EPM7128S device is ideal for introductory designs as well as larger combinatorial and sequential logic functions. EPF10K20 Device The EPF10K20 device, a member of Altera s high-density FLEX10K family, is based on reconfigurable SRAM elements. The EPF10K20 device comes in a 240-pin RQFP package and has 1,152 logic elements (LEs) and 6 embedded array blocks (EABs).Each LE consists of a 4- input look-up table (LUT), a programmable flipflop, and dedicated signal paths for carry and cascade functions. Each EAB provides 2,048 bits of memory, which can be used to create RAM, ROM, or first-in first-out (FIFO) functions. The EABs can also be used to implement logic functions, such as multipliers, microcontrollers, state machines, and digital signal processing 44

53 (DSP) functions. With a typical gate count of 20,000 gates, the EPF10K20 device is ideal for advanced designs, including computer architecture, communications, and DSP applications. ByteBlaster Parallel Port Download Cable Designs can be easily and quickly downloaded into the UP1 Education Board using the ByteBlaster download cable, which is hardware interface to a standard parallel port. This cable channels programming or configuration data between the MAX+PLUSII software and the UP1 Education Board. Because design changes are downloaded directly to the devices on the board, prototyping is easy and multiple design iterations can be accomplished in quick succession. Figure 4.1 UP1 Education Board Block Diagram DC_IN & RAW Power Input The DC_IN power input accepts a 2.5mm x 5.55 mm female connector. The acceptable DC input is 7 to 12V DC at a minimum of 250 ma. The RAW power input consists of two holes for 45

54 connecting an unregulated power source. The hole marked with a plus sign (+) is the positive input; the hole marked with a minus sign (-) is board common. On-Board Voltage Regulator The on-board voltage regulator, an LM340T, regulates the DC positive input at 5V. The DC input consists of two holes for connecting a 5-V DC regulated power source. The hole marked with a plus sign (+) is the positive input; the hole marked with a minus sign (-) is board common. A green light- emitting diode (LED) labeled POWER is illuminated when current is flowing from the 5-V DC regulated power source. JTAG_IN Header The 10-pin female plug on the ByteBlaster download cable connects with the JTAG_IN 10- pin male header on the UP1 Education Board. The UP1 Education Board provides power and ground to the ByteBlaster download cable. Data is shifted into the devices via the TDI pin and shifted out of the devices via the TDO pin. Table below identifies the JTAG_IN pin names when the ByteBlaster is operating in JTAG mode. Table 4.1 JTAG_IN 10-Pin Header Pin-Outs Pin JTAG Signal 1 TCK 2 GND 3 TD0 4 VCC 5 TMS 6 No Connect 7 No Connect 8 No Connect 9 TDI 10 GND Jumpers The UP1 Education Board contains four three-pin jumpers (TDI, TDO, DEVICE, and BOARD) that set the JTAG configuration. JTAG chain can be used to configure individual devices EPM7128S and EPF10K20 as well as to configure/program both devices. Figure

55 below shows the positions of the three connectors (C1, C2 and C3) on each of the four jumpers and Table 4.2 defines the settings for each configuration. Figure 4.2 Position of C1, C2 & C3 Connectors Table 4.2 JTAG Jumper Settings MAX_SW1 & MAX_SW2 Switches MAX_SW1 and MAX_SW2 each contain eight switches that provide logic-level signals. These switches are pulled-up through 10-K. resistors. Connections to these signals are made by inserting one end of the hook-up wire into the female header aligned with the appropriate switch. Insert the other end of the hook-up wire into the appropriate female header assigned to the I/O pin of the EPM7128S device. The switch output is set to logic 1 when the switch is open and set to logic 0 when the switch is closed. 47

56 D1 through D16 LEDs The UP Education Board contains 16 LEDs that are pulled-up with a resistor. An LED is illuminated when a logic 0 is applied to the female header associated with the LED. LEDs D1 through D8 are connected in the same sequence to the female headers (i.e., D1 is connected to position 1, and D2 is connected to position 2, etc.). LEDs D9 through D16 are connected in the same sequence to the female headers (i.e., D9 is connected to position 1, and D10 is connected to Figure 4.3 LED Positions EPF10K20 Device The UP1 Education Board provides the following resources for the EPF10K20 device. The pins from the EPF10K20 device are pre-assigned to switches and LEDs on the board. JTAG chain connection for the ByteBlaster Socket for an EPC1 Configuration EPROM 2 momentary push-button switches. 1 octal dipswitch Dual-digit 7-segment display On-board oscillator ( MHz) Mouse port 3 expansion ports, each with 42 I/O pins and 7 global pins. 48

57 EPF10K20 Configuration This section describes the procedures for configuring the EPF10K20 device (i.e., how to set the on-board jumpers, connect the ByteBlaster II download cable, and set options in the MAX+PLUS II software). Setting the On-Board Jumpers for EPF10K20 Configuration To configure the EPF10K70 device in a JTAG chain, set the jumpers TDI, TDO, DEVICE, and BOARD as shown in Figure 4.3 Figure 4.4 Jumper Settings for Configuring Only the FLEX 10K Device Setting the JTAG Options in the MAX+PLUS II Software for EPF10K20 Configuration The following steps describe how to use the MAX+PLUS II software to configure the EPF10K20 device in a JTAG: 1. Turn on the Multi-Device JTAG Chain command (JTAG menu) in the MAX+PLUS II Programmer to configure the EPF10K20 device. Follow this step even if there is only one programming device. 2. Choose Multi-Device JTAG Chain Setup (JTAG menu). 3. Select EPF10K20 in the Device Name list in the Multi-Device JTAG Chain Setup dialog box. 4. Type the name of the programming file for the EPF10K20 device in the Programming File Name box. You can also use the Select Programming File button to browse your computer s directory structure to locate the appropriate programming file. 49

58 5. Click Add to add the device and associated programming file to the Device Names & Programming File Names box. The number to the left of the device name shows the order of the device in the JTAG chain. The device s associated programming file is displayed on the same line as the device name. If no programming file is associated with a device, <none> is displayed next to the device name. 6. Click Detect JTAG Chain Info to have the ByteBlaster II cable check the device count, JTAG ID code, and total instruction length of the JTAG chain. A message just above the Detect JTAG Chain Info button reports the information detected by the ByteBlaster II cable. Manually verify that this message matches the information in the Device Names & Programming File Names box. 7. Click Save JCF to save the current settings to a JCF for future use. Type the name of the file in the File Name box and then select the desired directory in the Directories box in the Save JCF dialog box. Click OK. 8. Click OK to save changes. 9. Click Configure in the MAX+PLUS II Programmer. 4.3 VHDL Simulation Waveforms Before hardware implementation is carried out we should have VHDL simulation waveforms to verify that we are getting desired output for the given inputs. The MATLAB simulations that are obtained in chapter 3 give us the output values i.e the green phase duration of the traffic signals. The LPM_ROM in VHDL code is initialized by using these output values. As seen in figure 4.5 below the two 8-bit inputs i and j are used to select the address of the ROM and the corresponding data in the ROM is obtained as the 16-bit output Q. 50

59 Figure 4.5 VHDL simulation waveform 4.4 Circuit Implementation using UP 1 Education Board Now that we have studied about UP1 Education Board the fuzzy traffic controller circuit can be implemented using this board. Once the FPGA chip EPF10K20 is programmed using MAX+PLUS II then the two inputs to the chip are given by using MAX_SW1 & MAX_SW2.Depending upon the inputs the output is obtained and it can be observed on the LEDs on the board. When LED is illuminated it means logic 0 is applied to that LED. The UP1 Education Board with wired input connections is shown in figure

60 Figure 4.6 Circuit Implementation using UP1 Education Board 4.5 Printed Circuit Board design of the system Once the circuit is implemented using UP1 board the next step is to create a prototype for the circuit by using PCB design. So once we have the PCB for the circuit then we can give the input signal from the field to this board and get the desired output. PCB design is carried out by using PROTEL Design Explorer version software. Protel DXP provides a versatile and fully integrated design capture system for both PCB and FPGA applications. Design can be captured using schematic or any mixture of schematic and VHDL for an FPGA design. Protel's schematic environment supports designs targeted at PCB or FPGA implementation. Extensive project navigation features and error checking allow you to design in a logical way, with support for partitioning your design from the top down or bottom up. There is no limit to the number of sheets or hierarchy depth, enabling you to capture designs of any complexity. 52

61 With Protel 2004 you only need to draw a channel schematic once. Protel gives you access to a full set of features for managing multi-channel instantiation. Protel 2004 maintains the channel information in the schematic without the need to flatten the hierarchy, allowing you to update the design or number of channels at any time. Multi-channel design structure is maintained through to PCB layout, allowing you to step and repeat the routed channel layout on the PCB. Protel also supports extensive bus-level connectivity between both components and sheets, ensuring that wiring up even complex designs is fast and efficient. LiveDesign interactive development of FPGA-based designs Protel is the first board-level design system to recognize the growing importance of programmable devices in today s electronic systems. It comes with libraries of FPGA-based components that can be wired together at the schematic level to create an FPGA design without the need for HDLs. The FPGA-based components are pre-synthesized and pre-verified for a range of target devices, allowing easy changing of the target device. Protel also support VHDLbased development for the creation of custom FPGA components or logic blocks for integration with the schematic design. To facilitate the design of FPGAs, Protel 2004 works with Altium s unique NanoBoard a LiveDesign-enabled development board that allows you to interactively implement and debug your FPGA design. A combination of virtual instruments and boundary scan technology enables you to interact with your design running on the NanoBoard and 'see' the signals inside the FPGA. When you change your circuit, re-download the design to the NanoBoard for further debugging. Altium calls this process of real-time interaction with your design during development LiveDesign. LiveDesign allows you to rapidly develop FPGA-based applications without the need for HDL-based simulation. Automatic pin synchronization between PCB and FPGA projects The tedious and error-prone task of synchronizing FPGA pin assignments between the PCB and FPGA projects is handled automatically by the system, and a range of FPGA pin swapping features allow you automatically optimize FPGA-based board designs for routing. 53

62 Rules-driven board layout and editing With Protel s rules-driven PCB layout and editing environment, you have full control over the board design process. Define your board using design rules from 49 separate rule classes, covering 10 categories including routing, high speed and manufacturing. Protel uses queries to determine which rules are applied to which objects, giving you precise control over the target of rules. An because rules are hierarchical, you can control the order in which rules are applied. During routing, Protel can enforce rules such as track width and clearances as you work, ensuring that your design is created free from violations. Comprehensive set of integrated libraries Protel 2004 comes with a comprehensive set of integrated component libraries that contain over 68,000 components. Integrated libraries allow schematic symbols to be combined with their related models such as PCB footprints, SPICE and signal integrity models. Specific components can be easily located with Protel's cross-library search facility. Previous Protel schematic and PCB library formats are supported, ensuring easy porting of your custom libraries to the Protel 2004 environment. Situs Topological Autorouting With the inclusion of Altium s new Situs Topological Autorouting System, Protel gives you the power to cope with high-density component packaging and tightly-packed board designs. Unlike traditional shape-based routers, Protel s topological autorouter has the ability to natively find routing paths in non-orthogonal directions, allowing the intelligent assignment of connections to layers. Topological path mapping also allows Protel to efficiently route boards and components of any geometry, without the need for extensive post-route cleanup work. In Protel 2004, Situs has been enhanced to give superior completion rates, better support for plane layers and split planes, and support for neck down on pad entries Schematic Document for the Circuit Protel DXP provides a versatile and fully integrated design capture system for both PCB and FPGA applications. Designs can be captured using schematic, or any mixture of schematic and VHDL for an FPGA design. The schematic editor supports both top-down and bottom-up design, using a block diagram metaphor to provide an intuitive link between the sheets in the project 54

63 hierarchy each block representing an individual schematic sheet. Wiring these blocks together creates connectivity- connectivity that can be verified and navigated as soon as the design is compiled. Figure 4.7 Schematic Document for the circuit As seen from the schematic in figure 4.6 the circuit mainly consists of integrated chips, two Analog-to-Digital converters, one Field Programmable Gate Array (FPGA) and one Digital-to- Analog converter. Apart from the circuit has 10-pin header to connect the byte-blaster cable that is used to program the FPGA chip. The circuit also has three 2-pin connectors, two of which are used for two inputs and the other one is used for the output. Analog-To-Digital Converter Analog-to-digital converter is used to convert the analog input from the field into digital signal that can be used by FPGA device. In this project I have used 8-bit ADC 0803 as analogto-digital converter. 55

64 The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-State output data lines can be connected directly to the data bus. The differential analog voltage input allows for increased common-mode rejection and provides a means to adjust the zero-scale offset. Additionally, the voltage reference input provides a means of encoding small analog voltages to the full 8 bits of resolution. Figure 4.8 ADC 0803 FEATURES OF ADC 0803 Compatible with most microprocessors Differential inputs 3-State outputs Logic levels TTL and MOS compatible Can be used with internal or external clock Analog input range 0 V to VCC Single 5 V supply Guaranteed specification with 1 MHz clock 56

65 SYMBOL PARAMETER CONDITIONS RATING UNIT V cc Supply Voltage 6.5 V Logic control input voltages -0.3 to +16 V T amb All other input voltages -0.3 to (Vcc + 0.3) Operating temperature range ADC0803LCD/ADC0804LCD -40 to +85 ADC0803LCN/ADC0804LCN -40 to +85 ADC0803CD/ADC0804CD 0 to +70 ADC0803CN/ADC0804CN 0 to +70 T stg Storage temperature -65 to +150 C T sld Leading soldering temperature( 10 seconds) 230 C P D Maximum power dissipation T amb =25 C(still N package D package air) mw mw Figure 4.9 Absolute Maximum Ratings V C C C C Digital-To-Analog Converter Digital-to-Analog converter is used to convert the digital output of FPGA chip into an analog signal that can be used by the traffic control devices in the field. In this project I have used 16-bit DAC 712 as digital-to-analog converter. DAC712 is a complete 16-bit resolution D/A converter with 16 bits of monotonicity over temperature.dac712 has a precision +10V temperature compensated voltage reference, ±10V output amplifier and 16-bit port bus interface. The digital interface is fast, 60ns minimum write pulse width, is double-buffered and has a CLEAR function that resets the analog output to bipolar zero. GAIN and OFFSET adjustment inputs are arranged so that they can be easily trimmed by external D/A converters as well as by potentiometers. DAC712 is available in two linearity error performance grades: ±4LSB and ±2LSB and three differential linearity grades: ±4LSB, ±2LSB, and ±1LSB. The DAC712 is specified at power supply voltages of ±12V and ±15V. DAC712 is packaged in a 28-pin 0.3" wide plastic DIP and in a 28-lead wide-body plastic SOIC. The DAC712P, U, PB, UB, are specified over the 40 C to +85 C temperature range and the DAC712PK, UK,PL, UL are specified over the 0 C to +70 C range. 57

66 Figure 4.10 Pin Diagram for DAC712 FEATURES OF DAC 712 High-speed 16-bit parallel double buffered interface Voltage output: ±10v 13-, 14-, and 15-bit linearity grades 16-bit monotonic over temperature (L grade) Power dissipation: 600mw max Gain and offset adjust: convenient for auto-cal D/A converters 28-lead DIP and SOIC packages 58

67 +V CC to COMMON...0V, +17V -V CC to COMMON...0V, -17V +V CC to V CC... 34V Digital Inputs to COMMON -1V to + V CC -0.7V External Voltage Applied to BPO and Range Resistors...± V CC V REF OUT...Indefinite Short to COMMON V OUT...Indefinite Short to COMMON Power Dissipation..750mW Storage Temperature C to +150 C Lead Temperature (soldering. 10s) +300 C Figure 4.11 Absolute Maximum Ratings FLEX 10K Device The Altera FLEX 10K embedded programmable logic family delivers the flexibility of traditional programmable logic together with the efficiency and density of embedded gate arrays. With its two unique logic implementation structures the embedded array and the logic array the FLEX 10K family revolutionized programmable architectures and brought programmable logic into the mainstream gate-array market. The FLEX 10K family ranges from 10,000 to 250,000 typical gates and spans three process generations. Each succeeding generation provides higher performance, lower cost, and lower power consumption than the previous one. The 2.5-V, 0.22-micron FLEX 10KE devices average 20% to 30% faster than the equivalent 0.30-micron FLEX 10KA devices, which operate at 3.3 V. Similarly, FLEX 10KA devices are an average of 20% to 30% faster than the 0.42-micron FLEX 10K devices, which operate at 5.0 V. The FLEX 10K family provides a range of devices to suit today's varying design needs. Feature Table 4.3 FLEX 10K Device Overview EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K50E EPF10K50S Typical gates (logic 10,000 20,000 30,000 40,000 50,000 and RAM) Logic Elements (LEs) 576 1,152 1,178 2,304 2,880 Logic array blocks (LABs) Embedded array blocks (EABs) Total RAM bits 6,144 12,288 12,288 24,576 16,384 20,480 40,960 59

68 FLEX 10 K Device that is used in this project is EPF10K20RC240-4 and the pin diagram for this device is given in figure 4.11 Figure 4.12 Pin Diagram of EPF10K20RC240-4 Table 4.4 below gives input-output pin configuration for FPGA device EPF10K20RC

69 Table 4.4 Pin Configuration for EPF10K20RC240-4 Pin Node Name Pin Node Name 45 j0 231 Q0 46 j1 230 Q1 48 j2 229 Q2 49 j3 228 Q3 50 j4 227 Q4 51 j5 226 Q5 53 j6 225 Q6 54 j7 223 Q7 55 i0 222 Q8 56 i1 221 Q9 61 i2 220 Q10 62 i3 219 Q11 63 i4 218 Q12 64 i5 217 Q13 65 i6 215 Q14 66 i7 214 Q15 91 clk Printed Circuit Board design for the schematic Once schematic document of the circuit is obtained in PROTEL next step is to compile the document and verify that there are no errors in the connections. If the document compiles without any errors then it has to be updated to PCB level. After updating to PCB level and routing all the connections the final PCB design looks like in figure

70 Figure 4.13 Printed Circuit Board for the circuit 62