Timed Automata From Theory to Implementation
|
|
- Arabella Bryant
- 5 years ago
- Views:
Transcription
1 Timed Automata From Theory to Implementation Patricia Bouyer LSV CNRS & ENS de Cachan France Chennai january 2003 Timed Automata From Theory to Implementation p.1
2 Roadmap Timed automata, decidability issues Some extensions of the model Implementation of timed automata Chennai january 2003 Timed Automata From Theory to Implementation p.2
3 Timed automata, decidability issues presentation of the model decidability of the model the region automaton construction Chennai january 2003 Timed Automata From Theory to Implementation p.3
4 Timed automata x, y: clocks [Alur & Dill s] guard action reset p y < 4, a, x := 0 x = 5, b q c, y := 0 Chennai january 2003 Timed Automata From Theory to Implementation p.4
5 Timed automata x, y: clocks [Alur & Dill s] guard action reset p y < 4, a, x := 0 x = 5, b q c, y := 0 a c b p q q p value of x value of y timed word (a, 3.2)(c, 5.1)(b, 8.2)... Chennai january 2003 Timed Automata From Theory to Implementation p.4
6 Emptiness checking Emptiness problem: is the language accepted by a timed automaton empty? reachability properties basic liveness properties (final states) (Büchi (or other) conditions) Chennai january 2003 Timed Automata From Theory to Implementation p.5
7 Emptiness checking Emptiness problem: is the language accepted by a timed automaton empty? reachability properties basic liveness properties (final states) (Büchi (or other) conditions) Theorem: The emptiness problem for timed automata is decidable. It is PSPACE-complete. [Alur & Dill 1990 s] Chennai january 2003 Timed Automata From Theory to Implementation p.5
8 The region abstraction y 2 Equivalence of finite index x Chennai january 2003 Timed Automata From Theory to Implementation p.6
9 The region abstraction y 2 Equivalence of finite index x compatibility between regions and constraints Chennai january 2003 Timed Automata From Theory to Implementation p.6
10 The region abstraction y 2 Equivalence of finite index x compatibility between regions and constraints compatibility between regions and time elapsing Chennai january 2003 Timed Automata From Theory to Implementation p.6
11 The region abstraction y 2 Equivalence of finite index x compatibility between regions and constraints compatibility between regions and time elapsing Chennai january 2003 Timed Automata From Theory to Implementation p.6
12 The region abstraction y 2 Equivalence of finite index x compatibility between regions and constraints compatibility between regions and time elapsing a bisimulation property Chennai january 2003 Timed Automata From Theory to Implementation p.6
13 The region abstraction y 2 1 Equivalence of finite index region defined by I x =]1; 2[, I y =]0; 1[ {x} < {y} x compatibility between regions and constraints compatibility between regions and time elapsing a bisimulation property Chennai january 2003 Timed Automata From Theory to Implementation p.6
14 The region automaton timed automaton region partition q g,a,c:=0 q is transformed into: (q, R) a (q, R ) if there exists R Succ t (R) s.t. R g [C 0]R R L(reg. aut.) = UNTIME(L(timed aut.)) where UNTIME((a 1, t 1 )(a 2, t 2 )... ) = a 1 a 2... Chennai january 2003 Timed Automata From Theory to Implementation p.7
15 An example [AD 90 s] y x Chennai january 2003 Timed Automata From Theory to Implementation p.8
16 Partial conclusion a timed model interesting for verification purposes Numerous works have been (and are) devoted to: the theoretical comprehension of timed automata extensions of the model (to ease the modelling) expressiveness analyzability algorithmic problems and implementation Chennai january 2003 Timed Automata From Theory to Implementation p.9
17 Some extensions of the model adding constraints of the form x y c adding silent actions adding constraints of the form x + y c adding new operations on clocks Chennai january 2003 Timed Automata From Theory to Implementation p.10
18 Adding diagonal constraints x y c and x c Decidability: yes, using the region abstraction y x Expressiveness: no additional expressive power Chennai january 2003 Timed Automata From Theory to Implementation p.11
19 Adding diagonal constraints (cont.) c is positive copy where x y c x := 0 y := 0 x c x := 0 x y c y := 0 x := 0 x > c y := 0 y := 0 proof in [Bérard,Diekert,Gastin,Petit 1998] copy where x y > c Chennai january 2003 Timed Automata From Theory to Implementation p.12
20 Adding diagonal constraints (cont.) Open question: is this construction optimal? In the sense that timed automata with diagonal constraints are explonentially more concise than diagonal-free timed automata. Chennai january 2003 Timed Automata From Theory to Implementation p.12
21 Adding silent actions g, ε, C := 0 [Bérard,Diekert,Gastin,Petit 1998] Decidability: yes (actions has no influence on the previous construction) Expressiveness: strictly more expressive! x = 1 a x := x 1 0 < x < 1, b x = 1, ε, x := 0 a a b b a Chennai january 2003 Timed Automata From Theory to Implementation p.13
22 Adding constraints of the form x + y c x + y c and x c [Bérard,Dufourd 2000] Decidability: - for two clocks, decidable using the abstraction y x - for four clocks (or more), undecidable! Expressiveness: more expressive! (even using two clocks) x + y = 1, a, x := 0 {(a n, t 1... t n ) n 1 and t i = i } Chennai january 2003 Timed Automata From Theory to Implementation p.14
23 The two-counter machine Definition. A two-counter machine is a finite set of instructions over two counters (x and y): Incrementation: (p): x := x + 1; goto (q) Decrementation: (p): if x > 0 then x := x 1; goto (q) else goto (r) Theorem. [Minsky 67] The emptiness problem for two counter machines is undecidable. Chennai january 2003 Timed Automata From Theory to Implementation p.15
24 Undecidability proof c is unchanged c is incremented c c c c c c c c cc d d dd d d d d d d time d is decremented simulation of decrement of d increment of c We will use 4 clocks: u, tic clock (each time unit) x 0, x 1, x 2 : reference clocks for the two counters x i reference for c the last time x i has been reset is the last time action c has been performed [Bérard,Dufourd 2000] Chennai january 2003 Timed Automata From Theory to Implementation p.16
25 Undecidability proof (cont.) Increment of counter c: x 0 2, u + x 2 = 1, c, x 2 := 0 x 2 := 0 u = 1,, u := 0 x 0 > 2, c, x 2 := 0 u + x 2 = 1 ref for c is x 0 ref for c is x 2 Decrement of counter c: x 0 < 2, u + x 2 = 1, c, x 2 := 0 x 2 := 0 u = 1,, u := 0 x 0 = 2, c, x 2 := 0 u + x 2 = 1 u = 1, x 0 = 2,, u := 0, x 2 := 0 Chennai january 2003 Timed Automata From Theory to Implementation p.17
26 Adding constraints of the form x + y c Two clocks: decidable! using the abstraction y x Four clocks (or more): undecidable! Chennai january 2003 Timed Automata From Theory to Implementation p.18
27 Adding constraints of the form x + y c Two clocks: decidable! using the abstraction y 2 1 Three clocks: open question x Four clocks (or more): undecidable! Chennai january 2003 Timed Automata From Theory to Implementation p.18
28 Adding new operations on clocks Several types of updates: x := y + c, x :< c, x :> c, etc... Chennai january 2003 Timed Automata From Theory to Implementation p.19
29 Adding new operations on clocks Several types of updates: x := y + c, x :< c, x :> c, etc... The general model is undecidable. (simulation of a two-counter machine) Chennai january 2003 Timed Automata From Theory to Implementation p.19
30 Adding new operations on clocks Several types of updates: x := y + c, x :< c, x :> c, etc... The general model is undecidable. (simulation of a two-counter machine) Only decrementation also leads to undecidability Incrementation of counter x z = 0 z = 1, z := 0 z = 0, y := y 1 Decrementation of counter x z = 0 x 1 z = 0, x := x 1 x = 0 Chennai january 2003 Timed Automata From Theory to Implementation p.19
31 Decidability y := 0 y := 1 x y < image by y := 1 the bisimulation property is not met The classical region automaton construction is not correct. Chennai january 2003 Timed Automata From Theory to Implementation p.20
32 Decidability (cont.) A Diophantine linear inequations system is there a solution? if yes, belongs to a decidable class Examples: constraint x c constraint x y c c max x c max x,y update x : y + c max x max y +c and for each clock z, max x,z max y,z + c, max z,x max z,y c update x :< c c max x and for each clock z, max z c + max z,x The constants (max x ) and (max x,y ) define a set of regions. Chennai january 2003 Timed Automata From Theory to Implementation p.21
33 Decidability (cont.) y := 0 y := 1 x y < 1 max y 0 max x 0 + max x,y max y 1 max x 1 + max x,y max x,y 1 = max x = 2 max y = 1 max x,y = 1 max y,x = 1 y 1 The bisimulation property is met x Chennai january 2003 Timed Automata From Theory to Implementation p.22
34 What s wrong when undecidable? Decrementation x := x 1 max x max x 1 Chennai january 2003 Timed Automata From Theory to Implementation p.23
35 What s wrong when undecidable? Decrementation x := x 1 max x max x 1 Chennai january 2003 Timed Automata From Theory to Implementation p.23
36 What s wrong when undecidable? Decrementation x := x 1 max x max x 1 Chennai january 2003 Timed Automata From Theory to Implementation p.23
37 What s wrong when undecidable? Decrementation x := x 1 max x max x 1 Chennai january 2003 Timed Automata From Theory to Implementation p.23
38 What s wrong when undecidable? Decrementation x := x 1 max x max x 1 Chennai january 2003 Timed Automata From Theory to Implementation p.23
39 What s wrong when undecidable? Decrementation x := x 1 max x max x 1 Chennai january 2003 Timed Automata From Theory to Implementation p.23
40 What s wrong when undecidable? Decrementation x := x 1 max x max x 1 etc... Chennai january 2003 Timed Automata From Theory to Implementation p.23
41 Decidability (cont.) x := c, x := y x := x + 1 x := y + c x := x 1 x :< c x :> c x : y + c y + c <: x :< y + d y + c <: x :< z + d Diagonal-free constraints PSPACE-complete Undecidable PSPACE-complete Undecidable General constraints PSPACE-complete Undecidable PSPACE-complete Undecidable [Bouyer,Dufourd,Fleury,Petit 2000] Chennai january 2003 Timed Automata From Theory to Implementation p.24
42 Implementation of Timed Automata analysis algorithms the DBM data structure a bug in the forward analysis Chennai january 2003 Timed Automata From Theory to Implementation p.25
43 Notice The region automaton is not used for implementation: suffers from a combinatorics explosion (the number of regions is exponential in the number of clocks) no really adapted data structure Chennai january 2003 Timed Automata From Theory to Implementation p.26
44 Notice The region automaton is not used for implementation: suffers from a combinatorics explosion (the number of regions is exponential in the number of clocks) no really adapted data structure Algorithms for minimizing the region automaton have been proposed... [Alur & Co 1992] [Tripakis,Yovine 2001] Chennai january 2003 Timed Automata From Theory to Implementation p.26
45 Notice The region automaton is not used for implementation: suffers from a combinatorics explosion (the number of regions is exponential in the number of clocks) no really adapted data structure Algorithms for minimizing the region automaton have been proposed... [Alur & Co 1992] [Tripakis,Yovine 2001]...but on-the-fly technics are preferred. Chennai january 2003 Timed Automata From Theory to Implementation p.26
46 Reachability analysis forward analysis algorithm: compute the successors of initial configurations I F Chennai january 2003 Timed Automata From Theory to Implementation p.27
47 Reachability analysis forward analysis algorithm: compute the successors of initial configurations I F Chennai january 2003 Timed Automata From Theory to Implementation p.27
48 Reachability analysis forward analysis algorithm: compute the successors of initial configurations I F backward analysis algorithm: compute the predecessors of final configurations I F Chennai january 2003 Timed Automata From Theory to Implementation p.27
49 Reachability analysis forward analysis algorithm: compute the successors of initial configurations I F backward analysis algorithm: compute the predecessors of final configurations I F Chennai january 2003 Timed Automata From Theory to Implementation p.27
50 Note on the backward analysis of TA g, a, C := 0 l l [C 0] 1 (Z (C = 0)) g Z Chennai january 2003 Timed Automata From Theory to Implementation p.28
51 Note on the backward analysis of TA g, a, C := 0 l l [C 0] 1 (Z (C = 0)) g Z Z Chennai january 2003 Timed Automata From Theory to Implementation p.28
52 Note on the backward analysis of TA g, a, C := 0 l l [C 0] 1 (Z (C = 0)) g Z Z [C 0] 1 (Z (C = 0)) Chennai january 2003 Timed Automata From Theory to Implementation p.28
53 Note on the backward analysis of TA g, a, C := 0 l l [C 0] 1 (Z (C = 0)) g Z Z [C 0] 1 (Z (C = 0)) Chennai january 2003 Timed Automata From Theory to Implementation p.28
54 Note on the backward analysis of TA g, a, C := 0 l l [C 0] 1 (Z (C = 0)) g Z Z [C 0] 1 (Z (C = 0)) [C 0] 1 (Z (C = 0)) g Chennai january 2003 Timed Automata From Theory to Implementation p.28
55 Note on the backward analysis of TA g, a, C := 0 l l [C 0] 1 (Z (C = 0)) g Z Z [C 0] 1 (Z (C = 0)) [C 0] 1 (Z (C = 0)) g The exact backward computation terminates and is correct! Chennai january 2003 Timed Automata From Theory to Implementation p.28
56 Note on the backward analysis of TA (cont.) If A is a timed automaton, we construct its corresponding set of regions. Because of the bisimulation property, we get that: Every set of valuations which is computed along the backward computation is a finite union of regions Chennai january 2003 Timed Automata From Theory to Implementation p.29
57 Note on the backward analysis of TA (cont.) If A is a timed automaton, we construct its corresponding set of regions. Because of the bisimulation property, we get that: Every set of valuations which is computed along the backward computation is a finite union of regions But, the backward computation is not so nice, when also dealing with integer variables... i := j.k + l.m Chennai january 2003 Timed Automata From Theory to Implementation p.29
58 Forward analysis of TA g, a, C := 0 l l zones Z [C 0]( Z g) A zone is a set of valuations defined by a clock constraint ϕ ::= x c x y c ϕ ϕ Chennai january 2003 Timed Automata From Theory to Implementation p.30
59 Forward analysis of TA g, a, C := 0 l l zones Z [C 0]( Z g) Z Chennai january 2003 Timed Automata From Theory to Implementation p.30
60 Forward analysis of TA g, a, C := 0 l l zones Z [C 0]( Z g) Z Z Chennai january 2003 Timed Automata From Theory to Implementation p.30
61 Forward analysis of TA g, a, C := 0 l l zones Z [C 0]( Z g) Z Z Z g Chennai january 2003 Timed Automata From Theory to Implementation p.30
62 Forward analysis of TA g, a, C := 0 l l zones Z [C 0]( Z g) Z Z Z g [y 0]( Z g) Chennai january 2003 Timed Automata From Theory to Implementation p.30
63 Forward analysis of TA g, a, C := 0 l l zones Z [C 0]( Z g) Z Z Z g [y 0]( Z g) a termination problem Chennai january 2003 Timed Automata From Theory to Implementation p.30
64 Non Termination of the Forward Analysis y := 0, x := 0 x 1 y = 1, y := 0 y x an infinite number of steps... Chennai january 2003 Timed Automata From Theory to Implementation p.31
65 Solutions to this problem (f.ex. in [Larsen,Pettersson,Yi 1997] or in [Daws,Tripakis 1998]) inclusion checking: if Z Z and Z still handled, then we don t need to handle Z correct w.r.t. reachability... Chennai january 2003 Timed Automata From Theory to Implementation p.32
66 Solutions to this problem (f.ex. in [Larsen,Pettersson,Yi 1997] or in [Daws,Tripakis 1998]) inclusion checking: if Z Z and Z still handled, then we don t need to handle Z correct w.r.t. reachability activity: eliminate redundant clocks [Daws,Yovine 1996] correct w.r.t. reachability q g,a,c:=0 q = Act(q) = clocks(g) (Act(q ) \ C)... Chennai january 2003 Timed Automata From Theory to Implementation p.32
67 Solutions to this problem (cont.) convex-hull approximation: if Z and Z are computed then we overapproximate using Z Z. semi-correct w.r.t. reachability Chennai january 2003 Timed Automata From Theory to Implementation p.33
68 Solutions to this problem (cont.) convex-hull approximation: if Z and Z are computed then we overapproximate using Z Z. semi-correct w.r.t. reachability extrapolation, a widening operator on zones Chennai january 2003 Timed Automata From Theory to Implementation p.33
69 The DBM data structure DBM (Difference Bounded Matrice) data structure [Dill89] (x 1 3) (x 2 5) (x 1 x 2 4) x 0 x 1 x 2 x 0 x 1 x Chennai january 2003 Timed Automata From Theory to Implementation p.34
70 The DBM data structure DBM (Difference Bounded Matrice) data structure [Dill89] (x 1 3) (x 2 5) (x 1 x 2 4) x 0 x 1 x 2 x 0 x 1 x Existence of a normal form Chennai january 2003 Timed Automata From Theory to Implementation p.34
71 The DBM data structure DBM (Difference Bounded Matrice) data structure [Dill89] (x 1 3) (x 2 5) (x 1 x 2 4) x 0 x 1 x 2 x 0 x 1 x Existence of a normal form All previous operations on zones can be computed using DBMs Chennai january 2003 Timed Automata From Theory to Implementation p.34
72 The extrapolation operator Fix an integer k ( represents an integer between k and +k) > k + < k k intuitively, erase non-relevant constraints ensures termination Chennai january 2003 Timed Automata From Theory to Implementation p.35
73 The extrapolation operator Fix an integer k ( represents an integer between k and +k) > k + < k k intuitively, erase non-relevant constraints 2 2 ensures termination Chennai january 2003 Timed Automata From Theory to Implementation p.35
74 The extrapolation operator Fix an integer k ( represents an integer between k and +k) > k + < k k intuitively, erase non-relevant constraints 2 2 ensures termination Chennai january 2003 Timed Automata From Theory to Implementation p.35
75 Challenge Propose a good constant for the extrapolation: keep the correctness of the forward computation Solution by the past: maximal constant appearing in the automaton Several correctness proofs can be found Implemented in tools like UPPAAL, KRONOS, RT-SPIN... Successfully used on real-life examples Chennai january 2003 Timed Automata From Theory to Implementation p.36
76 Challenge Propose a good constant for the extrapolation: keep the correctness of the forward computation Solution by the past: maximal constant appearing in the automaton Several correctness proofs can be found Implemented in tools like UPPAAL, KRONOS, RT-SPIN... Successfully used on real-life examples However... Chennai january 2003 Timed Automata From Theory to Implementation p.36
77 A problematic automaton x 3 3 x 2 = 3 x 1 = 2, x 1 := 0 x 1, x 3 := 0 x 2 := 0 x 1 = 2 x 1 := 0 x 2 = 2, x 2 := 0 x 2 x 1 > 2 x 1 = 3 x 2 = 2 The loop Error x 4 x 3 < 2 x 1 := 0 x 2 := 0 Chennai january 2003 Timed Automata From Theory to Implementation p.37
78 A problematic automaton x 3 3 x 2 = 3 x 1 = 2, x 1 := 0 x 1, x 3 := 0 x 2 := 0 x 1 = 2 x 1 := 0 x 2 = 2, x 2 := 0 x 2 x 1 > 2 x 1 = 3 x 2 = 2 The loop Error x 4 x 3 < 2 x 1 := 0 x 2 := 0 v(x 1 ) = 0 v(x 2 ) = d v(x 3 ) = 2α + 5 v(x 4 ) = 2α d Chennai january 2003 Timed Automata From Theory to Implementation p.37
79 A problematic automaton x 3 3 x 2 = 3 x 1 = 2, x 1 := 0 x 1, x 3 := 0 x 2 := 0 x 1 = 2 x 1 := 0 x 2 = 2, x 2 := 0 x 2 x 1 > 2 x 1 = 3 x 2 = 2 The loop Error x 4 x 3 < 2 x 1 := 0 x 2 := 0 v(x 1 ) = 0 v(x 2 ) = d v(x 3 ) = 2α + 5 v(x 4 ) = 2α d [1; 3] [2α + 5] x 2 x 1 x 3 x 4 [2α + 5] [1; 3] Chennai january 2003 Timed Automata From Theory to Implementation p.37
80 The problematic zone [1; 3] [2α + 5] x 2 x 1 x 3 x 4 [2α + 5] [1; 3] implies x 1 x 2 = x 3 x 4. [2α + 2; 2α + 4] [2α + 6; 2α + 8] Chennai january 2003 Timed Automata From Theory to Implementation p.38
81 The problematic zone [1; 3] [2α + 5] x 2 x 1 x 3 x 4 [2α + 5] [1; 3] implies x 1 x 2 = x 3 x 4. [2α + 2; 2α + 4] [2α + 6; 2α + 8] If α is sufficiently large, after extrapolation: [1; 3] x 2 x 1 x 3 x 4 [1; 3] does not imply x 1 x 2 = x 3 x 4. > k Chennai january 2003 Timed Automata From Theory to Implementation p.38
82 General abstractions Criteria for a good abstraction operator Abs: [Bouyer03] Chennai january 2003 Timed Automata From Theory to Implementation p.39
83 General abstractions Criteria for a good abstraction operator Abs: easy computation Abs(Z) is a zone if Z is a zone [Effectiveness] [Bouyer03] Chennai january 2003 Timed Automata From Theory to Implementation p.39
84 General abstractions Criteria for a good abstraction operator Abs: easy computation Abs(Z) is a zone if Z is a zone finiteness of the abstraction {Abs(Z) Z zone} is finite [Effectiveness] [Termination] [Bouyer03] Chennai january 2003 Timed Automata From Theory to Implementation p.39
85 General abstractions Criteria for a good abstraction operator Abs: easy computation Abs(Z) is a zone if Z is a zone finiteness of the abstraction {Abs(Z) Z zone} is finite completeness of the abstraction Z Abs(Z) [Effectiveness] [Termination] [Completeness] [Bouyer03] Chennai january 2003 Timed Automata From Theory to Implementation p.39
86 General abstractions Criteria for a good abstraction operator Abs: easy computation Abs(Z) is a zone if Z is a zone finiteness of the abstraction {Abs(Z) Z zone} is finite completeness of the abstraction Z Abs(Z) soundness of the abstraction the computation of (Abs Post) is correct w.r.t. reachability [Effectiveness] [Termination] [Completeness] [Soundness] [Bouyer03] Chennai january 2003 Timed Automata From Theory to Implementation p.39
87 General abstractions Criteria for a good abstraction operator Abs: easy computation Abs(Z) is a zone if Z is a zone finiteness of the abstraction {Abs(Z) Z zone} is finite completeness of the abstraction Z Abs(Z) soundness of the abstraction the computation of (Abs Post) is correct w.r.t. reachability [Effectiveness] [Termination] [Completeness] [Soundness] For the previous automaton, no abstraction operator can satisfy all these criteria! [Bouyer03] Chennai january 2003 Timed Automata From Theory to Implementation p.39
88 Why that? Assume there is a nice operator Abs. The set {M DBM representing a zone Abs(Z)} is finite. k the max. constant defining one of the previous DBMs We get that, for every zone Z, Z Extra k (Z) Abs(Z) Chennai january 2003 Timed Automata From Theory to Implementation p.40
89 Problem! Open questions: - which conditions can be made weaker? - find a clever termination criterium? - use an other data structure than zones/dbms? Chennai january 2003 Timed Automata From Theory to Implementation p.41
90 What can we cling to? Diagonal-free: only guards x c (no guard x y c) Theorem: the classical algorithm is correct for diagonal-free timed automata. [Bouyer03] Chennai january 2003 Timed Automata From Theory to Implementation p.42
91 What can we cling to? Diagonal-free: only guards x c (no guard x y c) Theorem: the classical algorithm is correct for diagonal-free timed automata. General: both guards x c and x y c Proposition: the classical algorithm is correct for timed automata that use less than 3 clocks. (the constant used is bigger than the maximal constant...) [Bouyer03] Chennai january 2003 Timed Automata From Theory to Implementation p.42
92 Conclusion & Further Work Decidability is quite well understood. A rather big problem with the forward analysis of timed automata needs to be solved. a very unsatisfactory solution for dealing with diagonal constraints. maybe the zones are not the optimal objects that we can deal with. To be continued... Some other current challenges: adding C macros to timed automata reducing the memory consumption via new data structures Chennai january 2003 Timed Automata From Theory to Implementation p.43
93 Bibliography [ACD+92] Alur, Courcoubetis, Dill, Halbwachs, Wong-Toi. Minimization of Timed Transition Systems. CONCUR 92 (LNCS 630). [AD90] Alur, Dill. Automata for Modeling Real-Time Systems. ICALP 90 (LNCS 443). [AD94] Alur, Dill. A Theory of Timed Automata. TCS 126(2), [AL02] Aceto, Laroussinie. Is your Model-Checker on Time? On the Complexity of Model-Checking for Timed Modal Logics. To appear in JLAP [BD00] Bérard, Dufourd. Timed Automata and Additive Clock Constraints. IPL 75(1 2), [BDFP00a] Bouyer, Dufourd, Fleury, Petit. Are Timed Automata Updatable? CAV 00 (LNCS 1855). [BDFP00b] [BDGP98] [BF99] Bouyer, Dufourd, Fleury, Petit. Expressiveness of Updatable Timed Automata. MFCS 00 (LNCS 1893). Bérard, Diekert, Gastin, Petit. Characterization of the Expressive Power of Silent Transitions in Timed Automata. Fundamenta Informaticae 36(2 3), Bérard, Fribourg. Automatic Verification of a Parametric Real-Time Program: the ABR Conformance Protocol. CAV 99 (LNCS 1633). Chennai january 2003 Timed Automata From Theory to Implementation p.44
94 Bibliography (cont.) [Bouyer03] [Dill89] [DT98] [DY96] [LPY97] Bouyer. Untameable Timed Automata! To appear in STACS 03. Dill. Timing Assumptions and Verification of Finite-State Concurrent Systems. Aut. Verif. Methods for Fin. State Sys. (LNCS 1989). Daws, Tripakis. Model-Checking of Real-Time Reachability Properties using Abstractions. TACAS 98 (LNCS 1384). Daws, Yovine. Reducing the Number of Clock Variables of Timed Automata. RTSS 96. Larsen, Pettersson, Yi. UPPAAL in a Nutshell. Software Tools for Technology Transfer 1(1 2), [Minsky67] Minsky. Computation: Finite and Infinite Machines [TY01] Tripakis, Yovine. Analysis of Timed Systems using Time-Abstracting Bisimulations. FMSD 18(1), Hytech: Kronos: Uppaal: tah/hytech/ Chennai january 2003 Timed Automata From Theory to Implementation p.45
Timed Automata: Semantics, Algorithms and Tools
Timed Automata: Semantics, Algorithms and Tools Johan Bengtsson and Wang Yi Uppsala University Email: {johanb,yi}@it.uu.se Abstract. This chapter is to provide a tutorial and pointers to results and related
More informationCOMP 763. Eugene Syriani. Ph.D. Student in the Modelling, Simulation and Design Lab School of Computer Science. McGill University
Eugene Syriani Ph.D. Student in the Modelling, Simulation and Design Lab School of Computer Science McGill University 1 OVERVIEW In the context In Theory: Timed Automata The language: Definitions and Semantics
More informationTimed Automata with Asynchronous Processes: Schedulability and Decidability
Timed Automata with Asynchronous Processes: Schedulability and Decidability Elena Fersman, Paul Pettersson and Wang Yi Uppsala University, Sweden Abstract. In this paper, we exend timed automata with asynchronous
More informationSpecification and Analysis of Real-Time Systems Using Real-Time Maude
Specification and Analysis of Real-Time Systems Using Real-Time Maude Peter Csaba Ölveczky1,2 and José Meseguer 1 1 Department of Computer Science, University of Illinois at Urbana-Champaign 2 Department
More informationRT-Studio: A tool for modular design and analysis of realtime systems using Interpreted Time Petri Nets
RT-Studio: A tool for modular design and analysis of realtime systems using Interpreted Time Petri Nets Rachid Hadjidj and Hanifa Boucheneb Abstract. RT-Studio (Real Time Studio) is an integrated environment
More informationReducing Clocks in Timed Automata while Preserving Bisimulation
Reducing Clocks in Timed Automata while Preserving Bisimulation Shibashis Guha Chinmay Narayan S. Arun-Kumar Indian Institute of Technology Delhi {shibashis, chinmay, sak}@cse.iitd.ac.in arxiv:1404.6613v2
More informationTimed Automata. Rajeev Alur. University of Pennsylvania
Timed Automata Rajeev Alur University of Pennsylvania www.cis.upenn.edu/~alur/ SFM-RT, Bertinoro, Sept 2004 model temporal property Model Checker yes error-trace Advantages Automated formal verification,
More informationSoftware Testing IV. Prof. Dr. Holger Schlingloff. Humboldt-Universität zu Berlin
Software Testing IV Prof. Dr. Holger Schlingloff Humboldt-Universität zu Berlin and Fraunhofer Institute of Computer Architecture and Software Technology FIRST Outline of this Lecture Series 2006/11/24:
More informationFine-grained Compatibility and Replaceability Analysis of Timed Web Service Protocols
Fine-grained Compatibility and Replaceability Analysis of Timed Web Service Protocols Julien Ponge 1,2, Boualem Benatallah 2, Fabio Casati 3 and Farouk Toumani 1 (1) Université Blaise Pascal, Clermont-Ferrand,
More informationLecture 2. Decidability and Verification
Lecture 2. Decidability and Verification model temporal property Model Checker yes error-trace Advantages Automated formal verification, Effective debugging tool Moderate industrial success In-house groups:
More informationQuantitative analysis of real-time systems
Quantitative analysis of real-time systems Patricia Bouyer bouyer@lsv.ens-cachan.fr Kim G. Larsen kgl@cs.aau.dk LSV CNRS & ENS Cachan 6 avenue du Président Wilson 9 Cachan France Uli Fahrenberg uli@cs.aau.dk
More informationA Test Case Generation Algorithm for Real-Time Systems
A Test Case Generation Algorithm for Real-Time Systems Anders Hessel and Paul Pettersson Department of Information Technology Uppsala University, P.O. Box 337 SE-751 05 Uppsala, Sweden {hessel,paupet}@it.uu.se
More informationModel checking pushdown systems
Model checking pushdown systems R. Ramanujam Institute of Mathematical Sciences, Chennai jam@imsc.res.in Update Meeting, IIT-Guwahati, 4 July 2006 p. 1 Sources of unboundedness Data manipulation: integers,
More informationLecture 9: Reachability
Lecture 9: Reachability Outline of Lecture Reachability General Transition Systems Algorithms for Reachability Safety through Reachability Backward Reachability Algorithm Given hybrid automaton H : set
More informationReachability Analysis for Timed Automata using Max-Plus Algebra
Reachability Analysis for Timed Automata using Max-Plus Algebra DAT5, Fall 2010 Group d504a 7th semester Department of Computer Science Aalborg University January 17th 2011 Title: Reachability Analysis
More informationAutomatic synthesis of switching controllers for linear hybrid systems: Reachability control
Automatic synthesis of switching controllers for linear hybrid systems: Reachability control Massimo Benerecetti and Marco Faella Università di Napoli Federico II, Italy Abstract. We consider the problem
More informationStochastic Games for Verification of Probabilistic Timed Automata
Stochastic ames for Verification of Probabilistic Timed Automata Marta Kwiatkowska, ethin Norman, and David Parker Oxford University Computing Laboratory, Parks Road, Oxford, OX1 3QD Abstract. Probabilistic
More informationGraphical Tool For SC Automata.
Graphical Tool For SC Automata. Honours Project: 2000 Dr. Padmanabhan Krishnan 1 Luke Haslett 1 Supervisor Abstract SC automata are a variation of timed automata which are closed under complementation.
More informationReal-time Testing with Timed Automata Testers and Coverage Criteria
Real-time Testing with Timed Automata Testers and Coverage Criteria Moez Krichen and Stavros Tripakis VERIMAG Centre Equation, 2, avenue de Vignate, 38610 Gières, France. www-verimag.imag.fr. Abstract.
More informationAN ABSTRACTION TECHNIQUE FOR REAL-TIME VERIFICATION
AN ABSTRACTION TECHNIQUE FOR REAL-TIME VERIFICATION Edmund M. Clarke, Flavio Lerda, Muralidhar Talupur Computer Science Department Carnegie Mellon University Pittsburgh, PA 15213 {flerda,tmurali,emc}@cs.cmu.edu
More informationplant OUTLINE The Same Goal: Reliable Controllers Who is Who in Real Time Systems
OUTLINE Introduction Lecture 1: Motivation, examples, problems to solve Modeling and Verication of Timed Systems Lecture 2: Timed automata, and timed automata in UAAL Lecture 3: Symbolic verification:
More informationReal-time Testing with Timed Automata Testers and Coverage Criteria
Unité Mixte de Recherche 5104 CNRS - INPG - UJF Centre Equation 2, avenue de VIGNATE F-38610 GIERES tel : +33 456 52 03 40 fax : +33 456 52 03 50 http://www-verimag.imag.fr Real-time Testing with Timed
More informationKronos: A Model-Checking Tool for Real-Time Systems*
Kronos: A Model-Checking Tool for Real-Time Systems* Marius Bozga ], Conrado Daws 1, Oded Maler 1, Alfredo Olivero 2, Stavros Tripakis 1 and Sergio Yovine 3 ~ 1 VERIMAG, Centre ]~quation, 2 avenue de Vignate,
More informationVerifying Periodic Task-Control Systems. Vlad Rusu? Abstract. This paper deals with the automated verication of a class
Verifying Periodic Task-Control Systems Vlad Rusu? Abstract. This paper deals with the automated verication of a class of task-control systems with periods, durations, and scheduling specications. Such
More informationUPPAAL. Verification Engine, Options & Patterns. Alexandre David
UPPAAL Verification Engine, Options & Patterns Alexandre David 1.2.05 Outline UPPAAL Modelling Language Specification Language UPPAAL Verification Engine Symbolic exploration algorithm Zones & DBMs Verification
More informationwant turn==me wait req2==0
Uppaal2k: Small Tutorial Λ 16 October 2002 1 Introduction This document is intended to be used by new comers to Uppaal and verification. Students or engineers with little background in formal methods should
More informationUnder-Approximation Refinement for Timed Automata
Under-Approximation Refinement for Timed Automata Bachelor s thesis Natural Science Faculty of the University of Basel Department of Mathematics and Computer Science Artificial Intelligence http://ai.cs.unibas.ch/
More informationEfficient Synthesis of Production Schedules by Optimization of Timed Automata
Efficient Synthesis of Production Schedules by Optimization of Timed Automata Inga Krause Institute of Automatic Control Engineering Technische Universität München inga.krause@mytum.de Joint Advanced Student
More informationPriced Timed Automata and Timed Games. Kim G. Larsen Aalborg University, DENMARK
Priced Timed Automata and Timed Games Kim G. Larsen Aalborg University, DENMARK Scheduling Priced Timed Automata and Synthesis Timed Games Kim G. Larsen Aalborg University, DENMARK Overview Timed Automata
More informationDeep Random Search for Efficient Model Checking of Timed Automata
Deep Random Search for Efficient Model Checking of Timed Automata R. Grosu 1,X.Huang 1,S.A.Smolka 1,W.Tan 1, and S. Tripakis 2 1 Dept. of CS, Stony Brook Univ., Stony Brook, NY 11794, USA {grosu,xhuang,sas,wktan}@cs.sunysb.edu
More informationMANY real-time applications need to store some data
Proceedings of the International Multiconference on Computer Science and Information Technology pp. 673 678 ISBN 978-83-60810-14-9 ISSN 1896-7094 Modeling Real-Time Database Concurrency Control Protocol
More informationMore on Verification and Model Checking
More on Verification and Model Checking Wednesday Oct 07, 2015 Philipp Rümmer Uppsala University Philipp.Ruemmer@it.uu.se 1/60 Course fair! 2/60 Exam st October 21, 8:00 13:00 If you want to participate,
More informationAn MTBDD-based Implementation of Forward Reachability for Probabilistic Timed Automata
An MTBDD-based Implementation of Forward Reachability for Probabilistic Timed Automata Fuzhi Wang and Marta Kwiatkowska School of Computer Science, University of Birmingham, Birmingham B15 2TT, United
More informationTowards Compositional Testing of Real-Time Systems
Towards Compositional Testing of Real-Time Systems Kim G Larsen, Axel Legay, Marius Mikucionis, Brian Nielsen, Ulrik Nyman Aalborg University, DENMARK Compositional Testing Integration of fully conformant
More informationerics: A Tool for Verifying Timed Automata and Estelle Specifications
erics: A Tool for Verifying Timed Automata and Estelle Specifications Piotr Dembiński, Agata Janowska, Pawe l Janowski, Wojciech Penczek,5, Agata Pó lrola, Maciej Szreter,Bożena Woźna 4, and Andrzej Zbrzezny
More informationAutomata-Theoretic LTL Model Checking. Emptiness of Büchi Automata
Automata-Theoretic LTL Model Checking Graph Algorithms for Software Model Checking (based on Arie Gurfinkel s csc2108 project) Automata-Theoretic LTL Model Checking p.1 Emptiness of Büchi Automata An automation
More informationhal , version 1-9 Apr 2009
Author manuscript, published in "Computer Aided Verification 10th International Conference, CAV'98, Vancouver, BC : Canada (1998)" DOI : 10.1007/BFb0028779 Kronos: a model-checking tool for real-time systems?
More informationReal Time Software PROBLEM SETTING. Real Time Systems. Real Time Systems. Who is Who in Timed Systems. Real Time Systems
Schedulability Analysis of Timed Systems with contributions from PROBLEM SETTING Tobias Amnell, Elena Fersma, John Håkansson, Pavel Kracal, Leonid Mokrushine, Christer Nordström, Paul Pettersson and Anders
More informationLanguage Overview for PHAVer version 0.35
Language Overview for PHAVer version 0.35 Goran Frehse June 22, 2006 We have tried to construct a textual input language that is as user friendly as possible, while keeping the parser simple. In the syntax,
More informationRewriting Models of Boolean Programs
Rewriting Models of Boolean Programs Javier Esparza University of Stuttgart Joint work with Ahmed Bouajjani Automatic verification using model-checking Initiated in the early 80s in USA and France. 25
More informationEliminating the Storage Tape in Reachability Constructions
Eliminating the Storage Tape in Reachability Constructions Oscar H. Ibarra Department of Computer Science University of California Santa Barbara, CA 93106, USA Zhe Dang School of Electrical Engineering
More informationHybrid Acceleration using Real Vector Automata (extended abstract)
Appears in: Proc. of 15th International Conference on Computer-Aided Verification, Boulder, Colorado, USA, Lecture Notes in Computer Science, volume 2725, pp. 193-205, Springer-Verlag, July 2003. Hybrid
More informationDynamic Clock Elimination in Parametric Timed Automata
FSFMA 2013 16th July 2013 Singapore Dynamic Clock Elimination in Parametric Timed Automata Étienne André Laboratoire d'informatique de Paris Nord Université Paris 13, Sorbonne Paris Cité Étienne André
More informationMulti-Clock Timed Networks
Multi-Clock Timed Networks arosh Aziz Abdulla, Johann Deneux, and ritha Mahata Dept of Information Technology Uppsala University Sweden parosh,johannd,pritha @ituuse Abstract We consider verification of
More informationModeling and Verification of Priority Assignment in Real-Time Databases Using Uppaal
Modeling and Verification of Priority Assignment in Real-Time Databases Using Uppaal Martin Kot Martin Kot Center for Applied Cybernetics, Department of Computer Science, FEI, Center for Applied VSBCybernetics,
More informationAutomated Formal Methods for Embedded Systems
Automated Formal Methods for Embedded Systems Bernd Finkbeiner Universität des Saarlandes Reactive Systems Group 2011/02/03 Bernd Finkbeiner (UdS) Embedded Systems 2011/02/03 1 / 48 Automated Formal Methods
More informationReasoning about Timed Systems Using Boolean Methods
Reasoning about Timed Systems Using Boolean Methods Sanjit A. Seshia EECS, UC Berkeley Joint work with Randal E. Bryant (CMU) Kenneth S. Stevens (Intel, now U. Utah) Timed System A system whose correctness
More informationBehavioural Equivalences and Abstraction Techniques. Natalia Sidorova
Behavioural Equivalences and Abstraction Techniques Natalia Sidorova Part 1: Behavioural Equivalences p. p. The elevator example once more How to compare this elevator model with some other? The cabin
More informationTiPEX: A Tool Chain for Timed Property Enforcement During execution
TiPEX: A Tool Chain for Timed Property Enforcement During execution Srinivas Pinisetty, Yliès Falcone, Thierry Jéron, Hervé Marchand To cite this version: Srinivas Pinisetty, Yliès Falcone, Thierry Jéron,
More informationAction Language Verifier, Extended
Action Language Verifier, Extended Tuba Yavuz-Kahveci 1, Constantinos Bartzis 2, and Tevfik Bultan 3 1 University of Florida 2 Carnegie Mellon University 3 UC, Santa Barbara 1 Introduction Action Language
More informationAutomatic Verification of the IEEE-1394 Root Contention Protocol with KRONOS and PRISM
Software Tools for Technology Transfer manuscript No. (will be inserted by the editor) Automatic Verification of the IEEE-1394 Root Contention Protocol with KRONOS and PRISM Conrado Daws 1, Marta Kwiatkowska
More informationUPPAAL Tutorial. UPPAAL Family
UPPAAL Tutorial Beyond UPPAAL Alexandre David Paul Pettersson RTSS 05 Classic : real-time verification Cora: real-time scheduling Tron: online real-time testing Tiga: timed game Times: schedulability analysis
More informationGSPeeDI a Verification Tool for Generalized Polygonal Hybrid Systems
GSPeeDI a Verification Tool for Generalized Polygonal Hybrid Systems Hallstein A. Hansen 1 and Gerardo Schneider 2 1 Buskerud University College, Kongsberg, Norway Hallstein.Asheim.Hansen@hibu.no 2 Dept.
More informationTowards Validated Real-Time Software
Towards Validated Real-Time Software Valérie BERTIN, Michel POIZE, Jacques PULOU France Télécom - Centre National d'etudes des Télécommunications 28 chemin du Vieux Chêne - BP 98-38243 Meylan cedex - France
More informationDeveloping Uppaal over 15 Years
Developing Uppaal over 15 Years Gerd Behrmann 1, Alexandre David 2, Kim Guldstrand Larsen 2, Paul Pettersson 3, and Wang Yi 4 1 NORDUnet A/S, Copenhagen, Denmark 2 Department of Computer Science, Aalborg
More informationCritical Analysis of Computer Science Methodology: Theory
Critical Analysis of Computer Science Methodology: Theory Björn Lisper Dept. of Computer Science and Engineering Mälardalen University bjorn.lisper@mdh.se http://www.idt.mdh.se/ blr/ March 3, 2004 Critical
More informationCounting multiplicity over infinite alphabets
Counting multiplicity over infinite alphabets Amal Dev Manuel and R. Ramanujam The Institute of Mathematical Sciences, Chennai, India {amal,jam}@imsc.res.in Summary Motivation for infinite data. We need
More informationA Gentle Introduction to Program Analysis
A Gentle Introduction to Program Analysis Işıl Dillig University of Texas, Austin January 21, 2014 Programming Languages Mentoring Workshop 1 / 24 What is Program Analysis? Very broad topic, but generally
More informationUPPAAL. Validation and Verication of Real Time Systems. Status & Developments y. Abstract
UPPAAL Validation and Verication of Real Time Systems Status & Developments y Kim G Larsen z Paul Pettersson x Wang Yi x Abstract Uppaal is a tool box for validation (via graphical simulation) and verication
More informationEditor. Analyser XML. Scheduler. generator. Code Generator Code. Scheduler. Analyser. Simulator. Controller Synthesizer.
TIMES - A Tool for Modelling and Implementation of Embedded Systems Tobias Amnell, Elena Fersman, Leonid Mokrushin, Paul Pettersson, and Wang Yi? Uppsala University, Sweden Abstract. Times is a new modelling,
More informationVerification of Petri net properties in CLP
V C L 2 0 0 0 I m p l e x e Operational Intelligence Verification of Petri net properties in CLP Guy A. Narboni implexe @ gulliver.fr In this report, we show how to model a Petri net as a CLP program and
More informationComputing Delay with Coupling Using Timed Automata
Computing Delay with Coupling Using Timed Automata Serdar Taşıran, Yuji Kukimoto and Robert K. Brayton Department of Electrical Engineering and Computer Sciences, University of California, Berkeley Deep
More informationMODEL-BASED DESIGN OF CODE FOR PLC CONTROLLERS
Krzysztof Sacha Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warszawa, Poland k.sacha@ia.pw.edu.pl Keywords: Abstract: Automatic program generation, Model verification, Finite state machine,
More informationSynthesis of Optimal Strategies Using HyTech
GDV 2004 Preliminary Version Synthesis of Optimal Strategies Using HyTech Patricia Bouyer 1,2,3 LSV, UMR 8643, CNRS & ENS de Cachan, France Franck Cassez 1,2,4 IRCCyN, UMR 6597, CNRS, France Emmanuel Fleury
More informationModel checking and timed CTL
Chapter 6 Model checking and timed CTL Ah! What did I tell you? 88 miles per hour! The temporal displacement occurred at exactly 1:20am and *zero* seconds! [Dr Emmett Brown] 6.1 Timed CTL Page 86 Formal
More informationA game-theoretic approach to real-time system testing David, Alexandre; Larsen, Kim Guldstrand; Li, Shuhao; Nielsen, Brian
Aalborg Universitet A game-theoretic approach to real-time system testing David, Alexandre; Larsen, Kim Guldstrand; Li, Shuhao; Nielsen, Brian Published in: Design, Automation and Test in Europe DOI (link
More informationDistributed Memory LTL Model Checking
! " #$ %& D E ')(+*,.-0/132?@ACB 46587:9= F GH Faculty of Informatics Masaryk University Brno Distributed Memory LTL Model Checking Ph.D. Thesis Jiří Barnat September 2004 Abstract Distribution and
More informationALASKA Antichains for Logic, Automata and Symbolic Kripke structures Analysis
ALASKA Antichains for Logic, Automata and Symbolic Kripke structures Analysis M. De Wulf 1, L. Doyen 2, N. Maquet 1 and J.-F. Raskin 1 1 Université Libre de Bruxelles (ULB), Belgium 2 École Polytechnique
More informationKahina Gani, Marinette Bouet, Michel Schneider, and Farouk Toumani. 1 2
Modeling Home Care Plans Kahina Gani, Marinette Bouet, Michel Schneider, and Farouk Toumani. 1 2 Research Report LIMOS/RR-14-02 12 mai 2014 1. {gani,michel.schneider,ftoumani}@isima.fr 2. marinette.bouet@univ-bpclermont.fr
More informationLimitations of Algorithmic Solvability In this Chapter we investigate the power of algorithms to solve problems Some can be solved algorithmically and
Computer Language Theory Chapter 4: Decidability 1 Limitations of Algorithmic Solvability In this Chapter we investigate the power of algorithms to solve problems Some can be solved algorithmically and
More informationTheory of Computations Spring 2016 Practice Final Exam Solutions
1 of 8 Theory of Computations Spring 2016 Practice Final Exam Solutions Name: Directions: Answer the questions as well as you can. Partial credit will be given, so show your work where appropriate. Try
More informationAdvanced Programming Methods. Introduction in program analysis
Advanced Programming Methods Introduction in program analysis What is Program Analysis? Very broad topic, but generally speaking, automated analysis of program behavior Program analysis is about developing
More informationPast Pushdown Timed Automata and Safety Verification
Past Pushdown Timed Automata and Safety Verification Zhe Dang, Tevfik Bultan, Oscar H. Ibarra, and Richard A. Kemmerer Abstract We consider past pushdown timed automata that are discrete pushdown timed
More informationModeling and Analysis of Fischer s Algorithm
Processes and Data, Department of Computer Science, Swansea University Vino - July 2011 Today s Talk 1. Mutual Exclusion Algorithms (recap) 2. Fischer s Algorithm 3. Modeling Fischer s Algorithm 4. Analysis
More informationTIMES A Tool for Modelling and Implementation of Embedded Systems
TIMES A Tool for Modelling and Implementation of Embedded Systems Tobias Amnell, Elena Fersman, Leonid Mokrushin, Paul Pettersson, and Wang Yi Uppsala University, Sweden. {tobiasa,elenaf,leom,paupet,yi}@docs.uu.se.
More informationPARAMETRIC VERIFICATION AND TEST COVERAGE FOR HYBRID AUTOMATA USING THE INVERSE METHOD
International Journal of Foundations of Computer Science c World Scientific Publishing Company PARAMETRIC VERIFICATION AND TEST COVERAGE FOR HYBRID AUTOMATA USING THE INVERSE METHOD LAURENT FRIBOURG Laboratoire
More informationReal-Time Model Checking on Secondary Storage
Real-Time Model Checking on Secondary Storage Stefan Edelkamp and Shahid Jabbar University of Dortmund Otto-Hahn Straße 14 Germany {stefan.edelkamp,shahid.jabbar}@cs.uni-dortmund.de Abstract. In this paper,
More informationThe SPIN Model Checker
The SPIN Model Checker Metodi di Verifica del Software Andrea Corradini Lezione 1 2013 Slides liberamente adattate da Logic Model Checking, per gentile concessione di Gerard J. Holzmann http://spinroot.com/spin/doc/course/
More informationTo Store or Not To Store
To Store or Not To Store Radek Pelánek Masaryk University, Brno Gerd Behrmann, Kim G. Larsen Aalborg University To Store or Not To Store p.1/24 Reachability Problem Model: networks of timed automata with
More informationSafra's Büchi determinization algorithm
Safra's Büchi determinization algorithm Aditya Oak Seminar on Automata Theory 28 Jan 2016 Introduction Proposed by S. Safra in 1988 For determinization of non-deterministic Büchi automaton Gives equivalent
More informationXuandong Li. BACH: Path-oriented Reachability Checker of Linear Hybrid Automata
BACH: Path-oriented Reachability Checker of Linear Hybrid Automata Xuandong Li Department of Computer Science and Technology, Nanjing University, P.R.China Outline Preliminary Knowledge Path-oriented Reachability
More informationInteraction Between Input and Output-Sensitive
Interaction Between Input and Output-Sensitive Really? Mamadou M. Kanté Université Blaise Pascal - LIMOS, CNRS Enumeration Algorithms Using Structure, Lorentz Institute, August 26 th, 2015 1 Introduction
More informationThe Apron Library. Bertrand Jeannet and Antoine Miné. CAV 09 conference 02/07/2009 INRIA, CNRS/ENS
The Apron Library Bertrand Jeannet and Antoine Miné INRIA, CNRS/ENS CAV 09 conference 02/07/2009 Context : Static Analysis What is it about? Discover properties of a program statically and automatically.
More informationModeling and Verification of Marine Equipment Systems Using a Model Checker
Modeling and Verification of Marine Equipment Systems Using a Model Checker Shunsuke YAO Hiroaki AWANO Yasushi HIRAOKA Kazuko TAKAHASHI Abstract We discuss the modeling and verification of marine equipment
More informationAn Introduction to UPPAAL. Purandar Bhaduri Dept. of CSE IIT Guwahati
An Introduction to UPPAAL Purandar Bhaduri Dept. of CSE IIT Guwahati Email: pbhaduri@iitg.ernet.in OUTLINE Introduction Timed Automata UPPAAL Example: Train Gate Example: Task Scheduling Introduction UPPAAL:
More informationUTILIZATION OF TIMED AUTOMATA AS A VERIFICATION TOOL FOR REAL-TIME SECURITY PROTOCOLS
UTILIZATION OF TIMED AUTOMATA AS A VERIFICATION TOOL FOR REAL-TIME SECURITY PROTOCOLS A Thesis Submitted to the Graduate School of Engineering and Sciences of İzmir Institute of Technology in Partial Fulfillment
More informationComputational Techniques for Hybrid System Verification
64 IEEE TRANSACTIONS ON AUTOMATIC CONTROL, VOL 48, NO 1, JANUARY 2003 Computational Techniques for Hybrid System Verification Alongkrit Chutinan Bruce H Krogh, Fellow, IEEE Abstract This paper concerns
More informationModel Checking with Abstract State Matching
Model Checking with Abstract State Matching Corina Păsăreanu QSS, NASA Ames Research Center Joint work with Saswat Anand (Georgia Institute of Technology) Radek Pelánek (Masaryk University) Willem Visser
More informationModeling and Analysis of Real -Time Systems with Mutex Components
Modeling and Analysis of Real -Time Systems with Mutex Components APDCM Guoqiang Li, Xiaojuan Cai,Shoji Yuen 2 BASICS, Shanghai Jiao Tong University 2 Graduate School of Information Science, Nagoya University
More informationExtending Synchronous Languages for Generating Abstract Real-Time Models
Extending Synchronous Languages for Generating Abstract Real-Time Models G. Logothetis and K. Schneider University of Karlsruhe Institute for Computer Design and Fault Tolerance (Prof. Dr.-Ing. D. Schmid)
More informationAcceleration of Affine Hybrid Transformations
Acceleration of Affine Hybrid Transformations Bernard Boigelot 1, Frédéric Herbreteau 2, and Isabelle Mainz 1 1 Institut Montefiore, B28, Univ. Liège, Belgium {boigelot,mainz}@montefiore.ulg.ac.be 2 Univ.
More informationExtensions of the algorithm to deal with hybrid systems, controller synthesis and continuous disturbances are described in section 4 along with severa
Approximate Reachability Analysis of Piecewise-Linear Dynamical Systems? Eugene Asarin 1, Olivier Bournez 2, Thao Dang 1, and Oded Maler 1 1 Verimag, Centre Equation, 2, av. de Vignate, 38610 Gieres, France
More informationTemporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols
Temporal Refinement Using SMT and Model Checking with an Application to Physical-Layer Protocols Lee Pike (Presenting), Galois, Inc. leepike@galois.com Geoffrey M. Brown, Indiana University geobrown@cs.indiana.edu
More informationExpressiveness of Minmax Automata
Expressiveness of Minmax Automata Amaldev Manuel LIAFA, Université Paris Diderot!! joint work with! Thomas Colcombet Stefan Göller Minmax Automata Finite state automaton equipped with +ve-integer registers
More informationOn the Language Inclusion Problem for Timed Automata: Closing a Decidability Gap
SVC On the Language Inclusion Problem for Timed Automata 1 On the Language Inclusion Problem for Timed Automata: Closing a Decidability Gap Joël Ouaknine Computer Science Department, Carnegie Mellon University
More informationProc. XVIII Conf. Latinoamericana de Informatica, PANEL'92, pages , August Timed automata have been proposed in [1, 8] to model nite-s
Proc. XVIII Conf. Latinoamericana de Informatica, PANEL'92, pages 1243 1250, August 1992 1 Compiling Timed Algebras into Timed Automata Sergio Yovine VERIMAG Centre Equation, 2 Ave de Vignate, 38610 Gieres,
More informationOur aim is to extend this language in order to take into account a large class of timing constraints on systems to describe. Then, we will present a m
Timed Automata Generation from Estelle Specications H. Fouchal M. Defoin-Platel S. Bloch P. Moreaux E. Petitjean Departement de Mathematiques et Informatique Universite de Reims Champagne-Ardenne Moulin
More informationProcessing Regular Path Queries Using Views or What Do We Need for Integrating Semistructured Data?
Processing Regular Path Queries Using Views or What Do We Need for Integrating Semistructured Data? Diego Calvanese University of Rome La Sapienza joint work with G. De Giacomo, M. Lenzerini, M.Y. Vardi
More informationOverview of Timed Automata and UPPAAL
Overview of Timed Automata and UPPAAL Table of Contents Timed Automata Introduction Example The Query Language UPPAAL Introduction Example Editor Simulator Verifier Conclusions 2 Introduction to Timed
More informationDSVerifier: A Bounded Model Checking Tool for Digital Systems
DSVerifier: A Bounded Model Checking Tool for Digital Systems Hussama I. Ismail, Iury V. Bessa, Lucas C. Cordeiro, Eddie B. de Lima Filho and João E. Chaves Filho Electronic and Information Research Center
More information