Quartus II Software and Device Support Release Notes Version 12.1 SP1

Transcription

1 Quartus II Software and Device Support Release Notes Version 12.1 SP1 RN SP1.2 Release Notes This document provides late-breaking information about the Altera Quartus II software version 12.1 SP1. This document contains the following sections: New Features & Enhancements on page 2 Memory Recommendations on page 3 Changes in Device Support on page 5 Changes to Software Behavior on page 10 Device Support and Pin-Out Status on page 11 Timing and Power Models on page 13 EDA Interface Information on page 15 Antivirus Verification on page 16 Software Issues Resolved on page 16 Software Patches Included in this Release on page 17 Latest Known Quartus II Software Issues on page 17 For information about operating system support, refer to the readme.txt file in your altera/<version number>/quartus directory. For the latest information about the MegaCore IP Library, refer to the MegaCore IP Library Release Notes and Errata. 101 Innovation Drive San Jose, CA Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services February 2013 Altera Corporation Subscribe

2 New Features & Enhancements Page 2 New Features & Enhancements The Quartus II software version 12.1 SP1 includes the following new features and enhancements: Enhanced device support: Full device support for the following Arria V devices: 5AGXA1, 5AGXA3, 5AGXB1, 5AGXB3, 5AGXB5, 5AGXB7, 5AGTC3, 5AGTD3, and 5AGTD7 Full device support for the following Arria V GZ devices: 5AGZE1, 5AGZE3, 5AGZE5, and 5AGZE7 Full device support for the following Cyclone V devices: Cyclone V: 5CEA2, 5CEA4, 5CEA7, 5CEA9, 5CGXC7, 5CGXC9, 5CGTD7, and 5CGTD9 Full device support for the following Stratix V devices: 5SEE9, 5SEEB, 5SGXA9, 5SGXAB, 5SGXB5, 5SGXB6, 5SGXB9, 5SGXBB, 5SGSD6, and 5SGSD8 Advance device support for the following Arria V devices: 5AGXA5, 5AGXA7, and 5AGTC7 Advance device support for the following Cyclone V devices: 5CEA5, 5CSEA5, 5CSEA6, 5CGXC3, 5CGXC4, 5CGXC5, 5CSXC5, 5CSXC6, 5CGTD5, 5CSTD5, and 5CSTD6 Initial information device support for the following Arria V devices: 5ASXB3, 5ASXB5, 5ASTD3, and 5ASTD5 An IP Regeneration feature that detects outdated IP in your design and prompts you to allow the Quartus II software to upgrade that IP to the latest versions. You can use the Quartus II Help with the following browsers: Local Quartus II Help (Help on a local drive installed by the Altera Installer) is fully compatible with Microsoft Internet Explorer 8, Mozilla Firefox 7.0, and Safari 5 running on Windows 7 operating systems. You can view the Quartus II Help in Google Chrome; however, you cannot open a Chrome browser from the Quartus II GUI. You must start Chrome with the --allow-file-access-from-files flag and then navigate to <quartus installation directory>/common/help/master.htm. Local Quartus II Help is fully compatible with Mozilla Firefox 3.6 running on Linux 32-bit systems. Quartus II Web Help (hosted at is fully compatible with Microsoft Internet Explorer 8, Mozilla Firefox 7.0, Safari 5, and Google Chrome. Some Help features require you to disable pop-up blocking.

3 Memory Recommendations Page 3 Memory Recommendations A full installation of the Quartus II software requires up to 10 GB of available disk space on the drive or partition where you are installing the Altera software. The Quartus II Stand-Alone Programmer requires a minimum of 1GB of RAM plus additional memory, based on the size and number of SRAM Object Files (.sof) files and the size and number of devices being configured. Altera recommends that your system be configured to provide virtual memory equal to the recommended physical RAM that is required to process your design. The following table lists the memory required to process designs targeted for Altera devices. Recommended Physical RAM Family Device 32-bit 64-bit EP1AGX MB 512 MB Arria GX EP1AGX35, EP1AGX50, EP1AGX GB 1.5 GB EP1AGX GB 2.0 GB EP2AGX GB 1.5 GB Arria II GX EP2AGX GB 2.0 GB EP2AGX95, EP2AGX125, EP2AGX GB 4.0 GB EP2AGX GB 6.0 GB EP2AGZ GB 4.0 GB Arria II GZ EP2AGZ GB 6.0 GB EP2AGZ350 Not recommended 8.0 GB 5AGXA1 Not recommended 6.0 GB 5AGTC3, 5AGXA3 Not recommended 8.0 GB Arria V 5AGXA5, 5AGXA7 Not recommended 10.0 GB 5AGXB1 Not recommended 12.0 GB 5AGXB3, 5AGXB5 Not recommended 16.0 GB 5AGTD7, 5AGXB7 Not recommended 20.0 GB Arria V GZ 5AGZE1 Not recommended 12.0 GB 5AGZE3, 5AGZE5, 5AGZE7 Not recommended 16.0 GB Cyclone All 512 MB 512 MB EP2C5, EP2C8, EP2C15, EP2C MB 512 MB Cyclone II EP2C35, EP2C GB 1.5 GB EP2C GB 2.0 GB EP3C5, EP3C10, EP3C16, EP3C25, EP3C MB 512 MB Cyclone III EP3C55, EP3C MB 1.0 GB EP3C GB 2.0 GB Cyclone III LS EP3CLS70, EP3CLS GB 2.0 GB EP3CLS150, EP3CLS GB 4.0 GB

4 Memory Recommendations Page 4 Cyclone IV E Cyclone IV GX Cyclone V HardCopy II HardCopy III EP4CE6, EP4CE10, EP4CE15, EP4CE22, EP4CE30, EP4CE MB 512 MB EP4CE55, EP4CE MB 1.0 GB EP4CE GB 1.5 GB EP4CGX15, EP4CGX22, EP4CGX MB 512 MB EP4CGX50, EP4CGX GB 1.5 GB EP4CGX110, EP4CGX GB 2.0 GB 5CEA2, 5CGXC3, 5CEA4, 5CGXC4, 5CEA5, 5CGTD5, 5CGXC5, 5CSEA5, 5CSTD5, 5CSXC5 Not recommended 6.0 GB 5CSEA6, 5CSXC6, 5CSXC6, 5CEA7, 5CEA7, 5CGTD7, 5CGTD7, 5CGXC7 Not recommended 8.0 GB 5CEA9, 5CGTD9, 5CGTD9, 5CGXC9 Not recommended 12.0 GB HC210, HC210W 1.5 GB 2.0 GB HC220, HC230, HC GB 4.0 GB HC325 HC335 Not recommended 8.0 GB 12.0 GB HC4E GB HardCopy IV HC4GX GB Not recommended HC4E35, HC4GX GB HC4GX GB MAX All 512 MB 512 MB MAX II All 512 MB 512 MB MAX V All 512 MB 512 MB Stratix Stratix GX Stratix II Stratix II GX Stratix III Family Device Recommended Physical RAM 32-bit EP1S10, EP1S MB 512 MB EP1S25, EP1S30, EP1S40, EP1S GB 1.5 GB EP1S GB 2.0 GB EP1SGX MB 512 MB EP1SGX25, EP1SGX GB 1.5 GB EP2S MB 512 MB EP2S GB 1.5 GB EP2S60, EP2S GB 2.0 GB EP2S130, EP2S GB 4.0 GB EP2SGX30, EP2SGX GB 1.5 GB EP2SGX GB 2.0 GB EP2SGX GB 4.0 GB EP3SL50, EP3SE50, EP3SL GB 1.5 GB EP3SE GB 2.0 GB EP3SL110, EP3SE110, EP3SL150, EP3SL GB 4.0 GB EP3SE260, EP3SL GB 6.0 GB 64-bit

5 Changes in Device Support Page 5 Stratix IV Stratix V Family Device Recommended Physical RAM 32-bit EP4SGX GB 2.0 GB EP4SE230 EP4SGX110, EP4SGX230, EP4S40G2, 3.0 GB 4.0 GB EP4S100G2 EP4SGX GB 6.0 GB EP4SE360 EP4SGX360, EP4S100G3, EP4S100G4 Not recommended 8.0 GB EP4SGX530, EP4SE530, EP4SE820, EP4S40G5, EP4S100G5 Not recommended 12.0 GB 5SGSD3 Not recommended 10.0 GB 5SGXA3 Not recommended 12.0 GB 5SGSD4, 5SGXA4, 5SGTC5, 5SGSD5, 5SGXA5, 5SGXB5 Not recommended 16.0 GB 5SGSD6, 5SGXB6, 5SGTC7, 5SGXA7 Not recommended 20.0 GB 5SGSD8, 5SGXA9 Not recommended 24.0 GB 5SEE9, 5SEEB, 5SGXAB Not recommended 28.0 GB 5SGXB9, 5SGXBB Not recommended 32.0 GB 64-bit Changes in Device Support The following section is divided into device support changes according to whether the change is a notification, and whether the change has been fixed or not fixed. Description Workaround Change Notifications Device Support Not Fixed Arria V timing model is missing a timing delay An issue has been identified with a missing delay in the Quartus II software version 12.1 SP1 Arria V timing model. VCCRSTCLK_HPS pin labelled incorrectly The VCCRSTCLK_HPS pin was incorrectly labelled as VCC_HPS. Applies to some Cyclone V SoC devices. Ordering Part Number (OPN) change for Cyclone V E50 devices. Some OPNs have been identified as incorrect. For up-to-date information about Arria V timing model issues in the Quartus II software version 12.1 SP1, refer to solution number rd _17 in the Altera Knowledge Base. Refer to the updated pinout table to identify both VCCRSTCLK_HPS pins. 5CEFA2 devices become 5CEBA2 devices 5CEFA4 devices become 5CEBA4 devices

6 Changes in Device Support Page 6 Description Quartus II software restricting ATX PLL range issue The Quartus II software does not restrict the ATX PLL range to the current performance specifications, which are documented in the current errata sheet for Stratix V devices on the Altera website. The Quartus II software assumes that all the ATX PLLs have exactly the same data rate performance. Therefore it is possible for the Fitter to implement an ATX PLL with settings outside the performance specifications of your selected device and assigned ATX PLL location. Applies to Stratix V devices. Workaround Ensure that your design compiles with the specifications in the errata sheet. You may need to manually assign ATX PLLs in your design to specific locations. Device Support Fixed Stratix V Periphery Clock Timing Incorrect timing models in the Quartus II software version 12.1 might result in hardware errors for designs that have low timing margin on paths that originate or end with a register clocked by a PCLK signal. This issue affects Stratix V designs that use PCLK global resources. The Stratix V timing model has changed in the Quartus II software version 12.1 SP1 for Periphery Clock (PCLK) signals. Stratix V Hold Timing Changes for LVDS-to-Core Transfers in nondpa mode Incorrect timing models in the Quartus II software version 12.1 might result in hardware errors for designs that have low hold time margins between LVDS in nondpa mode and core registers. The Stratix V timing model has changed in the Quartus II software version 12.1 SP1 to update the hold time requirement for transfers from the LVDS receiver s outputs to registers in the core. To determine whether a design compiled with the Quartus II software version 12.1 is affected by this issue: 1. Backup the design database. 2. Open the design in the Quartus II software version 12.1, and then export the database by clicking Project > Export Database. When you are prompted, export the database to the suggested export_db directory. 3. Start the Quartus II software version 12.1 SP1. 4. Open the database. When you are prompted whether to overwrite the older database version, click Yes. 5. Run TimeQuest timing analysis on the design. If there are timing violations, run the Fitter to close timing on the design. To determine whether a design compiled with the Quartus II software version 12.1 is affected by this issue: 1. Backup the design database. 2. Open the design in the Quartus II software version 12.1, and then export the database by clicking Project > Export Database. When you are prompted, export the database to the suggested export_db directory. 3. Start the Quartus II software version 12.1 SP1. 4. Open the database. When you are prompted whether to overwrite the older database version, click Yes. 5. Run TimeQuest timing analysis on the design. If there are timing violations, run the Fitter to close timing on the design.

7 Changes in Device Support Page 7 Description T CO reported for wide data widths in M20K blocks with registered outputs in Stratix V devices is incorrect T CO values reported by the TimeQuest Timing Analyzer for Stratix V M20K blocks that use more than 16 bits and that have registered outputs may be pessimistic. T CO values of output register bits 16 to 39 reported by TimeQuest can be pessimistic by as much as 500 ps. T CO values for bits 0 to 15 are reported correctly. Timing paths from Stratix V DSP input ports are not analyzed in some circumstances. In designs that target Stratix V devices, if DSP outputs are registered, but the RESULT ports are disconnected, which is common among filters, then any paths from the DSP input port to the DSP output register are not analyzed for timing. Timing delays reported from QCLK to SCLK for QCLKs 73 to 91 in Stratix V devices are incorrect For designs that target Stratix V devices, the timing delay from Regional Clocks (QCLKs) to Spine Clocks (SCLKs) on the right center and left center of the device (QCLKs 73 to 91) is incorrectly reported as zero. The actual delay for speed grade 3 devices at 85 C is approximately 1 ns. No pipe_pclk output issue The pipe_pclk clock cannot be activated on a non-global clock. Workaround To determine whether a design compiled with the Quartus II software version 12.1 is affected by this issue: 1. Backup the design database. 2. Open the design in the Quartus II software version 12.1, and then export the database by clicking Project > Export Database. When you are prompted, export the database to the suggested export_db directory. 3. Start the Quartus II software version 12.1 SP1. 4. Open the database. When you are prompted whether to overwrite the older database version, click Yes. 5. Run TimeQuest timing analysis on the design. If there are timing violations, run the Fitter to close timing on the design. To determine whether a design compiled with the Quartus II software version 12.1 is affected by this issue: 1. Backup the design database. 2. Open the design in the Quartus II software version 12.1, and then export the database by clicking Project > Export Database. When you are prompted, export the database to the suggested export_db directory. 3. Start the Quartus II software version 12.1 SP1. 4. Open the database. When you are prompted whether to overwrite the older database version, click Yes. 5. Run TimeQuest timing analysis on the design. If there are timing violations, run the Fitter to close timing on the design. To determine whether a design compiled with the Quartus II software version 12.1 is affected by this issue: 1. Backup the design database. 2. Open the design in the Quartus II software version 12.1, and then export the database by clicking Project > Export Database. When you are prompted, export the database to the suggested export_db directory. 3. Start the Quartus II software version 12.1 SP1. 4. Open the database. When you are prompted whether to overwrite the older database version, click Yes. 5. Run TimeQuest timing analysis on the design. If there are timing violations, run the Fitter to close timing on the design. The pipe_pclk clock must be on a global clock signal to function properly.

8 Changes in Device Support Page 8 Description Stratix V voltage support is incorrect In the Quartus II software versions 12.0 and 12.0 SP1, the voltage reported in the reports such as the TimeQuest reports and the Fitter report is incorrect for Stratix V speed grade C2. The reports show 850 mv when they should say 900 mv. Applies to Stratix V devices. Stratix V clock pin migration issue When migrating between 5SGXA5 or 5SGXA7 and 5SGXA9 or 5SGSAB devices, Quartus II software is unable to determine whether the clock connectivity on the migration device is legal. Quartus II cannot verify that the guidelines on page 4-24 of the Clock Networks and PLLs in Stratix V Devices document (Stratix V Handbook volume 1 chapter 4) are being correctly followed. Applies to Stratix V devices. OE delay chain offset issue Quartus II fails to set the delay chain offset if: You have not defined a timing constraint on the output pin, or The data on the pin is connected to VCC/GND, and OE path is not I/O registered. In power-up mode, you may observe glitches on the I/O pins. The issue is resolved in Quartus II software version 12.0 SP1. Applies to Arria V, Cyclone V, and Stratix V devices. Incorrect merging of TX PLLs for Arria V GT channels 10G PMA direct channels can only be driven by TX PLL within the same triplet but the fitter automatically merges TX PLL within the same six pack. This creates the situation where a TX PLL drives data channels from beyond the same triplet. Applies to Arria V GT devices. Stratix IV PMA Direct transceiver timing The Stratix IV timing model was changed in Quartus II software version 12.0 to update the delay model for PMA Direct transceiver interfaces. The issue affects designs that use the ALTGX Megafunction transceiver mode Basic (PMA Direct) in the transmitter. This mode uses a direct core-to-pma register transfer on the transmit side, instead of using the hard PCS logic and phase-compensation FIFO. The incorrect timing models in the Quartus II software version 11.1 SP2 and earlier may result in hardware errors (increased bit error rates, BER) for designs that have low timing margin on the affected timing path, especially at high temperature and low core voltage. Applies to Stratix IV devices. Workaround To verify migration compatibility, compile the design for each migration device using the same fixed pin assignments. To prevent TX PLL from merging incorrectly, use location assignment to constrain the locations of the TX PLLs so that they always stay within the same triplet as the data channel that they are driving. The location of the PLLs can be found in the Chip Planner. The TX PLL should be assigned to the central channel of a triplet. Refer to the following Knowledge Base solution: 5.html

9 Changes in Device Support Page 9 Description Stratix V VCCHIP power optimization For lower power of VCCHIP pins, target a Stratix V production (non-es) part and do not reference an ES part in the migration list. The VCCHIP pins must be powered up for ES parts, but not for production parts. To support pinout migration, Quartus II indicates that the VCCHIP pins must be powered when an ES device is used or when an ES device is included in the migration list. For more information please refer to the Stratix V E, GS, and GX Device Family Pin Connection Guidelines document. Applies to Stratix V devices CPRI placement on restricted triplet issue Previous restrictions on Ch0, Ch1, and Ch2 in GXB_L0 and GXB_R0 is update in the Quartus II software Ch0 in both GXB_L0 and GXB_R0 is now available for deterministic latency protocols. Applies to Arria V devices Workaround

10 Changes to Software Behavior Page 10 Changes to Software Behavior This section documents instances in which the behavior and default settings of the Quartus II software have been changed from earlier releases of the software. Refer to the Quartus II Default Settings File (.qdf), <Quartus II installation directory>/quartus/bin/assignment_defaults.qdf, for a list of all the default assignment settings for the latest version of the Quartus II software. Items listed in the following table represent cases in which the behavior of the current release of the Quartus II software is different from a previous version. Description Service Pack (SP) releases of the Altera Complete Design Suite are now complete installations. Incremental installation to update an existing installation is not supported. The Rapid Recompile feature is disabled in this release. SOPC Builder will not be provided in future versions of the Quartus II software beginning with version Workaround Unlike previous service pack releases, you do not need to install the Quartus II software version 12.1 before you install the Quartus II software version 12.1 SP1. There is no workaround. Use Qsys. For guidelines to migrate your design from SOPC Builder to Qsys, refer to SOPC Builder to Qsys Migration Guidelines.

11 Device Support and Pin-Out Status Page 11 Device Support and Pin-Out Status This section contains information about the device support status in the Quartus II software version Full Device Support Full compilation, simulation, timing analysis, and programming support is now available for the new devices listed in the following table. Device Family Devices Arria V Arria V GZ Cyclone V Stratix V 5AGXA1 5AGXB1 5AGXB5 5AGTC3 5AGTD7 5AGZE1 5AGZE5 5CEA2 5CEA7 5CGXC7 5CGTD7 5CGXC7ES 5SEE9 5SGXA9 5SGXB5 5SGXB9 5SGSD6 5AGXA3 5AGXB3 5AGXB7 5AGTD3 5AGZE3 5AGZE7 5CEA4 5CEA9 5CGXC9 5CGTD9 5CEA7ES 5SEEB 5SGXAB 5SGXB6 5SGXBB 5SGSD8

12 Device Support and Pin-Out Status Page 12 Advance Device Support Compilation, simulation, and timing analysis support is provided for the devices listed in Table 1 that will be released in the near future. The Compiler generates pin-out information for these devices in this release, but does not generate programming files. Table 1. Devices with Advance Support Arria V Cyclone V Device Family 5AGXA5 5AGTC7 5CEA5 5CSEA6 5CGXC4 5CSXC5 5CGTD5 5CSTD6 Devices 5AGXA7 5CSEA5 5CGXC3 5CGXC5 5CSXC6 5CSTD5

13 Timing and Power Models Page 13 Initial Information Device Support Compilation, simulation, and timing analysis support is provided for the devices listed in Table 2 that will be released in upcoming versions of the Quartus II software. Programming files and pin-out information are not generated for these devices in this release. Table 2. Devices with Initial Information Support Arria V Device Family 5ASXB3 5ASTD3 Devices 5ASXB5 5ASTD5 Timing and Power Models Table 3 lists a summary of timing and power model status in the current version of the Quartus II software. Table 3. Devices with Timing and Power Models Device Family Device Timing Model Status Power Model Status Arria II GX All Correlated 10.0 SP1 Final 10.0 Arria II GZ All Final 10.1 Final AGXB5 Final 12.1 SP1 Preliminary 5AGXB7 Final 12.1 SP1 Preliminary 5AGTD7 Final 12.1 SP1 Preliminary 5AGXA1 Preliminary Preliminary Arria V 5AGXA3 Preliminary Preliminary 5AGXA5 Preliminary Preliminary 5AGXA7 Preliminary Preliminary 5AGXB1 Preliminary Preliminary 5AGXB3 Preliminary Preliminary 5AGTD3 Preliminary Preliminary Arria V GZ All Final 12.1 SP1 Preliminary Cyclone III LS All Final 10.0 Final 10.0 SP1 Cyclone IV E All Final 10.0 SP1 Final 10.0 SP1 EP4CGX15 Final 10.1 Final 11.0 EP4CGX22 Final 11.0 EP4CGX30 Final (1) Cyclone IV GX EP4CGX50 EP4CGX75 Final 11.0 Final 11.1 EP4CGX110 EP4CGX150 Final 10.1 Final 11.0 Cyclone V All Preliminary Preliminary HardCopy III All Correlated 11.1 Correlated 12.0

14 Timing and Power Models Page 14 Table 3. Devices with Timing and Power Models (Continued) Device Family Device Timing Model Status Power Model Status HardCopy IV E All Correlated 11.1 Correlated 12.0 HardCopy IV GX All Correlated 11.1 Correlated 12.0 MAX V All Final 11.0 Final 11.0 Stratix IV All Correlated 10.0 SP1 (2) Final SGXA7, 5SGXA5, 5SGTC5, 5SGTC7 Final 12.1 (3) Preliminary Stratix V Notes to Table 3: 5SGSD3, 5SGSD4, 5SGSD5, 5SGXA3, 5SGXA4, 5SGXB5, 5SGXB6, 5SGXAB, 5SGXA9, 5SEE9, 5SEEB, 5SGXB9, 5SGXBB Final 12.1 SP1 Preliminary 5SGSD6, 5SGSD8 Preliminary Preliminary (1) EP4CGX30BF14 and EP4CGX30CF19 are final in 11.0, EP4CGX30CF23 final in (2) The timing model is updated for PMA Direct transceiver timing in Quartus II software release (3) The timing model is updated in Quartus II software version 12.1 SP1. Refer to the Device Support Fixed section for details. The current version of the Quartus II software also includes final timing and power models for the Arria GX, Arria II GX, Cyclone, Cyclone II, Cyclone III, Cyclone III LS, Cyclone IV E, HardCopy II, MAX, MAX II, MAX IIZ, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, and Stratix IV device families. Timing models for these device families became final in the Quartus II software versions 10.1 or earlier.

15 EDA Interface Information Page 15 EDA Interface Information The Quartus II software version 12.1 SP1 supports the following EDA tools. Synthesis Tools Version NativeLink Support Mentor Graphics DK Design Suite 5.0 SP5 Mentor Graphics Precision RTL Synthesis 2012a Mentor Graphics LeonardoSpectrum 2012a Synopsys Synplify, Synplify Pro, and Synplify Premier E SP1 Simulation Tools Version NativeLink Support Aldec Active-HDL 9.1 (Windows only) Aldec Riviera-PRO Cadence NC-Sim (Linux only) Mentor Graphics ModelSim SE 10.1b Mentor Graphics ModelSim PE 10.1b Mentor Graphics QuestaSim 10.1b Mentor Graphics ModelSim-Altera 10.1b Synopsys VCS and VCS MX SP1 NativeLink Formal Verification Tools (Equivalence Checking) Version Support Cadence Encounter Conformal 8.1

16 Antivirus Verification Page 16 Antivirus Verification The Altera Complete Design Suite version 12.1 has been verified virus free using the following software: AVG Version: Virus database version: 2617/1 Software Issues Resolved McAfee VirusScan Enterprise + AntiSpyware Enterprise Version: 8.8 Scan Engine Version: DAT Version: The following Customer Service Requests were fixed or otherwise resolved in the Quartus II software version 12.1 SP1: Customer Service Request Numbers Resolved in the Quartus II Software Version 12.1 SP

17 Software Patches Included in this Release Page 17 Software Patches Included in this Release The Quartus II software version 12.1 SP1 includes the following patches released for previous versions of the Quartus II software: Quartus II Software Version Patch Customer Service Request Number Quartus II Software Version Patch Customer Service Request Number dp5g dp5e sp2 2.dp9e dp5c sp2 2.dp9d dp4b sp2 2.dp9a dp2b sp2 2.dp10h sp2 2.dp10g sp2 2.dp10f sp2 2.dp10c sp sp sp sp sp dp3b Latest Known Quartus II Software Issues For more information about known software issues, look for information on the Quartus II Software Support page at the following URL: You can find known issue information for previous versions of the Quartus II software on the Knowledge Database page at the following URL: Document Revision History Document Revision History The following table shows the revision history for this document. Date Version Changes February SP1.2 Updated the Stratix V timing model statuses in Table 3. February SP1 Initial release