Growing Solver-Aided Languages with ROSETTE

Transcription

1 Growing Solver-Aided Languages with ROSETTE Emina Torlak & Rastislav Bodik U.C. Berkeley

2 solver-aided domain-specific language Solver-aided DSL (SDSL) Noun 1. A high-level language in which partially implemented programs can be executed, verified, debugged and synthesized with the aid of a constraint solver. 2

3 programming specification assume pre(x) P(x) { } assert post(p(x)) 3

4 programming formula, input/ output pairs, traces, another program, assume pre(x) P(x) { } assert post(p(x)) 3

5 programming with a solver? assume pre(x) P(x) { } assert post(p(x)) translate( ) SAT/SMT solver 4

6 programming with a solver: code checking Is there a valid input x for which P(x) violates the spec? assume pre(x) P(x) { } assert post(p(x)) x. pre(x) post(p(x)) SAT/SMT solver CBMC [Oxford], Dafny [MSR], Jahob [EPFL], Miniatur / MemSAT [IBM], etc. 5

7 programming with a solver: code checking Is there a valid input x for which P(x) violates the spec? assume pre(x) P(x) { } assert post(p(x)) x = 42 x. pre(x) post(p(x)) SAT/SMT solver counterexample model CBMC [Oxford], Dafny [MSR], Jahob [EPFL], Miniatur / MemSAT [IBM], etc. 5

8 programming with a solver: localizing faults Given x and x, what subset of P is responsible for P(x) x? assume pre(x) P(x) { v = x + 2 } assert post(p(x)) pre(x) post(x ) x = P(x) SAT/SMT solver BugAssist [UCLA / MPI-SWS] 6

9 programming with a solver: localizing faults Given x and x, what subset of P is responsible for P(x) x? assume pre(x) P(x) { v = x + 2 } assert post(p(x)) pre(x) post(x ) x = P(x) SAT/SMT solver repair candidates MIN CORE / MAXSAT BugAssist [UCLA / MPI-SWS] 6

10 programming with a solver: angelic execution Given x, choose v at runtime so that P(x, v) satisfies the spec. assume pre(x) P(x) { v = choose() } assert post(p(x)) v. pre(x) post(p(x, v)) SAT/SMT solver Kaplan [EPFL], PBnJ [UCLA], Skalch [Berkeley], Squander [MIT], etc. 7

11 programming with a solver: angelic execution Given x, choose v at runtime so that P(x, v) satisfies the spec. assume pre(x) P(x) { v = choose() } assert post(p(x)) v = 0, v. pre(x) post(p(x, v)) SAT/SMT solver trace model Kaplan [EPFL], PBnJ [UCLA], Skalch [Berkeley], Squander [MIT], etc. 7

12 programming with a solver: synthesis Replace?? with expression e so that Pe(x) satisfies the spec on all valid inputs. assume pre(x) P(x) { v =?? } assert post(p(x)) e. x. pre(x) post(pe(x)) SAT/SMT solver Comfusy [EPFL], Sketch [Berkeley / MIT] 8

13 programming with a solver: synthesis Replace?? with expression e so that Pe(x) satisfies the spec on all valid inputs. assume pre(x) P(x) { v = x?? 2 } assert post(p(x)) e. x. pre(x) post(pe(x)) SAT/SMT solver expressions model Comfusy [EPFL], Sketch [Berkeley / MIT] 8

14 but building solver-aided languages is hard P(x) { }??? (Q x ) R(x) : Each new SDSL created by careful custom compilation to constraints, requiring years of training and experience. translate( ) translate( ) translate( ) SAT/SMT solver 9

15 a solver-aided framework for building SDSLs P(x) { }??? (Q x ) interpret( ) API( ) interpret( ) R(x) : ROSETTE Implement a library or an interpreter for your SDSL, and get a synthesizer, verifier, debugger and angelic oracle for programs in that SDSL. 10

16 a tiny solver-aided extension of racket top-level-form = general-top-level-form (#%expression expr) (module id name-id (#%plain-module-begin module-level-form...)) (begin top-level-form...) (begin-for-syntax top-level-form...) module-level-form = general-top-level-form (#%provide raw-provide-spec...) (begin-for-syntax module-level-form...) general-top-level-form = expr (define-values (id...) expr) (define-syntaxes (id...) expr) (#%require raw-require-spec...) (define-symbolic id expr) (define-symbolic* id expr) (assert expr) (solve expr) (verify expr) (debug [expr...+] expr) Racket expr = id (#%plain-lambda formals expr...+) (case-lambda (formals expr...+)...) (if expr expr expr) (begin expr...+) (begin0 expr expr...) (let-values ([(id...) expr]...) expr...+) (letrec-values ([(id...) expr]...) expr...+) (set! id expr) (quote datum) (quote-syntax datum) (with-continuation-mark expr expr expr) (#%plain-app expr...+) (#%top. id) (#%variable-reference id) (#%variable-reference (#%top. id)) (#%variable-reference) (synthesize #:forall expr #:guarantee expr) ROSETTE formals = (id...) (id...+. id) id 11

17 with a symbolic evaluator and compiler debug solve transform, evaluate & compile to constraints verify SDSL + program synthesize ROSETTE racket solver KODKOD 12

18 with a symbolic evaluator and compiler debug solve map solution to program level verify SDSL + program synthesize ROSETTE racket solver KODKOD 12

19 with a symbolic evaluator and compiler debug solve map solution to program level verify SDSL + program synthesize ROSETTE racket solver KODKOD 12

20 rosette by example: an SDSL for circuits Why a circuit language? A teaching aid An oracle for testing circuit transformations in SAT-based solvers Fa Tb Tc Td Fa Tb Tc Td spec impl Bool n Bool Bool n Bool 13

21 rosette by example: an SDSL for circuits Why a circuit language? A teaching aid An oracle for testing circuit transformations in SAT-based solvers Fa Tb Tc Td Fa Tb Tc Td spec impl verify a, b, c, d. impl(a, b, c, d) spec(a, b, c, d) 13

22 rosette by example: an SDSL for circuits Why a circuit language? A teaching aid An oracle for testing circuit transformations in SAT-based solvers F T T T F T T T spec impl F T debug 13

23 rosette by example: an SDSL for circuits Why a circuit language? A teaching aid An oracle for testing circuit transformations in SAT-based solvers Fa Tb Tc Td Fa Tb Tc Td synthesize spec impl 13

24 a tiny circuit language (tcl) in racket Warm up A classic DSL for testing and verification of circuits. a b c d a b spec verify a, b, c, d. impl(a, b, c, d) spec(a, b, c, d) c d impl 14

25 a sample tcl program #lang s-exp tcl (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define-circuit (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) A circuit is a procedure that works on boolean values. (verify-circuit AIG-parity RBC-parity) 15

26 a sample tcl program #lang s-exp tcl (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define-circuit (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) > (RBC-parity #f #f #t #f) #t > (AIG-parity #f #f #t #f) #t (verify-circuit AIG-parity RBC-parity) 15

27 a sample tcl program #lang s-exp tcl (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define-circuit (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) Reduced Boolean Circuit (, ) And Inverter Graph (, ) (verify-circuit AIG-parity RBC-parity) 15

28 a sample tcl program #lang s-exp tcl (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define-circuit (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) (verify-circuit AIG-parity RBC-parity) Verifies equivalence of two n-ary circuit functions. 15

29 a shallow embedding of tcl in racket 1 #lang racket 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) 16

30 a shallow embedding of tcl in racket 1 #lang racket 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) (define (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) 16

31 a shallow embedding of tcl in racket 1 #lang racket 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) (define (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) 7 (define (! a) (if a #f #t)) 8 (define (&& a b) (if a b #f)) 9 (define ( a b) (if a #t b)) 10 (define (<=> a b) (if a b (! b))) 16

32 a shallow embedding of tcl in racket 1 #lang racket 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) 7 (define (! a) (if a #f #t)) 8 (define (&& a b) (if a b #f)) 9 (define ( a b) (if a #t b)) 10 (define (<=> a b) (if a b (! b))) 12 (define (verify-circuit impl spec) 13 (define n (procedure-arity spec)) 14 (for ([i (expt 2 n)]) 15 (define bits (for/list ([j n]) (bitwise-bit-set? i j))) 16 (unless (eq? (apply impl bits) (apply spec bits)) 17 (error "failed on" bits)))) Naive exhaustive verifier. 16

33 a shallow embedding of tcl in racket 1 #lang racket 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) 7 (define (! a) (if a #f #t)) 8 (define (&& a b) (if a b #f)) 9 (define ( a b) (if a #t b)) 10 (define (<=> a b) (if a b (! b))) 12 (define (verify-circuit impl spec) 13 (define n (procedure-arity spec)) 14 (for ([i (expt 2 n)]) 15 (define bits (for/list ([j n]) (bitwise-bit-set? i j))) 16 (unless (eq? (apply impl bits) (apply spec bits)) 17 (error "failed on" bits)))) 19 (provide 20! && <=> define-circuit verify-circuit 21 #%datum #%app #%module-begin #%top-interaction) #lang s-exp tcl 16

34 verifying circuits with tcl #lang s-exp tcl (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define-circuit (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) j failed on (#f #f #f #f) > (RBC-parity #f #f #f #f) #f > (AIG-parity #f #f #f #f) #t (verify-circuit AIG-parity RBC-parity) 17

35 verifying circuits with tcl #lang s-exp tcl (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define-circuit (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) j failed on (#f #f #f #f) > (RBC-parity #f #f #f #f) #f > (AIG-parity #f #f #f #f) #t (verify-circuit AIG-parity RBC-parity) Where is the bug? How to fix it? Verify circuits with many inputs? 17

36 porting tcl to rosette 1 #lang racket 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) 7 (define (! a) (if a #f #t)) 8 (define (&& a b) (if a b #f)) 9 (define ( a b) (if a #t b)) 10 (define (<=> a b) (if a b (! b))) 12 (define (verify-circuit impl spec) 13 (define n (procedure-arity spec)) 14 (for ([i (expt 2 n)]) 15 (define bits (for/list ([j n]) (bitwise-bit-set? i j))) 16 (unless (eq? (apply impl bits) (apply spec bits)) 17 (error "failed on" bits)))) 19 (provide 20! && <=> define-circuit verify-circuit 21 #%datum #%app #%module-begin #%top-interaction) 18

37 porting tcl to rosette 1 #lang racket s-exp rosette 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) 7 (define (! a) (if a #f #t)) 8 (define (&& a b) (if a b #f)) 9 (define ( a b) (if a #t b)) 10 (define (<=> a b) (if a b (! b))) 12 (define (verify-circuit impl spec) 13 (define n (procedure-arity spec)) 14 (for ([i (expt 2 n)]) 15 (define bits (for/list ([j n]) (bitwise-bit-set? i j))) 16 (unless (eq? (apply impl bits) (apply spec bits)) 17 (error "failed on" bits)))) 19 (provide 20! && <=> define-circuit verify-circuit 21 #%datum #%app #%module-begin #%top-interaction) 18

38 tcl with solver-aided verification (tcl+) 1 #lang s-exp rosette 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) 7 (define (verify-circuit impl spec) 8 (define input (symbolic-input spec)) 9 (evaluate input (verify (correct impl spec input)))) 11 (define (symbolic-input spec) 12 (for/list ([i (procedure-arity spec)]) 13 (define-symbolic* b boolean?) 14 b)) 16 (define (correct impl spec input) 17 (assert (eq? (apply impl input) (apply spec input)))) 19 (provide 20! && <=> define-circuit verify-circuit 21 #%datum #%app #%module-begin #%top-interaction) 19

39 tcl with solver-aided verification (tcl+) 1 #lang s-exp rosette 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) 7 (define (verify-circuit impl spec) 8 (define input (symbolic-input spec)) 9 (evaluate input (verify (correct impl spec input)))) 11 (define (symbolic-input spec) 12 (for/list ([i (procedure-arity spec)]) 13 (define-symbolic* b boolean?) 14 b)) Creates a list of fresh symbolic boolean constants to use as input to the circuits. 16 (define (correct impl spec input) 17 (assert (eq? (apply impl input) (apply spec input)))) 19 (provide 20! && <=> define-circuit verify-circuit 21 #%datum #%app #%module-begin #%top-interaction) 19

40 tcl with solver-aided verification (tcl+) 1 #lang s-exp rosette 3 (define-syntax-rule 4 (define-circuit (id in...) expr) 5 (define (id in...) expr)) 7 (define (verify-circuit impl spec) 8 (define input (symbolic-input spec)) 9 (evaluate input (verify (correct impl spec input)))) 11 (define (symbolic-input spec) 12 (for/list ([i (procedure-arity spec)]) 13 (define-symbolic* b boolean?) 14 b)) (verify expr) searches for an interpretation of symbolic constants that causes expr to fail. 16 (define (correct impl spec input) 17 (assert (eq? (apply impl input) (apply spec input)))) 19 (provide 20! && <=> define-circuit verify-circuit 21 #%datum #%app #%module-begin #%top-interaction) 19

41 verifying circuits with tcl+ #lang s-exp tcl+ (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define-circuit (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) (#f #t #t #t) > (RBC-parity #f #t #t #t) #t > (AIG-parity #f #t #t #t) #f (verify-circuit AIG-parity RBC-parity) 20

42 debugging circuits with tcl+ (desiderata) #lang s-exp tcl+ (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define/debug (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) specification implementation (debug-circuit AIG-parity RBC-parity (#f #t #t #t)) Why does the implementation differ from the specification on this input? 21

43 extending tcl+ with solver-aided debugging 22 (require 23 rosette/lang/debug 24 rosette/lib/tools/render) 26 (define (debug-circuit impl spec input) 27 (render 28 (debug [boolean?] 29 (correct impl spec input)))) 31 (provide debug-circuit define/debug quote) (debug [t] expr) computes a minimal set of expressions of type t that are responsible for the failure in expr. 22

44 debugging circuits with tcl+ (a minimal core) #lang s-exp tcl+ (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define/debug (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (&& (! a) (! b)))) (! (&& (&& (! c) (! d)) (! (&& c d)))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) (debug-circuit AIG-parity RBC-parity (#f #t #t #t)) Non-core (grayed-out) expressions are irrelevant to the failure: there is no way to fix the behavior of AIGparity on the sample input by editing these expressions. 23

45 synthesizing circuits with tcl+ (desiderata) #lang s-exp tcl+ (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (define-circuit (AIG-parity a b c d) (&& (Circuit [! &&] a b c d #:depth 3) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) A sketch of the desired repair. (synthesize-circuit AIG-parity RBC-parity) Complete the sketch so that the given circuits are equivalent on all inputs. 24

46 extending tcl+ with solver-aided synthesis 32 (require rosette/lib/meta/meta) 34 (define (synthesize-circuit impl spec) 35 (define input (symbolic-input spec)) 36 (generate-forms 37 (synthesize #:forall input 38 #:guarantee (correct impl spec input)))) 40 (define-synthax (Circuit [op1 op2...] expr... #:depth d) 41 #:assert (>= d 0) 42 ([choose op1 identity] 43 [choose 44 expr ([choose op2...] 46 (Circuit [op1 op2...] expr... #:depth (- d 1)) 47 (Circuit [op1 op2...] expr... #:depth (- d 1)))])) (synthesize #:forall V #:guarantee expr[v, H]) searches for an interpretation of the symbolic constants H that guarantees expr will succeed for all interpretations of V. 49 (provide synthesize-circuit Circuit (for-syntax #%datum)) 25

47 extending tcl+ with solver-aided synthesis 32 (require rosette/lib/meta/meta) 34 (define (synthesize-circuit impl spec) 35 (define input (symbolic-input spec)) 36 (generate-forms 37 (synthesize #:forall input 38 #:guarantee (correct impl spec input)))) 40 (define-synthax (Circuit [op1 op2...] expr... #:depth d) 41 #:assert (>= d 0) 42 ([choose op1 identity] 43 [choose 44 expr ([choose op2...] 46 (Circuit [op1 op2...] expr... #:depth (- d 1)) 47 (Circuit [op1 op2...] expr... #:depth (- d 1)))])) 49 (provide synthesize-circuit Circuit (for-syntax #%datum)) To construct a circuit, choose a unary operator (or identity) and apply it either to one of the provided terminal expressions or to a circuit constructed using one of the given binary operators. 25

48 synthesizing circuits with tcl+ (the repair) #lang s-exp tcl+ (define-circuit (RBC-parity a b c d) (! (<=> (<=> a b) (<=> c d)))) (&& (Circuit [! &&] a b c d #:depth 3) (! (&& (&& (! (&& a b)) (! (&& (! (define-circuit (AIG-parity a b c d) (&& (! (&& (! (&& (! (&& a b)) (! (&& (! a) (! b))))) (! (&& (! (&& c d)) (! (&& (! c) (! d))))))) (! (&& (&& (! (&& a b)) (! (&& (! a) (! b)))) (&& (! (&& (! c) (! d))) (! (&& c d))))))) (synthesize-circuit AIG-parity RBC-parity) 26

49 stacking interpreters to synthesize a compiler RBC rax AIG TTL+. RBC. RBC rax(rbc) Z3 27

50 stacking interpreters to synthesize a compiler RBC rax AIG Deep SDSL embedding TTL+ Z3. RBC. RBC rax(rbc) Synthesized a rewriter from RBCs to AIGs that works for all RBCs of bounded size. 27

51 web, spatial programming, superoptimization 28

52 websynth: web scraping by demonstration Diamonds, Rihanna Sail, AWOLNATION Websynth synthesizes a scraping script given a web page and a few examples of desired data, using a declarative SDSL (XPaths). Implemented by two undergraduate students in a few weeks. 29

53 websynth: web scraping by demonstration itunes IMBDb AlAnon 30 Diamonds, Rihanna Sail, AWOLNATION synthesis time (sec) number of examples 29

54 partitioning code & data for a low power chip DB003 Evaluation Board Reference for EVB001 Instructions/Second vs Power ~100x Figure by Per Ljung GreenArrays GA144 Processor 2. Basic Architecture The purpose of this board is to facilitate evaluation and application prototyping using GreenArrays chips. Because no single I/O complement would be suitable for all likely uses, this board has two GA144 chips: One (called "Host") configured with sufficient I/O for intensive software development, and the other (called "Target") with as little I/O committed as possible so that pure, dedicated applications may be prototyped. 2.1 Highlights Three FTDI USB to serial chips provide high speed (960 kbaud) communications for interactive software development and general-purpose host communications. An onboard switching regulator takes power from the USB connectors and/or a conventional "wall wart" power supply. Whichever of these is offering the highest voltage is used by the regulator. A barrier strip provides for connection of bench power supplies. Each of the power buses of the two GA144 chips may selectively be run from external power in lieu of the onboard regulator, allowing you to run either chip from any desired VDD voltage and also facilitating current measurements. The Host chip is supplied with an SPI boot flash holding 1 MByte of nonvolatile data, an external SRAM with 1 MWord (2 MBytes) of memory; and may optionally use a dual voltage MMC card such as the 2 Gigabyte unit we have selected for in-house use. These memory resources may be used in conjunction with Virtual Machines such as eforth and polyforth, or for direct use by your own F18 code. The Target chip is committed to as few I/O connections as possible. The sources for its reset signal are fully configurable, and with the exception of a SERDES line connecting it with the Host chip, all other communications (two 2-wire serial interfaces) may be disconnected so that the chip is fully isolated and thus all practical I/O is available for any desired use. Roughly half the board is prototyping area, mainly populated with a grid of plated through holes on 0.1 inch centers. By soldering suitable headers to this grid, you can provide for expansion using various prototyping fixtures such as 30

55 partitioning code & data for a low power chip DB003 Evaluation Board Reference for EVB001 Instructions/Second vs Power ~100x GreenArrays GA144 Processor 2. Basic Architecture The purpose of this board is to facilitate evaluation and application prototyping using GreenArrays chips. Because no single I/O complement would be suitable for all likely uses, this board has two GA144 chips: One (called "Host") configured with sufficient I/O for intensive software development, and the other (called "Target") with as little I/O committed as possible so that pure, dedicated applications may be prototyped. Figure by Per Ljung Stack-based 18-bit architecture 32 instructions 8 x 18 array of asynchronous cores No shared resources (cache, memory) Limited communication, neighbors only < 300 byte memory per core 2.1 Highlights Three FTDI USB to serial chips provide high speed (960 kbaud) communications for interactive software development and general-purpose host communications. An onboard switching regulator takes power from the USB connectors and/or a conventional "wall wart" power supply. Whichever of these is offering the highest voltage is used by the regulator. A barrier strip provides for connection of bench power supplies. Each of the power buses of the two GA144 chips may selectively be run from external power in lieu of the onboard regulator, allowing you to run either chip from any desired VDD voltage and also facilitating current measurements. The Host chip is supplied with an SPI boot flash holding 1 MByte of nonvolatile data, an external SRAM with 1 MWord (2 MBytes) of memory; and may optionally use a dual voltage MMC card such as the 2 Gigabyte unit we have selected for in-house use. These memory resources may be used in conjunction with Virtual Machines such as eforth and polyforth, or for direct use by your own F18 code. The Target chip is committed to as few I/O connections as possible. The sources for its reset signal are fully configurable, and with the exception of a SERDES line connecting it with the Host chip, all other communications (two 2-wire serial interfaces) may be disconnected so that the chip is fully isolated and thus all practical I/O is available for any desired use. Roughly half the board is prototyping area, mainly populated with a grid of plated through holes on 0.1 inch centers. By soldering suitable headers to this grid, you can provide for expansion using various prototyping fixtures such as 30

56 partitioning code & data for a low power chip DB003 Evaluation Board Reference for EVB001 Instructions/Second vs Power ~100x GreenArrays GA144 Processor 2. Basic Architecture The purpose of this board is to facilitate evaluation and application prototyping using GreenArrays chips. Because no single I/O complement would be suitable for all likely uses, this board has two GA144 chips: One (called "Host") configured with sufficient I/O for intensive software development, and the other (called "Target") with as little I/O committed as possible so that pure, dedicated applications may be prototyped. Figure by Per Ljung Stack-based 18-bit architecture 32 instructions 8 x 18 array of asynchronous cores No shared resources (cache, memory) Limited communication, neighbors only < 300 byte memory per core 2.1 Highlights Three FTDI USB to serial chips provide high speed (960 kbaud) communications for interactive software development and general-purpose host communications. Whichever of these is offering the highest voltage is used by the regulator. Manual function partitioning: barrier strip provides for connection of bench power supplies. Each of the power buses of the two GA144 chips may break functions up into aaselectively pipeline be run from external power in lieu of the onboard regulator, allowing you to run either chip from any desired V voltage and also facilitating current measurements. with a few operations perthe Host core. chip is supplied with an SPI boot flash holding 1 MByte of nonvolatile data, an external SRAM with 1 MWord An onboard switching regulator takes power from the USB connectors and/or a conventional "wall wart" power supply. DD (2 MBytes) of memory; and may optionally use a dual voltage MMC card such as the 2 Gigabyte unit we have selected for in-house use. These memory resources may be used in conjunction with Virtual Machines such as eforth and polyforth, or for direct use by your own F18 code. The Target chip is committed to as few I/O connections as possible. The sources for its reset signal are fully configurable, and with the exception of a SERDES connectingphothilimthana it with the Host chip, all other communications (two Drawing bylinemangpo 2-wire serial interfaces) may be disconnected so that the chip is fully isolated and thus all practical I/O is available for any desired use. Roughly half the board is prototyping area, mainly populated with a grid of plated through holes on 0.1 inch centers. By soldering suitable headers to this grid, you can provide for expansion using various prototyping fixtures such as 30

57 partitioning code & data for a low power chip high-level program per-core high-level programs per-core optimized machine code partitioner code generator new programming model new approach using synthesis Mangpo Phothilimthana Nishant Totla 31

58 partitioning code & data for a low power chip high-level program per-core high-level programs per-core optimized machine code partitioner code generator new programming model new approach using synthesis Mangpo Phothilimthana Nishant Totla 31

59 partitioning code & data for a low power chip one iteration of MD5 hash optimal code partitioning (synthesized in 5 min) 256-byte mem per core initial data placement specified M i K i R i high R M F 105 <<< 106 K low 2 3 M F 4 5 <<< 6 K 32

60 component-based synthesis of loop free code (define-fragment (fast-max x y) #:ensures (lambda (x y result) (= result (if (> x y) x y))) 1000 completed timeout #:library (bvlib [{bvneg bvge bvand} 1] [{bvxor} 2])) Gulwani et al. PLDI 11 synthesis time (sec) (define (fast-max x y) (let* ([t1 (bvge x y]) [t2 (bvneg t1]) [t3 (bvxor y x]) [t4 (bvand t3 t2]) [t5 (bvxor y t4)]) t5)) 1 Hacker s Delight benchmarks 33

61 34

62 ROSETTE {emina, 34