23. Digital Baseband Design

Transcription

1 23. Digital Baseband Design Algorithm-to-VLSI Circuit Refinement (Floating Point) Tradeoff (SNR Loss, BER) (Fixed Point) VHDL, Verilog VHDL, Verilog Memory Control For I=0 to I=15 Sum = Sum + array[i] Behavioral Level Behavioral Synthesis Architectural Synthesis RTL Synthesis Architectural Level + 0 State Gate Level Circuit Synthesis Layout Synthesis Circuit & Layout Level Vdd Clk Gnd 2 C

2 Digital Baseband: Design & Verification Challenges Does my algoritm work? Does my algorithm work at certain bit data width? (Assess fixed point aspects) Refine the algorithm to improve the hardware implementation? How to capture the algorithm in a design environment (Software test bench and IP environments, Hardware verification engine, Description language,...)? Does the captured algorithm still working? How can I model the external world to stimulate my design? How do I know that I have exercised my entire design? How can I debug the software realization before developing the hardware? 3 Floating Point to Fixed Point Number Representation Translation floating point to fixed point number representation rests upon a tradeoff performance loss vs. bitwidth Simulation of quantization effects Gain Floating Point E.g. Constraint Gain loss < 0.5 db 4 bits 8 bits Input Parameter 4

3 Behavioral or High-Level Synthesis The fixed-point model can be can be captured as a behavioral model by using a hardware description language like VHDL or Verilog Behavioral Synthesis = Translation behavioral description (Register Transfer Level) description structural or RTL 1. Ressoure allocation 2. Scheduling (! Introduction of timing infornation!) 3. Ressource assignment TOOLS: SYNOPSYS Behavioral Compiler, Virtual Artist 5 Algorithm-to-VLSI Circuit Refinement (Floating Point) Tradeoff (SNR Loss, BER) (Fixed Point) Untimed VHDL, Verilog VHDL, Verilog Memory Control For I=0 to I=15 Sum = Sum + array[i] Behavioral Level Behavioral Synthesis Architectural Synthesis RTL Synthesis Architectural Level + 0 State Gate Level Circuit Synthesis Layout Synthesis Circuit & Layout Level Vdd Clocked Clk Gnd 6 C

4 Behavioral or High-Level Synthesis (cont d) Algorithm For i = 0 ; i = 15 0% technology dependent sum = sum + data[i] Mapping onto a technology Architecture (e.g. 10% technology dependent) Data[0] Data[15] i or Data[0] Data[15] Untimed Sum Sum Behavioral Synthesis Register level (e.g. 20% technology dependent) Clear address Clock MEM Clear sum Clocked 7 Low Power Design Power consumption in a digital CMOS circuit: P α.c eff.v 2 dd. f clk Power reduction at different levels - Logic level: Gated clocked, avoiding hazard generation, FSM encoding for low power - Architectural level: Parallelization, pipelining 8

5 Low Power Design Simple example: 4 bit counter Conventional counters are binary coded: A maximum of 4 bits change at the same time High power consumption Alternative: Gray-code the numbers: Only one one bit changes per clock cycle Reduced power consumption 9 Binary Counter Schematic Avarage Power Consumption: 102µW@20MHz 10

6 Gray-Counter Schematic Avarage Power Consumption: 11 Low Power 4 Bit Counter: Results By using Gray-coding instead of binary coding the power consumption of the 4 bit counter has been reduced to: 76µ W 102µ W = 75% 12