The Definitive Guide to ARM Ò Cortex Ò -M3 and Cortex-M4 Processors

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2 The Definitive Guide to ARM Ò Cortex Ò -M3 and Cortex-M4 Processors

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4 The Definitive Guide to ARM Ò Cortex Ò -M3 and Cortex-M4 Processors Third Edition Joseph Yiu ARM Ltd., Cambridge, UK AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO Newnes is an imprint of Elsevier

5 Newnes is an imprint of Elsevier The Boulevard, Langford Lane, Kidlington, Oxford OX5 1GB, UK 225 Wyman Street, Waltham, MA 02451, USA Copyright Ó 2014 Elsevier Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means electronic, mechanical, photocopying, recording or otherwise without the prior written permission of the publisher Permissions may be sought directly from Elsevier s Science & Technology Rights Department in Oxford, UK: phone (+44) (0) ; fax (+44) (0) ; permissions@elsevier.com. Alternatively you can submit your request online by visiting the Elsevier web site at and selecting Obtaining permission to use Elsevier material Notice No responsibility is assumed by the publisher for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions or ideas contained in the material herein. Because of rapid advances in the medical sciences, in particular, independent verification of diagnoses and drug dosages should be made British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the Library of Congress ISBNe13: For information on all Newnes publications visit our website at Printed and bound in the United States

6 Contents Foreword...xxi Preface... xxiii Synopsis...xxv About this Book... xxvii Contributor Bio-Paul Beckmann...xxix Acknowledgments...xxxi Terms and Abbreviations... xxxiii Conventions...xxxv CHAPTER 1 Introduction to ARM Ò Cortex Ò -M Processors What are the ARM Ò Cortex Ò -M processors? The Cortex Ò -M3 and Cortex-M4 processors The Cortex Ò -M processor family Differences between a processor and a microcontroller ARM Ò and the microcontroller vendors Selecting Cortex Ò -M3 and Cortex-M4 microcontrollers Advantages of the Cortex Ò -M processors Low power Performance Energy efficiency Code density Interrupts Ease of use, C friendly Scalability Debug features OS support Versatile system features Software portability and reusability Choices (devices, tools, OS, etc.) Applications of the ARM Ò Cortex Ò -M processors Resources for using ARM Ò processors and ARM microcontrollers What can you find on the ARM Ò website Documentation from the microcontroller vendors Documentation from tools vendors Other resources Background and history A brief history of ARM Ò ARM Ò processor evolution Architecture versions and Thumb Ò ISA...18 v

7 vi Contents Processor naming About the ARM Ò ecosystem...23 CHAPTER 2 Introduction to Embedded Software Development What are inside typical ARM Ò microcontrollers? What you need to start Development suites Development boards Debug adaptor Software device driver Examples Documentation and other resources Other equipment Software development flow Compiling your applications Software flow Polling Interrupt driven Multi-tasking systems Data types in C programming Inputs, outputs, and peripherals accesses Microcontroller interfaces The Cortex Ò microcontroller software interface standard (CMSIS) Introduction of CMSIS Areas of standardization in CMSIS-Core Organization of CMSIS-Core How do I use CMSIS-Core? Benefits of CMSIS-Core Various versions of CMSIS...54 CHAPTER 3 Technical Overview General information about the Cortex Ò -M3 and Cortex-M4 processors Processor type Processor architecture Instruction set Block diagram Memory system Interrupt and exception support Features of the Cortex Ò -M3 and Cortex-M4 processors Performance Code density...65

8 Contents vii Low power Memory system Memory protection unit Interrupt handling OS support and system level features Cortex Ò -M4 specific features Ease of use Debug support Scalability Compatibility...73 CHAPTER 4 Architecture Introduction to the architecture Programmer s model Operation modes and states Registers Special registers Floating point registers Behavior of the application program status register (APSR) Integer status flags Q status flag GE bits Memory system Memory system features Memory map Stack memory Memory protection unit (MPU) Exceptions and interrupts What are exceptions? Nested vectored interrupt controller (NVIC) Vector table Fault handling System control block (SCB) Debug Reset and reset sequence CHAPTER 5 Instruction Set Background to the instruction set in ARM Ò Cortex Ò -M processors Comparison of the instruction set in ARM Ò Cortex Ò -M processors Understanding the assembly language syntax Use of a suffix in instructions...128

9 viii Contents 5.5. Unified assembly language (UAL) Instruction set Moving data within the processor Memory access instructions Arithmetic operations Logic operations Shift and rotate instructions Data conversion operations (extend and reverse ordering) Bit-field processing instructions Compare and test Program flow control Saturation operations Exception-related instructions Sleep mode-related instructions Memory barrier instructions Other instructions Unsupported instructions Cortex Ò -M4-specific instructions Overview of enhanced DSP extension in Cortex-M SIMD and saturating instructions Multiply and MAC instructions Packing and unpacking Floating point instructions Barrel shifter Accessing special instructions and special registers in programming Overview Intrinsic functions Inline assembler and embedded assembler Using other compiler-specific features Access of special registers CHAPTER 6 Memory System Overview of memory system features Memory map Connecting the processor to memory and peripherals Memory requirements Memory endianness Data alignment and unaligned data access support Bit-band operations Overview Advantages of bit-band operations...210

10 Contents ix Bit-band operation of different data sizes Bit-band operations in C programs Default memory access permissions Memory access attributes Exclusive accesses Memory barriers Memory system in a microcontroller CHAPTER 7 Exceptions and Interrupts Overview of exceptions and interrupts Exception types Overview of interrupt management Definitions of priority Vector table and vector table relocation Interrupt inputs and pending behaviors Exception sequence overview Acceptance of exception request Exception entrance sequence Exception handler execution Exception return Details of NVIC registers for interrupt control Summary Interrupt enable registers Interrupt set pending and clear pending Active status Priority level Software trigger interrupt register Interrupt controller type register Details of SCB registers for exception and interrupt control Summary of the SCB registers Interrupt control and state register (ICSR) Vector table offset register (VTOR) Application interrupt and reset control register (AIRCR) System handler priority registers (SCB->SHP[0 to 11]) System handler control and state register (SCB->SHCSR) Details of special registers for exception or interrupt masking PRIMASK FAULTMASK BASEPRI...267

11 x Contents Example procedures in setting up interrupts Simple cases With vector table relocation Software interrupts Tips and hints CHAPTER 8 Exception Handling in Detail Introduction About this chapter Exception handler in C Stack frames EXC_RETURN Exception sequences Exception entrance and stacking Exception return and unstacking Interrupt latency and exception handling optimization What is interrupt latency? Interrupts at multiple-cycle instructions Tail chaining Late arrival Pop preemption Lazy stacking CHAPTER 9 Low Power and System Control Features Low power designs What does low power mean in microcontrollers? Low power system requirements Low power characteristics of the Cortex Ò -M3 and Cortex-M4 processors Low power features Sleep modes System control register (SCR) Entering sleep modes Wake-up conditions Sleep-on-Exit feature Send event on pend (SEVONPEND) Sleep extension/wake-up delay Wake-up interrupt controller (WIC) Event communication interface Using WFI and WFE instructions in programming When to use WFI Using WFE...308

12 Contents xi 9.4. Developing low power applications Reducing the active power Reduction of active cycles Sleep mode current reduction The SysTick timer Why have a SysTick timer Operations of the SysTick timer Using the SysTick timer Other considerations Self-reset CPU ID base register Configuration control register Overview of CCR STKALIGN bit BFHFNMIGN bit DIV_0_TRP bit UNALIGN_TRP bit USERSETMPEND bit NONBASETHRDENA bit Auxiliary control register Co-processor access control register CHAPTER 10 OS Support Features Overview of OS support features Shadowed stack pointer SVC exception PendSV exception Context switching in action Exclusive accesses and embedded OS CHAPTER 11 Memory Protection Unit (MPU) Overview of the MPU About the MPU Using the MPU MPU registers MPU type register MPU control register MPU region number register MPU region base address register MPU region base attribute and size register MPU alias registers Setting up the MPU Memory barrier and MPU configuration...373

13 xii Contents Using sub-region disable Allow efficient memory separation Reduce the total number of regions needed Considerations when using MPU Program code Data memory Peripherals Other usages of the MPU Comparing with the MPU in the Cortex Ò -M0þ processor CHAPTER 12 Fault Exceptions and Fault Handling Overview of fault exceptions Causes of faults Memory management (MemManage) faults Bus faults Usage faults HardFaults Enabling fault handlers MemManage fault Bus fault Usage fault HardFault Fault status registers and fault address registers Summary Information for MemManage fault Information for bus fault Information for usage fault HardFault status register Debug fault status register (DFSR) Fault address registers MMFAR and BFAR Auxiliary fault status register Analyzing faults Faults related to exception handling Stacking Unstacking Lazy stacking Vector fetches Invalid returns Priority levels and stacking or unstacking faults Lockup What is lockup? Avoiding lockup...400

14 Contents xiii Fault handlers HardFault handler for debug purpose Fault mask Additional information Running a system with two stacks Detect stack overflow CHAPTER 13 Floating Point Operations About floating point data Introduction Single-precision floating point numbers Half-precision floating point numbers Double-precision floating point numbers Floating point support in Cortex Ò -M processors Cortex Ò -M4 floating point unit (FPU) Floating point unit overview Floating point registers overview CPACR register Floating point register bank Floating point status and control register (FPSCR) Floating point context control register (FPU->FPCCR) Floating point context address register (FPU->FPCAR) Floating point default status control register (FPU-> FPDSCR) Media and floating point feature registers (FPU->MVFR0, FPU->MVFR1) Lazy stacking in detail Key elements of the lazy stacking feature Scenario #1: No floating point context in interrupted task Scenario #2: Floating point context in interrupted task but not in ISR Scenario #3: Floating point context in interrupted task and in ISR Scenario #4: Nested interrupt with floating point context in the second handler Scenario #5: Nested interrupt with floating point context in the both handlers Interrupt of lazy stacking Interrupt of floating point instructions...431

15 xiv Contents Using the floating point unit Floating point support in CMSIS-Core Floating point programming in C Compiler command line options ABI Options: Hard-vfp and Soft-vfp Special FPU modes Floating point exceptions Hints and tips Run-time libraries for microcontrollers Debug operation CHAPTER 14 Introduction to the Debug and Trace Features Debug and trace features overview What are debug features? What are trace features? Debug and trace features summaries Debug architecture CoreSight Ô debug architecture Processor debug interface Debug Port (DP), Access Port (AP), and Debug Access Port (DAP) Trace interface CoreSight characteristics Debug modes Debug events Breakpoint feature Debug components introduction Processor debug support Flash patch and breakpoint (FPB) unit Data watchpoint and trace (DWT) unit Instrumentation trace macrocell (ITM) Embedded trace macrocell (ETM) Trace port interface unit (TPIU) ROM table AHB access port (AHB-AP) Debug operations Debug connection Flash programming Breakpoints CHAPTER 15 Getting Started with Keil Microcontroller Development Kit for ARM Ò Overview Typical program compilation flow...488

16 Contents xv Getting started with mvision Project options Device option Target options Output options Listing options User options C/Cþþ options Assembler options Linker options Debug options Utilities options Using the IDE and the debugger Using the instruction set simulator Running programs from SRAM Optimization options Other hints and tips Stack and heap memory size configurations Other information CHAPTER 16 Getting Started with the IAR Embedded Workbench for ARM Ò Overview of the IAR embedded workbench for ARM Ò Typical program compilation flow Creating a simple blinky project Project options Hints and tips CHAPTER 17 Getting Started with the GNU Compiler Collection (gcc) The GNU Compiler Collection (gcc) toolchain Typical development flow Creating a simple blinky project Overview of the command line options Flash programming Using Keil MDK-ARM Using third-party flash programming utilities Using Keil Ô MDK-ARM with GNU tools for ARM Embedded Processors Using CoIDE with GNU tools for ARM Ò Embedded Processors Commercial gcc-based development suites Atollic TrueSTUDIO for ARM Ò Red Suite CrossWorks for ARM Ò...582

17 xvi Contents CHAPTER 18 Input and Output Software Examples Producing outputs Re-targeting to the Instrumentation Trace Macrocell (ITM) Overview Keil Ô MDK-ARM IAR Embedded Workbench GCC Semi-hosting Re-targeting to peripherals CHAPTER 19 Using Embedded Operating Systems Introduction to embedded OSs What are embedded OSs? When to use an embedded OS Role of CMSIS-RTOS Keil Ô RTX Real-Time Kernel About RTX Features overview RTX and CMSIS-RTOS Thread CMSIS-OS examples Simple CMSIS-RTOS with two threads Inter-thread communciation overview Signal event communication Mutual Exclusive (Mutex) Semaphore Message queue Mail queue Memory pool management feature Generic wait function and time-out value Timer feature Access privileged devices OS-aware debugging Troubleshooting Stack size and stack alignment Privileged level Miscellaneous CHAPTER 20 Assembly and Mixed Language Projects Use of assembly code in projects Interaction between C and assembly Structure of an assembly function Examples...652

18 Contents xvii Simple example with ARM Ò toolchains (Keil Ô MDK-ARM, DS-5) Simple example with GNU tools for ARM-embedded processors Accessing special registers Data memory Hello world Displaying values in hexadecimal and decimal NVIC interrupt control Unsigned integer square root Mixed language projects Calling a C function from assembly Calling an assembly function from C Embedded assembler (Keil Ô MDK-ARM/ARM Ò DS-5 Ô professional) Inline assembler Intrinsic functions Idiom recognition CHAPTER 21 ARM Ò Cortex Ò -M4 and DSP Applications DSP on a microcontroller? Dot product example Architecture of a traditional DSP processor Cortex Ò -M4 DSP instructions Registers and data types Fractional arithmetic SIMD data Load and store instructions Arithmetic instructions General Cortex Ò -M4 optimization strategies Instruction limitations Writing optimized DSP code for the Cortex Ò -M Biquad filter Fast Fourier transform FIR filter CHAPTER 22 Using the ARM Ò CMSIS-DSP Library Overview of the library Pre-built binaries Function naming convention Getting help Example 1 e DTMF demodulation Generating the sine wave...720

19 xviii Contents Decoding using an FIR filter Decoding using an FFT Decoding using a Biquad filter Example DTMF code Example 2 e least squares motion tracking Example least squares code CHAPTER 23 Advanced Topics Decisions and branches Conditional branches Complex decision tree Performance considerations Double-word stack alignment Various methods for semaphore implementation Using SVC services for semaphores Use bit-band for semaphores Non-base Thread enable Re-entrant Interrupt Handler Bit Data Handling in C Startup code Stack overflow detection Stack analysis by toolchain Stack analysis by trial Stack overflow detection by stack placement Using MPU Using DWT and Debug Monitor Exception Stack checking in OS context switching Flash patch feature Revision versions of the Cortex Ò -M3 and Cortex-M4 processors Overview Changes from Cortex Ò -M3 r0p0 to r1p0/r1p Changes from Cortex Ò -M3 r1p1 to r2p Changes from Cortex Ò -M3 r2p0 to r2p Changes from Cortex Ò -M4 r0p0 to r0p CHAPTER 24 Software Porting Overview Porting software from 8-bit/16-bit MCUs to Cortex Ò -M MCUs Architectural differences Common modifications Memory size requirements...775

20 Contents xix Non-applicable optimizations for 8-bit or 16-bit microcontrollers Example e migrate from 8051 to ARM Ò Cortex Ò -M Porting software from ARM7TDMI Ô to Cortex Ò -M3/M Overview of the hardware differences Assembly language files C language files Pre-compiled object files and libraries Optimization Porting software between different Cortex Ò -M processors Differences between different Cortex Ò -M processors Required software changes Embedded OS Creating portable program code for the Cortex Ò -M processors References Index Appendices AeI are available on the book s companion website