Designing, developing, debugging ARM Cortex-A and Cortex-M heterogeneous multi-processor systems

Transcription

1 Designing, developing, debugging ARM and heterogeneous multi-processor systems Kinjal Dave Senior Product Manager, ARM ARM Tech Symposia India December 7 th 2016

2 Topics Introduction System design Software 2

3 Topics Introduction System design Why heterogeneous processing? Use cases Terminology Software 3

4 Modern compute systems have diverse workloads Power Time Ambient mode Interactive mode Sleep mode 4

5 Diversity of workloads across markets 5

6 Why heterogeneous computing? Increase system performance Increase system efficiency Reduce system cost Right-sized processing 6

7 ARM architecture for diverse computing needs Highest performance Optimized for rich operating systems Cortex-R Fast response Optimized for high performance, hard real-time applications Smallest/ lowest power Optimized for discrete processing and microcontrollers 7

8 Heterogeneous systems are extremely diverse CPU GPU ISP Video Interconnect Display Audio DSP DDR MCU A heterogeneous system using different compute elements A heterogeneous using ARM Cortex processors 8

9 Heterogeneous multicore processors Multicore Homogeneous Heterogeneous Same ISA Same microarchitecture Same view of memory Performance asymmetry Same ISA Different microarchitecture Same view of memory OS/ Software symmetry Functional asymmetry Different ISA Different microarchitecture Different view of memory OS/ Software asymmetry + systems Interconnect Interconnect Interconnect 9

10 Use cases of HMP systems Mobile Wearables ADAS Rich OS, high performance Cortex-R Modem Real-time control System control, sensor fusion Sensor fusion System control 10

11 Use cases of HMP systems in embedded Industrial Consumer Medical Rich UI and OS, high performance Real-time control and monitoring Deterministic sensor control Real-time monitoring 11

12 Topics Introduction System design considerations Security models System design Software ARM activities 12

13 Architectural differences between Cortex families Cortex-R Higher performance Lower power, smaller area Operating system Rich OS/ RTOS RTOS only Instruction set 32/64-bit ARM &Thumb ISA 32-bit ARM &Thumb ISA Thumb ISA Interrupts SW-managed interrupts Deterministic SW-managed HW-managed interrupt Bus interface AMBA AXI AMBA AXI AMBA AHB/AXI 13

14 System design considerations How to address the memory map differences? Generic HMP compute using Cortex processors How to distribute interrupts? How to handle inter-processor communication? Shared L2 Cortex-R AHB interconnect Local memory How to handle Secure/Non-secure state communication? DMC Interconnect AHB interconnect DDR Sensor Timer SRAM 14

15 Addressing different memory address spaces option one: low area cost Sharing a common address space Peripherals grouped together in a system CPU cluster AXI interconnect AHB interconnect Restrictive approach DMC AHB interconnect Private memory and peripherals Requires design-time decision Sensor Timer SRAM 15

16 Addressing different memory address spaces option two: more flexibility Use a System Memory Management Unit (SMMU) SMMU benefits Moveable window full system access Adds security attribute to transactions Run time configurable by software CPU cluster DMC AXI interconnect SMMU AHB interconnect AXI /AHB interconnect Local memory and peripherals Modular design enables silicon cost sharing across different masters DDR Sensor Timer SRAM 16

17 Interrupts in Cortex processors /Cortex-R processors use GIC architecture processors include NVIC Interrupt sources GIC Interrupt sources WIC (optional) Wake up request to power management unit CPU2 CPU2 CPU2 CPU2 NVIC Shared L2 cache / Cortex-R CPU cluster processor 17

18 Sharing interrupts Option one: Wired interrupts Option two: Interrupt distribution HW Interrupt sources Interrupt sources Interrupt distribution unit GIC WIC GIC IRQ Mailbox (IPC) IRQ WIC processor NVIC processor processor Buses NVIC processor Interrupt must be enabled in only one controller Interrupt requests distributed by hardware. Optional software level interrupt passing by messaging/mail box 18

19 TrustZone security using processors ARMv6-M and ARMv7-M processors Always Secure or always Non-secure Use case dependent Shared L2 AHB interconnect Local memory Always Secure (secure boot) Power control System Control Processor (SCP) Designer needs to be careful Interconnect Power management Secure access only Debug system needs to match security domain for each processor DMC DDR AHB interconnect Local memory Always Non-secure Audio interface Audio 19

20 TrustZone for ARMv8-M: More flexibility for designers processor Non-secure processor (ARMv8-M) Non-secure Shared L2 Secure/ Non-secure AHB interconnect Local memory Smart DMA engine Interconnect Secure Secure Shared secure world (e.g. as a smart DMA engine) DMC DDR AHB interconnect Local memory Audio interface Audio 20

21 Topics Introduction Overview of software challenges Making software development easier System design Software 21

22 Overview of software challenges Task partitioning Data sharing Developer productivity How to optimally partition tasks? Is coherency necessary? Usability, portability, debugging 22

23 Task partitioning: Separate memory systems Sensor fusion can be on the same chip or off chip Allows separate chip development Wake up app processor only when certain event is detected App processor system processor Sensor fusion processor Sensors Pros Easier design and software development Subsystems on different process nodes Cons Communication link can become the bottleneck Limited data set size in SRAM Memory SRAM 23

24 Task partitioning: Locally shared memory Shared SRAM Sharing sensor data and results App processor Sensor fusion Pros Program code for can be transferred by system can access data / results from Semaphores in shared memory Cons Limited data set size in SRAM Slower access of data by from SRAM processor Memory Bus bridge processor Shared SRAM Always on Sensors 24

25 Task partitioning: Shared main memory Use parts of main memory as shared memory App processor Sensor fusion Pros Allows larger data set for sensor fusion processors can access sensor data quickly Utilize ARM NEON for signal processing Semaphores in shared memory processor Bus bridge processor Sensors Cons Main memory system and part of the main interconnect need to be awake more often Frequency of data transfer between two s Shared memory SRAM Always on 25

26 Standardization of software interfaces CMSIS adopting OpenAMP remoteproc Cortex Microcontroller Software Interface Standard (CMSIS) Now open source on Github Rich OS/ RTOS RPMsg RTOS OS support for HMP systems Remote Processor Messaging (RPMsg) for inter-processor communication Management framework using remoteproc processor Memory processor SRAM 26

27 Debug Linux and RTOS apps from a single tool Debug : The application JTAG The Linux kernel CoreSight The Linux application TCP/IP Linux kernel Linux application RTOS system Microcontroller application DS-MDK debugger enables complete visibility to all software applications in the heterogeneous system 27

28 Performance tuning for HMP systems Quickly discover hot spots of your application Simplifies efficient task partitioning on your system System-wide views as bottlenecks are often outside the CPU 28

29 Summary You can build heterogeneous multicore systems today using different Cortex processors and other system IP ARM architecture enhancements make future HMP systems better System and software considerations required in the context of use cases ARM is working on several activities to make HMP easier 29

30 The trademarks featured in this presentation are registered and/or unregistered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. Copyright 2016 ARM Limited