Digital Design using HDLs EE 4755 Midterm Examination
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1 Name Digital Design using HDLs EE 4755 Midterm Examination Monday, 16 October 217 9:3 1:2 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Exam Total (2 pts) (2 pts) (2 pts) (15 pts) (1 pts) (15 pts) (1 pts) Good Luck!
2 Problem 1: [2 pts] Write a Verilog description of the hardware illustrated below. The description must include the modules and instantiations as illustrated. The description can be behavioral or structural, but it must be synthesizable. a 2 b 2 ci a[] b[] a b ci bf BFA_fast co sum a[1] b[1] a b ci tba bf1 BFA_fast co sum lsb msb sum 3 Verilog corresponding to illustrated hardware. Show instantiations, Verilog for instantiated module(s), and all module ports. 2
3 Problem 2: [2 pts] Appearing below is a partially completed recursive description of an n = 2 b -input, w-bit multiplexor, which is a generalized version of the multiplexors appearing in Homework 1. Complete it. Fill in the condition and code for the terminating case. Complete recursive case, including the instantiation port and parameter connections (look for FILL IN). module muxn #( int w = 5, int b = 4, int n = 1 << b ) ( output uwire [w-1:] x, input uwire [b-1:] sel, input uwire [w-1:] a[:n-1] ); if ( ) // Terminating Case Condition <---- FILL IN begin // Terminating Case end else begin // Recursive Case uwire [w-1:] y[2]; // Instantiate two n/2-input muxen, and connect each to half the inputs. // // <---- FILL IN muxn #(.w( ),.b( ) ) mlo( y[], sel[b-2:], a[ : n/2-1 ] ); // <---- FILL IN muxn #(.w( ),.b( ) ) mhi( y[1], sel[ ], a[ n/2 : n-1 ] ); // Instantiate one 2-input mux. // // <---- FILL IN muxn #(.w( ),.b( ) ) m2( ) end 3
4 Problem 3: [2 pts] Appearing below to the right is an 8-input multiplexor constructed from 2-input multiplexors using the technique from Homework 1 and from the previous problem. Call a multiplexor constructed this way a tree mux. Appearing below to the left is a diagram showing a flat mux, the kind usually used in class. The flat mux diagram shows a timing analysis based on the simple model, and some details about cost. For reference: b 1 i= a2i = a(2 b 1). Assume that n is a power of 2. s a w a1 w w s[lg(n)-1] a(n-1) mux n, w One decode AND per input (n total). s[1] s[] s= s=1 lg lg n s=n-1 w gate ANDs per input (nw total). 1 w OR gates lg n (lg lg n) lg n x select a a1 a2 a3 a4 : 1:1 2:2 x (a) Compute the cost of an n-input, w-bit flat mux using the simple model and without optimization. Cost of flat mux in terms of n and w. a5 a6 a7 (b) Compute the cost of an n-input, w-bit tree mux using the simple model. Cost of tree mux in terms of n and w. Describe assumptions made about 2-input mux implementation. (c) Compute the delay of an n-input, w-bit tree mux using the simple model. Delay of tree mux in terms of n and w. 4
5 Problem 4: [15 pts] Show the hardware that will be synthesized for the modules below. (a) Show the hardware that will be inferred for the module below, including the minimum number of bits in each wire. Assume that sqrt is defined in a library somewhere. module wqf #( int w = 16 ) ( output logic signed [2*w-1:] rad, output uwire [31:] srad, input uwire [w-1:] a, b, c ); sqrt #(32,2*w) s1(srad,rad); always_comb begin end rad = b*b - 4 * a * c; if ( rad < ) rad = ; Show inferred hardware. Show minimum correct bit widths. (b) Show the hardware that will be inferred for the module below. module sort2 #( int w = 4 ) ( output logic [w-1:] x[2], input uwire [w-1:] a[2] ); always_comb begin end for ( int i=; i<2; i++ ) x[i] = a[i]; if ( a[] < a[1] ) begin x[] = a[1]; x[1] = a[]; end Show inferred hardware. 5
6 Problem 5: [1 pts] Answer each question below. (a) The mux2 module below uses implicit structural code. Modify it so that it uses behavioral (procedural) code. module mux2 #( int w = 16 ) ( output uwire [w-1:] x, input uwire s, input uwire [w-1:] a,b ); assign x = s ==? a : b; Modify so that is procedural. Change ports if necessary. (b) Modify the module port and parameter declarations below so that the Verilog is correct. Do not modify the contents of the module itself. Note that opt is not defined, but that it should be. Note: In the original exam assign was omitted from the module body, making the problem impossible to solve. module sum_or_dff #( int w = 16 ) ( output uwire [w-1:] x, input uwire [w-1:] a, b ); if ( opt == ) assign x = a+b; else assign x = a-b; Modify port and parameter declarations for correctness. 6
7 Problem 6: [15 pts] Answer each question below. (a) Why is always_comb preferred over x or y or.. ) when describing combinational logic? always comb preferred because... What is the risk with x or y or.. )? (b) Describe what the technology mapping step of synthesis is, and the kind of optimizations that need to be performed after technology mapping. Technology mapping is: Optimizations that must be performed after technology mapping: (c) The module below adds a real and an integer and assigns the sum (in real format) to its output. It is valid Verilog but is not synthesizable by Owr EDA software. So, you call Owr EDA and ask, why not?. They answer, because it is impossible to add an integer to a real. Is that the real reason? Explain. module plusri (output real sum, input real a, input [2:] x); assign sum = a + x; Reason a+x not synthesizable by Owr EDA software: 7
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