ECE 468, Fall Midterm 2

Transcription

1 ECE 468, Fall 08. Midterm INSTRUCTIONS (read carefully) Fill in your name and PUID. NAME: PUID: Please sign the following: I affirm that the answers given on this test are mine and mine alone. I did not receive help from any person or material (other than those eplicitly allowed). There are 5 problems. Make sure you have a complete eam. The point value of each problem is indicated net to the problem, as well as in the table below. Points may be deducted for solutions which are correct but ecessively complicated, hard to understand, or poorly eplained. Please keep your solutions short and crisp. The I DON T KNOW rule: if you do not know the answer to a problem, you can simply write I DON T KNOW and you will get 0% of credit for that problem. The number of points you get in this manner cannot eceed 0 points across the whole eam. It is wise to skim all problems and point values first, to best plan your time. This is an open book, open note eam. Use the back of sheets if necessary. See the proctor if you need more paper. Please bring any apparent bugs to the attention of the proctors. After the midterm is over, discuss its contents with other ECE 468 students only after verifying that they have also taken the eam (e.g. they aren t about to take the conflict eam). Some people are taking the conflict eam so please make sure before you discuss with anyone! The eam is designed for one hour (you can take 75 mins to finish). We indicate net to each problem how much time we suggest you spend on it. We also suggest you spend the last 0 minutes of the eam reviewing your answers. X Problem Possible Score Total 00

2 Problem : Optimization Short Answers (6 points) [0 minutes] The following questions concern the interactions between different optimizations a compiler can do. You should be able to answer them in to sentences each. (4 points each) (A) Performing register allocation before instruction scheduling can lead to worse (longer-running) schedules. Why? (4 points). Register allocation minimizes the number of registers used but introduces more dependencies between instructions (two independent variables may share a single register). Hence it reduces the freedom of instruction scheduling and possibly results in longer schedules. (B) Performing common subepression elimination (CSE) can make instruction scheduling worse. Why? (Assume, for this question only, that register allocation is not an issue; you have enough registers to never have to spill) (4 points). Similar to the answer for question (A), CSE between two independent instructions introduces new dependencies, potentially making instruction scheduling harder and longer. (C) Doing a poor job of alias analysis (i.e., the compiler thinks too many variables could alias each other) can make register allocation worse. Why? (4 points).

3 When aliased variables are allocated to different registers, etra operations (e.g., save dirty registers to memory or free invalid registers) are needed to maintain the consistency between the variables. These operations are unnecessary unless the variables indeed alias each other. (D) Performing common subepression elimination can make register allocation worse. Why? (4 points) The variable used to memoize a common subepression becomes live, no matter whether it was live before the CSE. The new live variables put more pressure on register allocation and may cause etra spill code. Problem : Function Calls and Semantic Actions (0 points) [5 minutes] (A) For the following function, show what the activation record for calling the function would be, including both what the caller sets up and what the callee sets up. Make the following assumptions: (i) the machine has four registers, plus an FP register and an SP register, and all the registers are 4 bytes; (ii) the program is using caller saves; (iii) the compiler had to spill one temporary in foo (holding an integer) to the stack. Show the stack growing down (as in the notes); (iv) Assume doubles are 8 bytes, and ints, floats and pointers are 4 bytes. 3

4 For each entry in the stack, show how many bytes that entry takes up. (0 points): double foo (int, double y) { double z; float bar;... //some computation return z; } rest of stack saved registers (4*4 bytes) return val for caller (8 bytes) arg for foo (4 bytes) arg y for foo (4 bytes) caller s old return address (4 bytes) caller s old frame pointer (4 bytes) z (8 bytes) bar (4 bytes) spilled temporary (4 bytes) caller callee Problem 3: Common Subepression Elimination (5 points) [0 minutes] Consider the following piece of code: A = B + C B = A + C 3 D = B + C 4 A = B + C 5 C = A + C (A) Assume there is no aliasing between variables. For each statement, list which epressions are available after the statement eecutes. (5 points) After Instruction Available Epressions 4

5 After Instruction Available Epressions B + C A + C 3 A + C, B + C 4 B + C 5 (B) What does the code look like after performing CSE? Leave the code in IR form. When eliminating a redundant epression, replace it with the variable that holds the previous result of computing the epression. (5 points) A = B + C B = A + C 3 D = B + C 4 A = D 5 C = A + C (C) How would your response to part (B) change if C and D were aliased? (5 points) No redundant epression can be eliminated at all. Problem 4: Register Allocation (4 points) [5 minutes] Consider the following code (assume this is the full program): 5

6 READ(A) B = A 3 A = A + B 4 C = B + A 5 D = C A 6 E = D + A 7 A = C E 8 B = B + A 9 WRITE(A) //this counts as a use of A 0 WRITE(B) //this counts as a use of B (A) Answer the following questions: ) Show which variables and temporaries are live after each instruction (assume no aliasing). (0 points) After Instruction Live Variables After Instruction Live Variables {A} {B, A} 3 {B, A} 4 {B, C, A} 5 {B, C, D, A} 6 {B, C, E} 7 {B, A} 8 {B, A} 9 {B} 0 {} (B) For the following scenarios, show what code needs to be generated using bottom-up register allocation for the given three-address-code instruction and give the state of the registers after code generation (if a value in a register is dirty, mark it with a *) If variables need to be spilled, spill non-dirty registers before dirty registers, and if there is a tie, spill the numerically lower register. Before instruction 5, assume the state of the registers is as follows: 6

7 R R R3 A B* C* What code is generated for instruction 5, D = C * A (assume B, C, D and A are live after this instruction) (4 points)? MUL R3 R R What is the state of the registers after this code (3 points)? R R R3 R R R3 D* B* C* Based on the register states you computed above, what code is generated for the net instruction, E = D + A (assume B, C, and E are live after this instruction) (4 points)? STORE R B LOAD A R 3 ADD R R R What is the state of the registers after this code (3 points)? R R R3 7

8 R R R3 E* C* Problem 5: Instruction Scheduling (35 points) [0 minutes] For the following problems, assume a machine that has ALUs and L/S units. The ALUs can eecute ADDs with a single-cycle latency. Only ALU0 can eecute SUBs with a two-cycle latency. Only ALU can eecute MULs with a two-cycle latency. LDs take two cycles, and occupy either ALU in the first cycle and either L/S unit in the second. STs occupy either L/S unit for one cycle. Assume that ALU0 is pipelined, but ALU is not. Assume that neither L/S unit is pipelined. (A) There are ten reservation tables for instructions LD, ST, ADD, SUB, and MUL. Fill in the five empty ones (0 points): ADD: SUB: ALU0 ALU L/S0 L/S ALU0 ALU L/S0 L/S ADD: MUL: ALU0 ALU L/S0 L/S ALU0 ALU L/S0 L/S LOAD: ALU0 ALU L/S0 L/S LOAD: ALU0 ALU L/S0 L/S LOAD3: ALU0 ALU L/S0 L/S LOAD4: ALU0 ALU L/S0 L/S STORE: ALU0 ALU L/S0 L/S STORE: ALU0 ALU L/S0 L/S ADD: SUB: LOAD: LOAD3: ALU0 ALU L/S0 L/S ALU0 ALU L/S0 L/S ALU0 ALU L/S0 L/S ALU0 ALU L/S0 L/S ADD: MUL: LOAD: LOAD4: ALU0 ALU L/S0 L/S ALU0 ALU L/S0 L/S ALU0 ALU L/S0 L/S ALU0 ALU L/S0 L/S 8

9 STORE: ALU0 ALU L/S0 L/S STORE: ALU0 ALU L/S0 L/S (B) Fill in the five missing arrows (including latencies) and the four missing heights to the datadependence graph for the following piece of code. Show the heights of each node in the graph (recall that the height of an instruction with no dependent instructions is its latency) (9 points): LD A, R; //Load A into R LD B, R; //Load B into R 3 R3 = R R 4 R4 = R LD C, R5; 6 R6 = R4 + R 7 R7 = R5 R6 8 ST R7, C //Store R7 into C 9 R8 = R3 + R6 0 ST R8, D //Store R8 into D 3: R3 = R*R [4] 9: R8 = R3+R6 [] 0: ST R8, D [] 4: R4 = R+3 [ ] : LD B, R [ ] 6: R6 = R4+R [ ] 8: ST R7, C [] : LD A, R [ ] 5: LD C, R5 [5] 7: R7=R5-R6 [3] The DDG with heights of each node is shown below. 9

10 3: R3 = R*R [4] 9: R8 = R3+R6 [] 0: ST R8, D [] 4: R4 = R+3 [5] : LD B, R [7] : LD A, R [6] 5: LD C, R5 [5] 8: ST R7, C [] 6: R6 = R4+R [4] 7: R7=R5-R6 [3] (C) For each instruction above, show in which cycle it will be eecuted if we use height-based list scheduling (we have scheduled instructions and for you). If there is a tie in heights, give priority to the instruction earlier in program order. Use the reservation tables from Part. Show your work in the table below. You may not use all of the rows. ( points) Cycle ALU0 ALU L/S0 L/S Cycle ALU0 ALU L/S0 L/S (D) Would the program run faster if you had 3 L/S units? Why or why not? (You shouldn t have to re-do the entire schedule to answer this question) (4 points) 0

11 Yes, the program would run faster with the third L/S unit. Instruction 5 can be scheduled to start at cycle, using ALU0 and L/S. Then Instruction 4 can still start at cycle 3 by using ALU. One cycle got saved and the rest of the instructions can be scheduled in the same way.