TC58NYG1S3HBAI4 2 GBIT (256M 8 BIT) CMOS NAND E 2 PROM DESCRIPTION. FEATURES Organization x8 Memory cell array K 8 Register C

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1 MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 GBIT (256M 8 BIT) CMOS NAND E 2 PROM DESCRIPTION The is a single.8v 2Gbit (2,28,70,376 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E 2 PROM) organized as ( ) bytes 64 pages 2048 blocks. The device has two 276-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 276-byte increments. The Erase operation is implemented in a single block unit (28 Kbytes + 8 Kbytes: 276 bytes 64 pages). The is a serial-type memory device which utilizes the pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed, making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATUS Organization x8 Memory cell array K 8 Register Page size 276 bytes Block size (28K + 8K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read Mode control Serial input/output Command control Number of valid blocks Min 2008 blocks Max 2048 blocks Power supply VCC =.7V to.95v Access time Cell array to register Read Cycle Time Program/Erase time Auto Page Program Auto Block Erase Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby 25 µs max 25 ns min (CL=30pF) 300 µs/page typ. 3.5 ms/block typ. 30 ma max 30 ma max 30 ma max 50 µa max Package P-TFBGA CZ (Weight: 0.5 g typ.) 8 bit ECC for each 52Byte is required C

2 PIN ASSIGNMENT (TOP VIEW) A NC NC NC NC B NC NC NC C WP V SS RY/BY D NC NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC NC NC NC NC H NC NC NC NC V CC J NC 2 NC V CC 6 8 K V SS V SS L NC NC NC NC M NC NC NC NC PIN NAMES to 8 WP V CC V SS NC port Chip enable Write enable Read enable Command latch enable latch enable Write protect Ready/Busy Power supply Ground No Connection C

3 BLOCK DIAGRAM Status register V CC V SS to Control circuit register Column buffer Column decoder 8 Command register Data register Sense amp WP Logic control Control circuit Row address buffer decoder Row address decoder Memory cell array HV generator ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT V CC Power Supply Voltage 0.6 to 2.5 V V IN Input Voltage 0.6 to 2.5 V V Input / Output Voltage 0.6 to V CC ( 2.5 V) V P D Power Dissipation 0.3 W T STG Storage Temperature 55 to 25 C T OPR Operating Temperature -40 to 85 C Note: Avoid locations where the device may be exposed to water (wet, rain, dew condensation, etc.) CAPACITAN *(Ta = 25 C, f = MHz) SYMBOL PARAMETER CONDITION MIN MAX UNIT C IN Input V IN = 0 V 0 pf C OUT Output V OUT = 0 V 0 pf * This parameter is periodically sampled and is not tested for every device C

4 VALID BLOCKS SYMBOL PARAMETER MIN TYP. MAX UNIT N VB Number of Valid Blocks Blocks NOTE: The device occasionally contains unusable blocks. Refer to Application Note (3) toward the end of this document. The first block (Block 0) is guaranteed to be a valid block at the time of shipment. The specification for the minimum number of valid blocks is applicable over lifetime. DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT V CC Power Supply Voltage.7.95 V V IH High Level Input Voltage V CC x 0.8 V CC V V IL Low Level Input Voltage 0.3* V CC x 0.2 V * 2 V (pulse width lower than 20 ns) DC CHARACTERISTICS (Ta = -40 to 85 C, VCC =.7 to.95v) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT I IL Input Leakage Current V IN = 0 V to V CC ±0 µa I LO Output Leakage Current V OUT = 0 V to V CC ±0 µa I CCO Serial Read Current = V IL, I OUT = 0 ma, t RC = 25 ns 30 ma I CCO2 Programming Current 30 ma I CCO3 Erasing Current 30 ma I CCS Standby Current = V CC 0.2 V, WP = 0 V/V CC 50 µa V OH High Level Output Voltage I OH = 0. ma V CC 0.2 V V OL Low Level Output Voltage I OL = 0. ma 0.2 V I OL Output Current of ( ) pin V OL = 0.2 V 4 ma C

5 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -40 to 85 C, VCC =.7 to.95v) SYMBOL PARAMETER MIN MAX UNIT Setup Time 2 ns t CLH Hold Time 5 ns t CH Setup Time 20 ns Hold Time 5 ns t WP Write Pulse Width 2 ns t ALS Setup Time 2 ns t ALH Hold Time 5 ns t DS Data Setup Time 2 ns t DH Data Hold Time 5 ns t WC Write Cycle Time 25 ns t WH t WW WP High Hold Time 0 ns High to Low 00 ns t RR Ready to Falling Edge 20 ns t RW Ready to Falling Edge 20 ns t RP Read Pulse Width 2 ns t RC Read Cycle Time 25 ns t A t A Access Time 20 ns Access Time 25 ns t CLR t AR Low to Low to Low 0 ns Low 0 ns t RHOH t RLOH t RHZ t CHZ D t H High to Output Hold Time 25 ns Low to Output Hold Time 5 ns High to Output High Impedance 60 ns High to Output High Impedance 20 ns High to or Don t Care 0 ns High Hold Time 0 ns t IR Output-High-Impedance-to- Falling Edge 0 ns t RHW High to Low 30 ns t WHC t WHR High to High to Low 30 ns Low 60 ns t WB High to Busy 00 ns t RST Device Reset Time (Ready/Read/Program/Erase) 5/5/0/500 µs *: tcls and tals can not be shorter than twp *2: tcs should be longer than twp + 8ns C

6 AC TEST CONDITIONS PARAMETER CONDITION V CC:.7 to.95v Input level Input pulse rise and fall time V CC 0.2 V, 0.2 V 3 ns Input comparison level V CC / 2 Output data comparison level V CC / 2 Output load C L (30 pf) + TTL Note: Busy to ready time depends on the pull-up resistor tied to the (Refer to Application Note (9) toward the end of this document) pin. PROGRAMMING / ERASING / ADING CHARACTERISTICS (Ta = -40 to 85 C, VCC =.7 to.95v) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES t PROG Programming Time µs t DCBSYW Data Cache Busy Time in Write Cache (following h) 0 µs t DCBSYW2 Data Cache Busy Time in Write Cache (following 5h) 700 µs (2) N Number of Partial Program Cycles in the Same Page 4 () t BERASE Block Erasing Time ms t R Memory Cell Array to Starting 25 µs t DCBSYR Data Cache Busy in Read Cache (following 3h and 3Fh) 25 µs t DCBSYR2 Data Cache Busy in Page Copy (following 3Ah) 30 µs () Refer to Application Note (2) toward the end of this document. (2) t DCBSYW2 depends on the timing between internal programming time and data in time. Data Output When th is long, output buffers are disabled by /=High, and the hold time of data output depends on trhoh (25ns MIN). Under this condition, the waveforms look like Normal Serial Read Mode. When th is short, output buffers are not disabled by /=High, and the hold time of data output depends on trloh (5ns MIN). Under this condition, output buffers are disabled by the rising edge of,, / or the falling edge of /, and waveforms look like Extended Data Output Mode C

7 TIMING DIAGRAMS Latch Timing Diagram for Command//Data Setup Time Hold Time t DS t DH : V IH or V IL Command Input Cycle Timing Diagram t CLH t CH t WP t ALS t ALH t DS t DH : V IH or V IL C

8 Input Cycle Timing Diagram t CLH t CH t WC t WC t CH t WP t WH t WP t WH t WP t WH t WP t WH t WP t ALS t ALH t DS t DH t DS t DH t DS t DH t DS t DH t DS t DH CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 : V IH or V IL Data Input Cycle Timing Diagram t CLH t CH t CH t ALS t ALH t WC t WP t WH t WP t WP t DS t DH t DS t DH t DS t DH D IN0 D IN D IN C

9 Serial Read Cycle Timing Diagram t RC t RP t H t RP t RP t CHZ t A t RHZ t RHZ t RHZ t RHOH t A trhoh t A trhoh t A t RR t A : V IH or V IL Status Read Cycle Timing Diagram t CLR t CLH t WP t CH t A t WHC t CHZ t WHR t DS t DH t IR t A t RHZ t RHOH 70h/7h* Status output *: 70h/7h represent the hexadecimal number : V IH or V IL C

10 Read Cycle Timing Diagram t CLR t CLH t CLH t CH t CH t WC t ALH t ALS t ALH t ALS t R t RC t WB t RR t A 00h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 30h t A DOUT N DOUT N + Col. Add. N Data out from Col. Add. N Read Cycle Timing Diagram: When Interrupted by t CLR t CLH t CLH t CH t CH t WC D t ALH t ALS t ALH t ALS t R t RC t CHZ t WB t RR t A t RHZ t RHOH 00h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 30h t A DOUT N DOUT N + Col. Add. N Data out from Col. Add. N C

11 Read Cycle with Data Cache Timing Diagram (/2) t CLR t CLR t CLH t CH t CLH t CH t CLH t CH t CLH t CH t WC t ALH t ALS t ALH t ALS t RW t A t A t R t DCBSYR t RC t DCBSYR t WB t WB t WB t RR t A t RR t A 00h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 30h 3h DOUT 0 DOUT DOUT 3h DOUT 0 Column address N * Page address M Page address M Page address M + Data out from Col. Add. 0 Data out from Col. Add. 0 * The column address will be reset to 0 by the 3h command input. Continues to of next page C

12 Read Cycle with Data Cache Timing Diagram (2/2) t CLR t CLR t CLR t CLH t CH t CLH t CH t CLH t CH t A t A t A t DCBSYR t RC t DCBSYR t RC tdcbsyr t RC t WB t WB t WB t RR ta t RR ta t RR t A D OUT 3h DOUT 0 DOUT Page address M + D OUT 3h DOUT 0 DOUT Page address M + 2 D OUT 3Fh DOUT 0 DOUT Page address M + x D OUT Data out from Col. Add. 0 Data out from Col. Add. 0 Data out from Col. Add. 0 Make sure to terminate the operation with 3Fh command. Continues from of previous page C

13 Column Change in Read Cycle Timing Diagram (/2) t CLR t CLH t CLH t CH t CH t WC t A talh t ALS t ALH t ALS t R t RC t WB t RR t A 00h CA0 to 7 CA8 to Column address A PA0 to 7 PA8 to 5 Page address P PA6 30h D OUT A D OUT A + D OUT A + N Page address P Data out from Column address A Continues to of next page C

14 Column Change in Read Cycle Timing Diagram (2/2) t CLR tclh t CLH t CH t CH t RHW t WC t A t ALH t ALS t ALH t ALS t WHR t RC t A t IR D OUT A + N 05h CA0 to 7 CA8 to Column address B E0h D OUT B D OUT B + Page address P D OUT B + N Data out from Column address B Continues from of previous page C

15 Data Output Timing Diagram t CLH t CH t ALH t RC t CHZ t RP t H t RP t RP t RHZ t A t A t A t DS t t A RLOH t RLOH t DH Dout Dout Dout Command t RR t RHOH t RHOH C

16 Auto-Program Operation Timing Diagram t CLH t CH t ALH t ALH t ALS t ALS t WB t PROG t RW t DS t DS tdh t DS tdh t DH 80h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 D INN D IN N+ D INM* 0h 70h Status output Column address N : Do not input data while data is being output. : V IH or V IL * M: up to C

17 Auto-Program Operation with Data Cache Timing Diagram (/3) t CLH t CH t ALH t ALH t ALS t DCBSYW2 t ALS t WB t DS t DS t DH t DS tdh t DH 80h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 D INN D IN N+ 5h 80h CA0 to 7 Column address N D INM* : Do not input data while data is being output. : V IH or V IL Continues to of next page * M: up to C

18 Auto-Program Operation with Data Cache Timing Diagram (2/3) t CLH t CH t ALH t ALH t ALS t ALS t DCBSYW2 t WB t DS t DS tdh t DH t DS t DH 80h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 D INN D IN N+ 5h 80h CA0 to 7 Column address N D INM* Repeat a max of 62 times (in order to program pages to 62 of a block). 2 Continues from of previous page Continues to 2 of next page : Do not input data while data is being output. : V IH or V IL * M: up to C

19 Auto-Program Operation with Data Cache Timing Diagram (3/3) t CLH t CH t ALH t ALH t ALS t ALS t PROG (*) t WB t DS t DS tdh t DH t DS t DH 80h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 D INN D IN N+ 0h 70h Status Column address N D INM* 2 Continues from 2 of previous page : Do not input data while data is being output. : V IH or V IL * M: up to 275 (*) t PROG: Since the last page s programming by 0h command is initiated after the previous cache program, the t PROG during cache programming is given by the following equation. t PROG = t PROG of the last page + t PROG of the previous page A A = (command input cycle + address input cycle + data input cycle time of the last page) If A exceeds the t PROG of previous page, t PROG of the last page is t PROG max. (Note) Make sure to terminate the operation with 80h-0h command sequence. If the operation is terminated by 80h-5h command sequence, monitor 6 (Ready / Busy) by issuing the Status Read command (70h) and make sure the previous page program operation is completed. If the page program operation is completed, issue FFh reset before the next operation C

20 Multi-Page Program Operation with Data Cache Timing Diagram (/4) t CLH t CH t ALH t ALH t ALS t ALS t DCBSYW t WB t DS t DS tdh t DH t DS t DH 80h CA0 to 7 CA8 to PA0 to7 PA8 to 5 PA6 D INN D IN N+ h 8h CA0 to 7 Column address N Page P District-0 D INM* Repeat a max of 63 times (in order to program pages 0 to 62 of a block). : Do not input data while data is being output. Continues to of next page : V IH or V IL * M: up to C

21 Multi-Page Program Operation with Data Cache Timing Diagram (2/4) t CLH t CH t ALH t ALH t ALS t DCBSYW2 t ALS t WB t DS t DS tdh t DH t DS t DH 8h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 D INN D IN N+ 5h 80h CA0 to 7 Column address N Page P District- D INM* Repeat a max of 63 times (in order to program pages 0 to 62 of a block). 2 Continues from of previous page Continues to 2 of next page : Do not input data while data is being output. : V IH or V IL * M: up to C

22 Multi-Page Program Operation with Data Cache Timing Diagram (3/4) t CLH t CH t ALH t ALH t ALS t ALS t DCBSYW t WB t DS t DS t DH t DS tdh t DH 80h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 D INN D IN N+ h 8h CA0 to 7 Column address N Page P+n District-0 D INM* 2 Continues from 2 of previous page 3 Continues to 3 of next page : Do not input data while data is being output. : V IH or V IL * M: up to C

23 Multi-Page Program Operation with Data Cache Timing Diagram (4/4) t CLH t CH t ALH t ALH t ALS t ALS t PROG (*) t WB t DS t DS tdh t DH t DS t DH 8h CA0 to 7 CA8 to PA0 to 7 PA8 to 5 PA6 D INN D IN N+ 0h 7h Status output Column address N Page P+n District- D INM* 3 Continues from 3 of previous page : Do not input data while data is being output. : V IH or V IL * M: up to 275 (*) t PROG: Since the last page s programming by 0h command is initiated after the previous cache program, the t PROG during cache programming is given by the following equation. t PROG = t PROG of the last page + t PROG of the previous page A A = (command input cycle + address input cycle + data input cycle time of the last page) If A exceeds the t PROG of previous page, t PROG of the last page is t PROG max. (Note) Make sure to terminate the operation with 8h-0h command sequence. If the operation is terminated by 8h-5h command sequence, monitor 6 (Ready / Busy) by issuing the Status Read command (70h) and make sure the previous page program operation is completed. If the page program operation is completed, issue FFh reset before the next operation C

24 Auto Block Erase Timing Diagram t CLH t ALS t ALH t WB t BERASE 60h PA0 PA8 PA6 D0h 70h to 7 to 5 Status output Auto Block Erase Setup command Erase Start command Busy Status Read command : Do not input data while data is being output. : V IH or V IL C

25 Multi Block Erase Timing Diagram t CLH t ALS t ALH t WB t BERASE 60h PA0 to 7 PA8 to 5 PA6 D0h 7h Status output Auto Block Erase Setup command Erase Start command Busy Status Read command Repeat 2 times (District-0,) : V IH or V IL : Do not input data while data is being output C

26 ID Read Operation Timing Diagram t CH t A t CH t ALH t ALS t ALH t AR t DH t DS t A t A t A t A t A 90h 00h 98h AAh See Table 5 See Table 5 See Table 5 ID Read command 00 Maker code Device code 3rd Data 4th Data 5th Data : V IH or V IL C

27 PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. Command Latch Enable: The input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the port on the rising edge of the signal while is High. Latch Enable: The signal is used to control loading address information into the internal address register. information is latched into the address register from the port on the rising edge of while is High. Chip Enable: The device goes into a low-power Standby mode when goes High while the device is in Ready state. The signal is ignored when the device is in Busy state ( = L), such as during a Program, Erase or Read operation, and will not enter Standby mode even if the input goes High. Write Enable: The signal is used to control the acquisition of data from the port. Read Enable: The signal controls serial data output. Data is available ta after the falling edge of. The internal column address counter is also incremented ( = + ) on this falling edge. Port: to 8 The to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: WP The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used to protect the data during the power-on/off sequence when input signals are invalid. Ready/Busy: The output signal is used to indicate the operating condition of the device. The signal is in Busy state ( = L) during the Program, Erase and Read operations and will return to Ready state ( = H) after completion of the operation. The output buffer for this signal is an open drain and has to be pulled up to VCC with an appropriate resistor. If signal is not pulled up to VCC ( Open state), device operation cannot be guaranteed C

28 Schematic Cell Layout and Assignment The Program operation works on page units while the Erase operation works on block units. Data Cache A page consists of 276 bytes in which 2048 bytes are used for main memory storage and 28 bytes are for redundancy or for other uses. Page Buffer page = 276 bytes block = 276 bytes 64 pages = (28K + 8K) bytes Capacity = 276 bytes 64 pages 2048 blocks 3072 pages 2048 blocks 64 Pages= block An address is read in via the port over five consecutive clock cycles, as shown in Table Table. ing First cycle CA7 CA6 CA5 CA4 CA3 CA2 CA CA0 Second cycle L L L L CA CA0 CA9 CA8 CA0 to CA: Column address PA0 to PA5: Page address in block PA6 to PA6: Block address Third cycle PA7 PA6 PA5 PA4 PA3 PA2 PA PA0 Fourth cycle PA5 PA4 PA3 PA2 PA PA0 PA9 PA8 Fifth cycle L L L L L L L PA C

29 Operation Mode: Logic and Command Tables The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown in Table 3. input, command input and data input/output are controlled by the,,,, and WP signals, as shown in Table 2. Table 2. Logic Table WP * Command Input H L L H * Data Input L L L H H Input L H L H * Serial Data Output L L L H * During Program (Busy) * * * * * H During Erase (Busy) * * * * * H During Read (Busy) * * H * * * * * L H (*2) H (*2) * Program, Erase Inhibit * * * * * L Standby * * H * * 0 V/V CC H: V IH, L: V IL, *: V IH or V IL *: When the WP signal goes Low, Program or Erase operation is inhibited (Refer to Application Note (0) toward the end of this document). *2: If is Low during Read Busy, and to the device. Reset or Status Read command can be input during Read Busy. must be held High to avoid unintended command/address input to the device or read C

30 Table 3. Command table (HEX) First Cycle Second Cycle Acceptable while Busy Serial Data Input 80 Read Column Change in Serial Data Output 05 E0 Read with Data Cache 3 Read Start for Last Page in Read Cycle with Data Cache 3F Auto Page Program 80 0 Column Change in Serial Data Input 85 Auto Page Program with Data Cache Multi Page Program Read for Page Copy (2) with Data Out 00 3A Auto Program with Data Cache during Page Copy (2) 8C 5 Auto Program for last page during Page Copy (2) 8C 0 Auto Block Erase 60 D0 ID Read 90 Status Read 70 Status Read for Multi-Page Program or Multi Block Erase 7 Reset FF HEX data bit assignment (Example) Serial Data Input: 80h Table 4. Read mode operation states to 8 Power Output select L L L H L Data output Active Output Deselect L L L H H High impedance Active H: V IH, L: V IL C

31 DEVI OPERATION Read Mode Read mode is set when the "00h" and 30h commands are issued to the Command register. Between the two commands, a start address for the Read mode needs to be issued. After the initial power on sequence, 00h command is latched into the internal command register. Then the Read operation after the power on sequence is executed by the setting of only five address cycles and 30h command. The sequence and the block diagram are shown below (Refer to the timing chart for detail). Column M Page N Busy t R 00h 30h M M+ M+2 Data Cache Page Buffer Select page N M Start-address input to 8: m = 275 m Cell array Page N A data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of in the 30h command input cycle (after the address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the clock from the start address designated in the address input cycle. Random Column Change in Read Cycle 00h Busy t R Col. M 30h M M+ M+2 M+3 05h E0h M M + M +2 M +3 M +4 Select page N Col. M Page N Start-address input M M Page N Col. M Page N Start from Col. M Start from Col. M During the serial data output from the Data Cache, the column address can be changed by inputting a new column address using the 05h and E0h commands. The data is read out in serially starting at the new column address. Random Column Change operation can be done multiple times within the same page C

32 Read with Data Cache The device has a Read with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be started from the beginning. 00h 30h t R t DCBSYR t DCBSYR t DCBSYR h h Fh Data Cache Page Buffer Cell Array If the 3h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, reducing the t R (Data transfer from memory cell to data register). Page N Col. M 30h Page N 2 Page N + Column 0 Page N 3 Page N Page N + Page N + 2 Page N Page N+ Page N h & clock Page N + 2 Page N + 2. Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state for t R max. 2. After the Ready/Busy signal returns to Ready, 3h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes t DCBSYR max and the completion of this time period can be detected by Ready/Busy signal. 3. Data of Page N + is transferred to Page Buffer from cell while the data of Page N in Data Cache can be read out by / clock simultaneously. 4. The 3h command makes data of Page N + transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for t DCBSYR max.. This Busy period depends on the combination of the internal data transfer time from cell to Page Buffer and the serial data out time. 5. Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + in Data Cache can be read out by / clock simultaneously. 6. The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for t DCBSYR max.. This Busy period depends on the combination of the internal data transfer time from cell to Page Buffer and the serial data out time. 7. Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately after the completion of serial data out. 3h & clock 5 Page N + 3Fh & clock C

33 Multi Page Read Operation The device has a Multi Page Read operation and Multi Page Read with Data Cache operation. () Multi Page Read without Data Cache The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each District has to be selected. Command input 60 (3 cycles) (3 cycles) input 60 Page PA0 to PA6 (District 0) input 30 A Page PA0 to PA6 (District ) tr A A A Command input 00 (5 cycles) input 05 Column + Page CA0 to CA, PA0 to PA6 (District 0) (2 cycles) input E0 Data output B Column CA0 to CA (District 0) (District 0) B B B Command input 00 (5 cycles) input 05 Column + Page CA0 to CA, PA0 to PA6 (District ) (2 cycles) input Column CA0 to CA (District ) E0 Data output (District ) District 0 District Reading Selected page Selected page The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising edge of in the 30h command input cycle (after the 2 Districts address information has been latched). The device will be in the Busy state during this transfer period. After the transfer period, the device returns to Ready state. Serial data can be output synchronously with the clock from the start address designated in the address input cycle C

34 (2) Multi Page Read with Data Cache When the block address changes (increments) this sequence has to be started from the beginning. The sequence of command and address input is shown below. Same page address (PA0 to PA5) within each District has to be selected. Command input 60 input 60 Page PA0 to PA6 (Page m0 ; District 0) input 30 A Page PA0 to PA6 (Page n0 ; District ) tr A A A 3 tdcbsyr Command input 00 input 05 Column + Page CA0 to CA, PA0 to PA6 (Page m0 ; District 0) input E0 Data output B Column CA0 to CA (District 0) (District 0) B B B Command input 00 input 05 Column + Page CA0 to CA, PA0 to PA6 (Page n0 ; District ) input Column CA0 to CA (District ) E0 Data output (District ) C C C C 3F tdcbsyr Command input 00 input 05 Column + Page CA0 to CA, PA0 to PA6 (Page m63 ; District 0) input E0 Data output D Column CA0 to CA (District 0) Return to A Repeat a max of 63 times (District 0) D Command input D 00 input 05 input E0 Data output D Column + Page CA0 to CA, PA0 to PA6 (Page n63 ; District ) Column CA0 to CA (District ) (District ) C

35 (3) Notes (a) Internal addressing in relation to the Districts To use the Multi Page Read operation, the internal addressing should be considered in relation to the District. The device consists of 2 Districts. Each District consists of 024 erase blocks. The allocation rule as follows: District 0: Block 0, Block 2, Block 4, Block 6,, Block 2046 District : Block, Block 3, Block 5, Block 7,, Block 2047 (b) input restriction for the Multi Page Read operation There are the following restrictions in using Multi Page Read: (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two Districts has to be selected. For example: (60) [District 0, Page 0x00000] (60) [District, Page 0x00040] (30) (60) [District 0, Page 0x0000] (60) [District, Page 0x0004] (30) (Acceptance) There is no order limitation of the District for the address input. For example, the following operation is accepted: (60) [District 0] (60) [District ] (30) (60) [District ] (60) [District 0] (30) It requires no mutual address relation between the selected blocks from each District. (c) WP signal Make sure WP is held to High when the Multi Page Read operation is performed C

36 Auto Page Program Operation The device carries out an Auto Page Program operation when it receives a "0h" Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to the detailed timing chart). 80h Din Din Din Din 0h 70h Status Out Col. M Page P Data Data input Selected page Program Read & verification The data is transferred (programmed) from the Data Cache via the Page Buffer to the selected page on the rising edge of following input of the 0h command. After programming, the programmed data is transferred back to the Page Buffer to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. Random Column Change in Auto Page Program Operation The column address can be changed by the 85h command during the data input sequence of the Auto Page Program operation. Two address input cycles after the 85h command are recognized as a new column address for the data input. After the new data is input to the new column address, the 0h command initiates the actual data program into the selected page automatically. The Random Column Change operation can be repeated multiple times within the same page. 80h Din Din Din Din 85h Din Din Din Din 0h 70h Status Col. M Page N Col. M Busy Col. M Col. M Data input Selected page Program Read & verification C

37 Multi Page Program The device has a Multi Page Program, which enables even higher speed program operation compared to Auto Page Program. The sequence of command, address and data input is shown below (Refer to the detailed timing chart). Although two Districts are programmed simultaneously, Pass/Fail is not available for each page by "70h" command when the program operation completes. The status bit of is set to when any of the pages fail. Limitation in addressing with Multi Page Program is shown below. Multi Page Program t DCBSYW t PROG 0 to 8 80h & Data Input h 8h & Data Input 0h 70h Pass Note CA0 to CA : Valid CA0 to CA : Valid PA0 to PA5 : Valid PA0 to PA5 : Valid PA6 : District0 PA6 : District Fail PA7 to PA6 : Valid PA7 to PA6 : Valid NOTE: Any command between h and 8h is prohibited except 70h and FFh. Data Input 80h h 8h 0h District 0 (024 Block) District (024 Block) Block 0 Block 2 Block Block 3 Block 2044 Block 2046 Block 2045 Block C

38 Auto Page Program Operation with Data Cache The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes, this sequence has to be started from the beginning. t DCBSYW2 t DCBSYW2 t PROG (NOTE) 80h Add Add Add Add Add Din Din Din 5h 70h 80h Add Add Add Add Add Din Din Din 5h 70h 80h Add Add Add Add Add Din Din Din 0h 70h Page N 2 Status Output Page N Status Output Page N + P 5 6 Status Output Data Cache Page Buffer Data for Page N 2 3 Data for Page N + 4 Data for Page N Data for Page N + 5 Data for Page N + P Cell Array Page N Page N + Page N + P Page N + P Issuing the 5h command to the device after serial data input initiates the program operation with Data Cache.. Data for Page N is input to Data Cache. 2. Data is transferred to the Page Buffer by the 5h command. During the transfer the Ready/Busy signal outputs Busy state (t DCBSYW2). 3. Data is programmed to the selected page while the data for Page N + is input to the Data Cache. 4. By the 5h command, the data in the Data Cache is transferred to the Page Buffer after the programming of Page N is completed. The device outputs Busy state from the 5h command until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of Page N and serial data input for Page N + (t DCBSYW2). 5. Data for Page N + P is input to the Data Cache while the data of the Page N + P is being programmed. 6. The programming with Data Cache is terminated by the 0h command. When the device becomes Ready state, it shows that the internal programming of the Page N + P is completed. NOTE: Since the last page s programming by the 0h command is initiated after the previous cache program, the t PROG during cache programming is given by the following: t PROG = t PROG for the last page + t PROG of the previous page ( command input cycle + address input cycle + data input cycle time of the last page) C

39 Pass/Fail status for each page programmed by the Auto Page Program with Data Cache operation can be detected by the Status Read operation. : Pass/Fail of the current page program operation. 2: Pass/Fail of the previous page program operation. The Pass/Fail status on and 2 are valid under the following conditions. Status on : Page Buffer Ready/Busy is Ready. The Page Buffer Ready/Busy is output on 6 by Status Read operation or pin after the 0h command. Status on 2: Data Cache Read/Busy is Ready. The Data Cache Ready/Busy is output on 7 by Status Read operation or pin after the 5h command. Example) 2 => => Invalid Invalid Page Invalid Page Page 2 Page N 2 Invalid Invalid Invalid Page N Page N 80h 5h 70h Status Out 80h 5h 70h Status Out 70h Status Out 80h 5h 70h Status Out 80h 0h 70h Status Out 70h Status Out Page Page 2 Page N Page N pin Data Cache Busy Page Buffer Busy Page Page 2 Page N Page N If the Page Buffer Busy returns to Ready before the next 80h command input and Status Read is done during this Ready period, the Status Read provides the Pass/Fail result for Page 2 on and the Pass/Fail result for Page on C

40 Multi Page Program with Data Cache The device has a Multi Page Program with Data Cache operation, which enables an even higher speed program operation compared to Auto Page Program with Data Cache as shown below. When the block address changes (increments) this sequence has to be started from the beginning. The sequence of command, address and data input is shown below (Refer to the detailed timing chart). Data input command Data input command for multi-page program input (District 0) Dummy Program command Data input 0 to 275 input (District ) Program with Data Cache command Data input 0 to 275 Data input command input (District 0) Dummy Program command Data input 0 to 275 Data input command for multi-page program input (District) Auto Page Program command Data input 0 to 275 After either 5h or 0h Program command is input to the device, physical programing starts as follows. For details about Auto Page Program with Data Cache, refer to Auto Page Program Operation with Data Cache. District 0 District Program Read & verification Selected page The data is transferred (programmed) from the page buffer to the selected page on the rising edge of / following input of the 5h or 0h command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached C

41 By starting the above operation from the st page of the selected erase blocks, repeating total of 64 times while incrementing the page address in the blocks, and then inputting the last page data of the blocks, 0h command executes the final programming. Make sure to terminate with 8h-0h command sequence. In this full sequence, the command sequence is following. st th th After the 5h or 0h command, the results of the above operation is shown through the 7h Status Read command. 0 or5 7 Status Read command Fail Pass The 7h command Status description is as below. STATUS OUTPUT Chip Status : Pass/Fail Pass: 0 Fail: 2 District 0 Chip Status : Pass/Fail Pass: 0 Fail: 3 District Chip Status : Pass/Fail Pass: 0 Fail: 4 District 0 Chip Status2 : Pass/Fail Pass: 0 Fail: 5 District Chip Status2 : Pass/Fail Pass: 0 Fail: 6 Ready/Busy Ready: Busy: 0 7 Data Cache Ready/Busy Ready: Busy: 0 describes the Pass/Fail condition of District 0 and (OR data of 2 and 3). If one of the Districts fails during Multi Page Program operation, it shows Fail. 2 to 5 show the Pass/Fail condition of each District. For details on Chip Status and Chip Status2, refer to section Status Read. 8 Write Protect Protect: 0 Not Protect: C

42 Internal addressing in relation to the Districts To use the Multi Page Program operation, the internal addressing should be considered in relation to the District. The device consists of 2 Districts. Each District consists of 024 erase blocks. The allocation rule is as follows: District 0: Block 0, Block 2, Block 4, Block 6,, Block 2046 District : Block, Block 3, Block 5, Block 7,, Block 2047 input restriction for the Multi Page Program with Data Cache operation There are the following restrictions in using Multi Page Program with Data Cache: (Restriction) Maximum one block should be selected from each District. Same page address (PA0 to PA5) within two Districts has to be selected. For example: (80) [District 0, Page 0x00000] () (8) [District, Page 0x00040] (5 or 0) (80) [District 0, Page 0x0000] () (8) [District, Page 0x0004] (5 or 0) (Acceptance) There is no order limitation of the District for the address input. For example, the following operation is accepted: (80) [District 0] () (8) [District ] (5 or 0) (80) [District ] () (8) [District 0] (5 or 0) It requires no mutual address relation between the selected blocks from each District. Operating restriction during the Multi Page Program with Data Cache operation (Restriction) The operation must be terminated with 0h command. Once the operation has started, no commands other than the commands shown in the timing diagram are allowed to be input except for Status Read command and Reset command C

43 Page Copy (2) By using Page Copy (2), data in a page can be copied to another page after the data has been read out. When the block address changes (increments) this sequence has to be started from the beginning. Command input 00 2 input 30 Data output 8C input CA0 to CA, PA0 to PA6 (Page N) Col = 0 start 3 CA0 to CA, PA0 to PA6 (Page M) Data input 5 00 input 3A Data output When changing data, changed data is input. Col = 0 start CA0 to CA, PA0 to PA6 4 (Page N+P) 5 t R t DCBSYW2 t DCBSYR2 A A Data Cache Page Buffer Data for Page N Data for Page N Data for Page M Data for Page N + P Cell Array Page M Page N Page N + P Page Copy (2) operation is as follows.. Data for Page N is transferred to the Data Cache. 2. Data for Page N is read out. 3. for Page M is input. If the data needs to be changed, changed data is input. 4. Data Cache for Page M is transferred to the Page Buffer. 5. After the Ready state, Data for Page N + P is output from the Data Cache while the data of Page M is being programmed C

44 A A Command input 6 8C input Data input 5 00 input 3A Data output 00 input 3A Data output CA0 to CA, PA0 to PA6 (Page M+R) When changing data, changed data is input. 7 CA0 to CA, PA0 to PA6 (Page N+P2) Col = 0 start Col = 0 start CA0 to CA, PA0 to PA6 8 (Page N+Pn) 9 t DCBSYW2 t DCBSYR2 t DCBSYR2 B B Data Cache Page Buffer Data for Page M + R Data for Page M + R Data for Page N + P2 Data for Page N + Pn 9 Cell Array Page M Page N + P Page M + R Page N + P2 Page M + Rn Page N + Pn Page M + Rn 6. for Page (M + R) is input. If the data needs to be changed, changed data is input. 7. After programming of page M is completed, Data Cache for Page M + R is transferred to the Page Buffer. 8. By the 5h command, the data in the Page Buffer is programmed to Page M + R. Data for Page N + P2 is transferred to the Data cache. 9. The data in the Page Buffer is programmed to Page M + Rn. Data for Page N + Pn is transferred to the Data Cache C

45 B B Command input 0 input 8C Data input 0 70 Status CA0 to CA, PA0 to PA6 (Page M+Rn) t PROG (*) Data Cache Page Buffer Page M + Rn Cell Array Data for Page M + Rn 0 Page M + Rn Data for Page M + Rn 0. for Page (M + Rn) is input. If the data needs to be changed, changed data is input.. By issuing the 0h command, the data in the Page Buffer is programmed to Page M + Rn. (*) Since the last page s programming by the 0h command is initiated after the previous cache program, the t PROG here will be expected as the following: t PROG = t PROG of the last page + t PROG of the previous page ( command input cycle + address input cycle + data output/input cycle time of the last page) NOTE) This operation needs to be executed within District-0 or District-. Data input is required only if previous data output needs to be altered. If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed. If the data does not have to be changed, data input cycles are not required. Make sure WP is held to High when the Page Copy (2) operation is performed. Also make sure the Page Copy operation is terminated with 8Ch-0h command sequence C

46 Multi Page Copy (2) By using Multi Page Copy (2), data in two pages can be copied to other pages after the data has been read out. When each block address changes (increments) this sequence has to be started from the beginning. Same page address (PA0 to PA5) within two Districts has to be selected. Command input 60 input 60 input input 05 input E0 Data output A PA0 to PA6 (Page m0 ; District 0) PA0 to PA6 (Page n0 ; District ) CA0 to CA, PA0 to PA6 (Page m0) CA0 to CA (Col = 0) t R A A A 00 input 05 input E0 Data output 8C input Data input B CA0 to CA, PA0 to PA6 (Page n0) CA0 to CA (Col = 0) CA0 to CA, PA0 to PA6 (Page M0 ; District 0) t DCBSYW B B 8C input Data input 5 60 input 60 input 3A C B CA0 to CA, PA0 to PA6 (Page N0 ; District ) t DCBSYW2 PA0 to PA6 (Page m ; District 0) PA0 to PA6 (Page n ; District ) t DCBSYR2 C C 00 input 05 input E0 Data output 00 input 05 input E0 Data output D C CA0 to CA, PA0 to PA6 (Page m) CA0 to CA (Col = 0) CA0 to CA, PA0 to PA6 (Page n) CA0 to CA (Col = 0) D C

47 D 8C input Data input 8C input Data input 5 E D CA0 to CA, PA0 to PA6 (Page M ; District 0) t DCBSYW CA0 to CA, PA0 to PA6 (Page N ; District ) t DCBSYW2 E E 60 input 60 input 3A 00 input 05 input E0 Data output F PA0 to PA6 (Page m63 ; District 0) PA0 to PA6 (Page n63 ; District ) CA0 to CA, PA0 to PA6 (Page m63) CA0 to CA (Col = 0) E t DCBSYR2 F F F 00 input 05 input E0 Data output 8C input Data input G CA0 to CA, PA0 to PA6 (Page n63) CA0 to CA (Col = 0) CA0 to CA, PA0 to PA6 (Page M63 ; District 0) t DCBSYW G G G 8C input Data input 0 CA0 to CA, PA0 to PA6 (Page N63 ; District ) tprog (*) Note) This operation needs to be executed within each District. Data input is required only if previous data output needs to be altered. If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed. If the data does not have to be changed, data input cycles are not required. Make sure WP is held to High when the Multi Page Copy (2) operation is performed. Also make sure the Multi Page Copy operation is terminated with 8Ch-0h command sequence (*) t PROG: Since the last page s programming by 0h command is initiated after the previous cache program, the t PROG* during cache programming is given by the following equation. t PROG = t PROG of the last page + t PROG of the previous page-a A = (command input cycle + address input cycle + data output/input cycle time of the last page) If A exceeds the t PROG of previous page, t PROG of the last page is t PROG max C

48 Auto Block Erase The Auto Block Erase operation starts on the rising edge of after the Erase Start command D0h which follows the Erase Setup command 60h. This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. 60 D0 70 Block input: 3 cycles Erase Start command Status Read command Fail Pass Busy Multi Block Erase The Multi Block Erase operation starts by selecting two block addresses before D0h command as in the below diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by checking the status with 7h status read command. For details on 7h status read command, refer to section Multi Page Program with Data Cache D0 7 Block input: 3 cycles District 0 Block input: 3 cycles District Erase Start command Status Read command Fail Pass Busy Internal addressing in relation to the Districts To use the Multi Block Erase operation, the internal addressing should be considered in relation to the District. The device consists of 2 Districts. Each District consists of 024 erase blocks. The allocation rule is as follows: District 0: Block 0, Block 2, Block 4, Block 6,, Block 2046 District : Block, Block 3, Block 5, Block 7,, Block 2047 input restriction for the Multi Block Erase There are the following restrictions in using Multi Block Erase: (Restriction) Maximum one block should be selected from each District. For example: (60) [District 0] (60) [District ] (D0) (Acceptance) There is no order limitation of the District for the address input. For example, the following operation is accepted: (60) [District ] (60) [District 0] (D0) It requires no mutual address relation between the selected blocks from each District. Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h command input, input the FFh reset command to terminate the operation C

49 ID Read The device contains ID codes which can be used to identify the device type, the manufacturer, and features of the device. The ID codes can be read out under the following timing conditions: t A t AR 90h 00h 98h AAh ID Read command t A 00 Maker code Device code See table 5 See table 5 See table 5 3rd Data 4th Data 5th Data Table 5. Code table Description Hex Data st Data Maker Code h 2nd Data Device Code AAh 3rd Data Chip Number, Cell Type h 4th Data Page Size, Block Size, Width h 5th Data District Number h 3rd Data Description Internal Chip Number Cell Type 2 level cell 4 level cell 8 level cell 6 level cell Reserved C

50 4th Data Description Page Size (without redundant area) KB 2 KB 4 KB 8 KB Block Size (without redundant area) 64 KB 28 KB 256 KB 52 KB Width x8 x6 0 Reserved 0 0 5th Data Description District Number District 2 Districts 4 Districts 8 Districts Reserved C

51 Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass /fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is output via the port using after a 70h command input. The Status Read command can also be used during a Read operation to monitor the Ready/Busy status. The resulting information is outlined in Table 6. Table 6. Status output table Definition Page Program Block Erase Cache Program Read Cache Read 2 Chip Status Pass: 0 Fail: Chip Status 2 Pass: 0 Fail: Pass/Fail Pass/Fail Invalid Invalid Pass/Fail Invalid 3 Not Used Not Used Not Used Page Buffer Ready/Busy Ready: Busy: 0 Data Cache Ready/Busy Ready: Busy: 0 Write Protect Not Protected : Protected: 0 Ready/Busy Ready/Busy Ready/Busy Ready/Busy Ready/Busy Ready/Busy Not Protected/Protected Not Protected/Protected Not Protected/Protected The Pass/Fail status on and 2 is only valid during a Program/Erase operation when the device is in the Ready state. Chip Status : During an Auto Page Program or Auto Block Erase operation this bit indicates the Pass/Fail result. During an Auto Page Program with Data Cache operation, this bit shows the Pass/Fail results of the current page program operation and therefore this bit is only valid when 6 shows the Ready state. Chip Status 2: This bit shows the Pass/Fail result of the previous page program operation during Auto Page Program with Data Cache. This status is valid when 7 shows the Ready State. The status output on 6 is the same as that of 7 if the command input just before 70h is not 5h or 3h C

52 An application example with multiple devices is shown in the figure below. 2 3 N N+ Device Device 2 Device 3 Device N Device N + to 8 Busy N 70h 70h Status on Device Status on Device N System Design Note: If the pin signals from multiple devices are wired together as shown in the diagram, the Status Read function can be used to determine the status of each individual device. Reset The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally generated voltage is discharged to 0 volts and the device enters the Wait state. Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also stop the previous program at a page depending on when the FF reset is input. The response to a FFh Reset command input during the various device operations is as follows: When a Reset (FFh) command is input during Program operation Internal generated voltage 80 0 FF 00 t RST (max 0 µs) C

53 When a Reset (FFh) command is input during Erase operation Internal generated voltage D0 FF 00 t RST (max 500 µs) When a Reset (FFh) command is input during Read operation FF 00 t RST (max 5 µs) When a Reset (FFh) command is input during Ready FF 00 t RST (max 5 µs) When a Status Read command (70h) is input after a Reset FF 70 status : Pass/Fail Pass : Ready/Busy Ready When two or more Reset commands are input in succession () (2) (3) 0 FF FF FF The second FF command is invalid, but the third FF command is valid C

54 APPLICATION NOTES AND COMMENTS () Power-on/off sequence The timing sequence shown in the figure below is necessary for the power-on/off sequence. The device s internal initialization starts after the power supply reaches an appropriate level during the power-on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the figure below. In this time period, the acceptable commands are FFh or 70h. The WP signal is useful for protecting against data corruption at power-on/off. V CC 0 V,,, Don t care.5 V.7 V V IH Don t care ms.7 V.5 V 0.5 V 0.5 V Don t care WP V IL 00 µs max ms max Operation V IL 00 µs max ms max Invalid Invalid Invalid (2) Power-on Reset The following sequence is necessary because some input signals may not be stable at power-on. Power on FF Reset (3) Prohibition of unspecified commands The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. (4) Restriction of commands while in the Busy state During the Busy state, do not input any command except 70h, 7h and FFh C