TMS320C6000 Programmer s Guide

Transcription

1 TMS320C6000 Programmer s Guide Literature Number: SPRU198E October 2000 Printed on Recycled Paper

2 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical Applications ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 2000, Texas Instruments Incorporated

3 Preface Read This First About This Manual This manual is a reference for programming TMS320C6000 digital signal processor (DSP) devices. Before you use this book, you should install your code generation and debugging tools. This book is organized in five major parts: Part I: Introduction includes a brief description of the C6000 architecture and code development flow. It also includes a tutorial that introduces you to the tools you will use in each phase of development and an optimization checklist to help you achieve optimal performance from your code. Part II: C Code includes C code examples and discusses optimization methods for the code. This information can help you choose the most appropriate optimization techniques for your code. Part III: Assembly Code describes the structure of assembly code. It provides examples and discusses optimizations for assembly code. It also includes a chapter on interrupt subroutines. Part IV: C64x Programming Techniques describes programming considerations for the C64x. Part V: Appendix provides a summary of feedback solutions. Contents iii

4 Related Documentation From Texas Instruments Related Documentation From Texas Instruments The following books describe the TMS320C6000 devices and related support tools. To obtain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) When ordering, please identify the book by its title and literature number. TMS320C6000 Assembly Language Tools User s Guide (literature number SPRU186) describes the assembly language tools (assembler, linker, and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the C6000 generation of devices. TMS320C6000 Optimizing C Compiler User s Guide (literature number SPRU187) describes the C6000 C compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code and produces assembly language source code for the C6000 generation of devices. The assembly optimizer helps you optimize your assembly code. TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 CPU architecture, instruction set, pipeline, and interrupts for these digital signal processors. TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes common peripherals available on the TMS320C6201/6701 digital signal processors. This book includes information on the internal data and program memories, the external memory interface (EMIF), the host port interface (HPI), multichannel buffered serial ports (McBSPs), direct memory access (DMA), enhanced DMA (EDMA), expansion bus, clocking and phase-locked loop (PLL), and the power-down modes. TMS320C64x Technical Overview (SPRU395) The TMS320C64x technical overview gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x VelociTI. TMS320 DSP Designer s Notebook: Volume 1 (literature number SPRT125) presents solutions to common design problems using C2x, C3x, C4x, C5x, and other TI DSPs. iv

5 Trademarks Trademarks Solaris and SunOS are trademarks of Sun Microsystems, Inc. VelociTI is a trademark of Texas Instruments Incorporated. Windows and Windows NT are registered trademarks of Microsoft Corporation. Read This First v

6 Contents Contents 1 Introduction Introduces some features of the C6000 microprocessor and discusses the basic process for creating code and understanding feedback. 1.1 TMS320C6000 Architecture TMS320C6000 Pipeline Code Development Flow To Increase Performance Understanding Feedback Stage 1: Qualify the Loop for Software Pipelining Stage 2: Collect Loop Resource and Dependency Graph Information Stage 3: Software Pipeline the Loop Compiler Optimization Tutorial Uses example code to walk you through the code development flow for the TMS320C Introduction: Simple C Tuning Lesson 1: Loop Carry Path From Memory Pointers Lesson 2: Balancing Resources With Dual-Data Paths Lesson 3: Packed Data Optimization of Memory Bandwidth Lesson 4: Program Level Optimization Lesson 5: Writing Linear Assembly Optimizing C/C++ Code Explains how to maximize C performance by using compiler options, intrinsics, and code transformations. 3.1 Writing C/C++ Code Tips on Data Types Analyzing C Code Performance Compiling C/C++ Code Compiler Options Memory Dependencies Performing Program-Level Optimization ( pm Option) Profiling Your Code Using the Standalone Simulator (load6x) to Profile Refining C/C++ Code Using Intrinsics Using Word Access for Short Data Software Pipelining vii

7 Contents 4 Linking Issues Explains linker messages and how to use RTS functions. 4.1 How to Use Linker Error Messages How to Find The Problem Executable Flag How to Save On-Chip Memory by Placing RTS Off-Chip How to Compile Must #include Header Files RTS Data How to Link Example Compiler Invocation Header File Details Changing RTS Data to near Structure of Assembly Code Describes the structure of the assembly code, including labels, conditions, instructions, functional units, operands, and comments. 5.1 Labels Parallel Bars Conditions Instructions Functional Units Operands Comments Optimizing Assembly Code via Linear Assembly Describes methods that help you develop more efficient assembly language programs. 6.1 Assembly Code Assembly Optimizer Options and Directives The on Option The mt Option and the.no_mdep Directive The.mdep Directive The.mptr Directive The.trip Directive Writing Parallel Code Dot Product C Code Translating C Code to Linear Assembly Linear Assembly Resource Allocation Drawing a Dependency Graph Nonparallel Versus Parallel Assembly Code Comparing Performance viii

8 Contents 6.4 Using Word Access for Short Data and Doubleword Access for Floating-Point Data Unrolled Dot Product C Code Translating C Code to Linear Assembly Drawing a Dependency Graph Linear Assembly Resource Allocation Final Assembly Comparing Performance Software Pipelining Modulo Iteration Interval Scheduling Using the Assembly Optimizer to Create Optimized Loops Final Assembly Comparing Performance Modulo Scheduling of Multicycle Loops Weighted Vector Sum C Code Translating C Code to Linear Assembly Determining the Minimum Iteration Interval Drawing a Dependency Graph Linear Assembly Resource Allocation Modulo Iteration Interval Scheduling Using the Assembly Optimizer for the Weighted Vector Sum Final Assembly Loop Carry Paths IIR Filter C Code Translating C Code to Linear Assembly (Inner Loop) Drawing a Dependency Graph Determining the Minimum Iteration Interval Linear Assembly Resource Allocation Modulo Iteration Interval Scheduling Using the Assembly Optimizer for the IIR Filter Final Assembly If-Then-Else Statements in a Loop If-Then-Else C Code Translating C Code to Linear Assembly Drawing a Dependency Graph Determining the Minimum Iteration Interval Linear Assembly Resource Allocation Final Assembly Comparing Performance Contents ix

9 Contents 6.9 Loop Unrolling Unrolled If-Then-Else C Code Translating C Code to Linear Assembly Drawing a Dependency Graph Determining the Minimum Iteration Interval Linear Assembly Resource Allocation Final Assembly Comparing Performance Live-Too-Long Issues C Code With Live-Too-Long Problem Translating C Code to Linear Assembly Drawing a Dependency Graph Determining the Minimum Iteration Interval Linear Assembly Resource Allocation Final Assembly With Move Instructions Redundant Load Elimination FIR Filter C Code Translating C Code to Linear Assembly Drawing a Dependency Graph Determining the Minimum Iteration Interval Linear Assembly Resource Allocation Final Assembly Memory Banks FIR Filter Inner Loop Unrolled FIR Filter C Code Translating C Code to Linear Assembly Drawing a Dependency Graph Linear Assembly for Unrolled FIR Inner Loop With.mptr Directive Linear Assembly Resource Allocation Determining the Minimum Iteration Interval Final Assembly Comparing Performance Software Pipelining the Outer Loop Unrolled FIR Filter C Code Making the Outer Loop Parallel With the Inner Loop Epilog and Prolog Final Assembly Comparing Performance Outer Loop Conditionally Executed With Inner Loop Unrolled FIR Filter C Code Translating C Code to Linear Assembly (Inner Loop) Translating C Code to Linear Assembly (Outer Loop) Unrolled FIR Filter C Code Translating C Code to Linear Assembly (Inner Loop) Translating C Code to Linear Assembly (Inner Loop and Outer Loop) Determining the Minimum Iteration Interval Final Assembly Comparing Performance x

10 Contents 7 Interrupts Describes interrupts from a software programming point of view. 7.1 Overview of Interrupts Single Assignment vs. Multiple Assignment Interruptible Loops Interruptible Code Generation Level 0 - Specified Code is Guaranteed to Not Be Interrupted Level 1 Specified Code Interruptible at All Times Level 2 Specified Code Interruptible Within Threshold Cycles Getting the Most Performance Out of Interruptible Code Interrupt Subroutines ISR with the C/C++ Compiler ISR with Hand-Coded Assembly Nested Interrupts C64x Programming Considerations Describes programming considerations for the C64x. 8.1 Overview of C64x Architectural Enhancements Improved Scheduling Flexibility Greater Memory Bandwidth Support for Packed Data Types Non-aligned Memory Accesses Additional Specialized Instructions Packed-Data Processing on the C64x Introduction to Packed Data Processing Techniques Packed Data Types Storing Multiple Elements in a Single Register Packing and Unpacking Data Optimizing for Packed Data Processing Vectorizing With Packed Data Processing Combining Multiple Operations in a Single Instruction Non-Aligned Memory Accesses Performing Conditional Operations with Packed Data Linear Assembly Considerations Using BDEC and BPOS in Linear Assembly Avoiding Cross Path Stalls FeedbackSolutions A-1 A.1 Loop Disqualification Messages A-2 A.2 Pipeline Failure Messages A-4 A.3 Investigative Feedback A-10 Contents xi

11 Figures Figures 3 1 Dependency Graph for Vector Sum # Software-Pipelined Loop Labels in Assembly Code Parallel Bars in Assembly Code Conditions in Assembly Code Instructions in Assembly Code TMS320C6x Functional Units Units in the Assembly Code Operands in the Assembly Code Operands in Instructions Comments in Assembly Code Dependency Graph of Fixed-Point Dot Product Dependency Graph of Floating-Point Dot Product Dependency Graph of Fixed-Point Dot Product with Parallel Assembly Dependency Graph of Floating-Point Dot Product with Parallel Assembly Dependency Graph of Fixed-Point Dot Product With LDW Dependency Graph of Floating-Point Dot Product With LDDW Dependency Graph of Fixed-Point Dot Product With LDW (Showing Functional Units) Dependency Graph of Floating-Point Dot Product With LDDW (Showing Functional Units) Dependency Graph of Fixed-Point Dot Product With LDW (Showing Functional Units) Dependency Graph of Floating-Point Dot Product With LDDW (Showing Functional Units) Dependency Graph of Weighted Vector Sum Dependency Graph of Weighted Vector Sum (Showing Resource Conflict) Dependency Graph of Weighted Vector Sum (With Resource Conflict Resolved) Dependency Graph of Weighted Vector Sum (Scheduling ci +1) Dependency Graph of IIR Filter Dependency Graph of IIR Filter (With Smaller Loop Carry) Dependency Graph of If-Then-Else Code Dependency Graph of If-Then-Else Code (Unrolled) Dependency Graph of Live-Too-Long Code Dependency Graph of Live-Too-Long Code (Split-Join Path Resolved) Dependency Graph of FIR Filter (With Redundant Load Elimination) Bank Interleaved Memory xii

12 Figures Bank Interleaved Memory With Two Memory Blocks Dependency Graph of FIR Filter (With Even and Odd Elements of Each Array on Same Loop Cycle) Dependency Graph of FIR Filter (With No Memory Hits) Four Bytes Packed Into a Single General Purpose Register Two Half Words Packed Into a Single General Purpose Register Graphical Representation of _packxx2 Intrinsics Graphical Representation of _spack Graphical Representation of 8 bit Packs (_packx4 and _spacku4) Graphical Representation of 8 bit Unpacks (_unpkxu4) Graphical Representation of (_shlmb, _shrmb, and _swap4) Graphical Representation of a Simple Vector Operation Graphical Representation of Dot Product Graphical Representation of a Single Iteration of Vector Complex Multiply Array Access in Vector Sum by LDDW Array Access in Vector Sum by STDW Vector Addition Graphical Representation of a Single Iteration of Vector Multiply Packed 16x16 Multiplies Using _mpy Fine Tuning Vector Multiply (shift > 16) Fine Tuning Vector Multiply (shift < 16) Graphical Representation of the _dotp2 Intrinsic c = _dotp2(b, a) The _dotpn2 Intrinsic Performing Real Portion of Complex Multiply _packlh2 and _dotp2 Working Together Graphical Illustration of _cmpxx2 Intrinsics Graphical Illustration of _cmpxx4 Intrinsics Graphical Illustration of _xpnd2 Intrinsic Graphical Illustration of _xpnd4 Intrinsic C64x Data Cross Paths Contents xiii

13 Tables Tables 1 1 Code Development Steps Status Update: Tutorial example lesson_c lesson1_c Status Update: Tutorial example lesson_c lesson1_c lesson2_c Status Update: Tutorial example lesson_c lesson1_c lesson2_c lesson3_c Status Update: Tutorial example lesson_c lesson1_c lesson2_c lesson3_c Compiler Options to Avoid on Performance Critical Code Compiler Options for Performance Compiler Options That Slightly Degrade Performance and Improve Code Size Compiler Options for Control Code Compiler Options for Information TMS320C6000 C/C++ Compiler Intrinsics Command Line Options for RTS Calls How _FAR_RTS is Defined in Linkage.h With mr Selected TMS320C6x Directives Functional Units and Operations Performed Comparison of Nonparallel and Parallel Assembly Code for Fixed-Point Dot Product Comparison of Nonparallel and Parallel Assembly Code for Floating-Point Dot Product Comparison of Fixed-Point Dot Product Code With Use of LDW Comparison of Floating-Point Dot Product Code With Use of LDDW Modulo Iteration Interval Scheduling Table for Fixed-Point Dot Product (Before Software Pipelining) Modulo Iteration Interval Scheduling Table for Floating-Point Dot Product (Before Software Pipelining) Modulo Iteration Interval Table for Fixed-Point Dot Product (After Software Pipelining) Modulo Iteration Interval Table for Floating-Point Dot Product (After Software Pipelining) Software Pipeline Accumulation Staggered Results Due to Three-Cycle Delay Comparison of Fixed-Point Dot Product Code Examples Comparison of Floating-Point Dot Product Code Examples Modulo Iteration Interval Table for Weighted Vector Sum (2-Cycle Loop) Modulo Iteration Interval Table for Weighted Vector Sum With SHR Instructions Modulo Iteration Interval Table for Weighted Vector Sum (2-Cycle Loop) Modulo Iteration Interval Table for Weighted Vector Sum (2-Cycle Loop) Resource Table for IIR Filter Modulo Iteration Interval Table for IIR (4-Cycle Loop) xiv

14 Tables 6 18 Resource Table for If-Then-Else Code Comparison of If-Then-Else Code Examples Resource Table for Unrolled If-Then-Else Code Comparison of If-Then-Else Code Examples Resource Table for Live-Too-Long Code Resource Table for FIR Filter Code Resource Table for FIR Filter Code Comparison of FIR Filter Code Comparison of FIR Filter Code Resource Table for FIR Filter Code Comparison of FIR Filter Code Packed data types Supported Operations on Packed Data Types Instructions for Manipulating Packed Data Types Unpacking Packed 16-bit Quantities to 32-bit Values Intrinsics Which Combine Multiple Operations in one Instruction Comparison Between Aligned and Non Aligned Memory Accesses Contents xv

15 Examples Examples 1 1 Compiler and/or Assembly Optimizer Feedback Stage 1 Feedback Stage 2 Feedback Stage 3 Feedback Vector Summation of Two Weighted Vectors lesson_c.c Feedback From lesson_c.asm lesson_c.asm lesson1_c.c lesson1_c.asm lesson1_c.asm lesson2_c.c lesson2_c.asm lesson2_c.asm lesson3_c.c lesson3_c.asm Profile Statistics Using the iircas4 Function in C Software Pipelining Feedback From the iircas4 C Code Rewriting the iircas4 ( ) Function in Linear Assembly Software Pipeline Feedback from Linear Assembly Basic Vector Sum Use of the Restrict Type Qualifier With Pointers Use of the Restrict Type Qualifier With Arrays Incorrect Use of the restrict Keyword Including the clock( ) Function Saturated Add Without Intrinsics Saturated Add With Intrinsics Vector Sum With restrict Keywords, MUST_ITERATE Pragma, Word Reads Vector Sum With Non aligned Word Accesses to Memory Vector Sum With restrict Keywords, MUST_ITERATE pragma, and Word Reads (Generic Version) Dot Product Using Intrinsics FIR Filter Original Form FIR Filter Optimized Form Basic Float Dot Product xvi

16 Examples 3 15 Float Dot Product Using Intrinsics Float Dot Product With Peak Performance Int Dot Product with Nonaligned Doubleword Reads Using the Compiler to Generate a Dot Product With Word Accesses Using the _nassert() Intrinsic to Generate Word Accesses for Vector Sum Using _nassert() Intrinsic to Generate Word Accesses for FIR Filter Compiler Output From Example Compiler Output From Example Compiler Output From Example Automatic Use of Word Accesses Without the _nassert Intrinsic Trip Counters Vector Sum With Three Memory Operations Word-Aligned Vector Sum Vector Sum Using const Keywords, MUST_ITERATE pragma, Word Reads, and Loop Unrolling FIR_Type2 Original Form FIR_Type2 Inner Loop Completely Unrolled Vector Sum Use of If Statements in Float Collision Detection (Original Code) Use of If Statements in Float Collision Detection (Modified Code) Referencing Far Global Objects Defined in Other Files Linear Assembly Block Copy Block copy With.mdep Linear Assembly Dot Product Linear Assembly Dot Product With.mptr Fixed-Point Dot Product C Code Floating-Point Dot Product C Code List of Assembly Instructions for Fixed-Point Dot Product List of Assembly Instructions for Floating-Point Dot Product Nonparallel Assembly Code for Fixed-Point Dot Product Parallel Assembly Code for Fixed-Point Dot Product Nonparallel Assembly Code for Floating-Point Dot Product Parallel Assembly Code for Floating-Point Dot Product Fixed-Point Dot Product C Code (Unrolled) Floating-Point Dot Product C Code (Unrolled) Linear Assembly for Fixed-Point Dot Product Inner Loop with LDW Linear Assembly for Floating-Point Dot Product Inner Loop with LDDW Linear Assembly for Fixed-Point Dot Product Inner Loop With LDW (With Allocated Resources) Linear Assembly for Floating-Point Dot Product Inner Loop With LDDW (With Allocated Resources) Assembly Code for Fixed-Point Dot Product With LDW (Before Software Pipelining) Assembly Code for Floating-Point Dot Product With LDDW (Before Software Pipelining) Contents xvii

17 Examples 6 21 Linear Assembly for Fixed-Point Dot Product Inner Loop (With Conditional SUB Instruction) Linear Assembly for Floating-Point Dot Product Inner Loop (With Conditional SUB Instruction) Pseudo-Code for Single-Cycle Accumulator With ADDSP Linear Assembly for Full Fixed-Point Dot Product Linear Assembly for Full Floating-Point Dot Product Assembly Code for Fixed-Point Dot Product (Software Pipelined) Assembly Code for Floating-Point Dot Product (Software Pipelined) Assembly Code for Fixed-Point Dot Product (Software Pipelined With No Extraneous Loads) Assembly Code for Floating-Point Dot Product (Software Pipelined With No Extraneous Loads) Assembly Code for Fixed-Point Dot Product (Software Pipelined With Removal of Prolog and Epilog) Assembly Code for Floating-Point Dot Product (Software Pipelined With Removal of Prolog and Epilog) Assembly Code for Fixed-Point Dot Product (Software Pipelined With Smallest Code Size) Assembly Code for Floating-Point Dot Product (Software Pipelined With Smallest Code Size) Weighted Vector Sum C Code Linear Assembly for Weighted Vector Sum Inner Loop Weighted Vector Sum C Code (Unrolled) Linear Assembly for Weighted Vector Sum Using LDW Linear Assembly for Weighted Vector Sum With Resources Allocated Linear Assembly for Weighted Vector Sum Assembly Code for Weighted Vector Sum IIR Filter C Code Linear Assembly for IIR Inner Loop Linear Assembly for IIR Inner Loop With Reduced Loop Carry Path Linear Assembly for IIR Inner Loop (With Allocated Resources) Linear Assembly for IIR Filter Assembly Code for IIR Filter If-Then-Else C Code Linear Assembly for If-Then-Else Inner Loop Linear Assembly for Full If-Then-Else Code Assembly Code for If-Then-Else Assembly Code for If-Then-Else With Loop Count Greater Than If-Then-Else C Code (Unrolled) Linear Assembly for Unrolled If-Then-Else Inner Loop Linear Assembly for Full Unrolled If-Then-Else Code Assembly Code for Unrolled If-Then-Else Live-Too-Long C Code Linear Assembly for Live-Too-Long Inner Loop xviii

18 Examples 6 58 Linear Assembly for Full Live-Too-Long Code Assembly Code for Live-Too-Long With Move Instructions FIR Filter C Code FIR Filter C Code With Redundant Load Elimination Linear Assembly for FIR Inner Loop Linear Assembly for Full FIR Code Final Assembly Code for FIR Filter With Redundant Load Elimination Final Assembly Code for Inner Loop of FIR Filter FIR Filter C Code (Unrolled) Linear Assembly for Unrolled FIR Inner Loop Linear Assembly for Full Unrolled FIR Filter Final Assembly Code for FIR Filter With Redundant Load Elimination and No Memory Hits Unrolled FIR Filter C Code Final Assembly Code for FIR Filter With Redundant Load Elimination and No Memory Hits With Outer Loop Software-Pipelined Unrolled FIR Filter C Code Linear Assembly for Unrolled FIR Inner Loop Linear Assembly for FIR Outer Loop Unrolled FIR Filter C Code Linear Assembly for FIR With Outer Loop Conditionally Executed With Inner Loop Linear Assembly for FIR With Outer Loop Conditionally Executed With Inner Loop (With Functional Units) Final Assembly Code for FIR Filter Code With Multiple Assignment of A Code Using Single Assignment Dot Product With MUST_ITERATE Pragma Guaranteeing Minimum Trip Count Dot Product With _nassert Guaranteeing Trip Count Range Dot Product With MUST_ITERATE Pragma Guaranteeing Trip Count Range and Factor of Dot Product With MUST_ITERATE Pragma Guaranteeing Trip Count Range and Factor of Hand-Coded Assembly ISR Hand-Coded Assembly ISR Allowing Nesting of Interrupts Vector Sum Vector Multiply Dot Product Vector Complex Multiply Vectorization: Using LDDW and STDW in Vector Sum Vector Addition (Complete) Using LDDW and STDW in Vector Multiply Using _mpy2() and _pack2() to Perform the Vector Multiply Vectorized Form of the Dot Product Kernel Vectorized Form of the Dot Product Kernel Contents xix

19 Examples 8 11 Final Assembly Code for Dot Product Kernel s Inner Loop Vectorized form of the Vector Complex Multiply Kernel Vectorized form of the Vector Complex Multiply Non aligned Memory Access With _mem4 and _memd Vector Sum Modified to use Non Aligned Memory Accesses Clear Below Threshold Kernel Clear Below Threshold Kernel, Using _cmpgtu4 and _xpnd4 Intrinsics Loop Trip Count in C Loop Trip Count in Linear Assembly without BDEC Loop Trip Count Using BDEC Loop Tip Count Using BDEC With Extra Loop Iterations Using the.call Directive in Linear Assembly Compiler Output Using ADDKPC Avoiding Cross Path Stalls: Weighted Vector Sum Example Avoiding Cross Path Stalls: Partitioned Linear Assembly Avoiding Cross Path Stalls: Vector Sum Loop Kernel Avoiding Cross Path Stalls: Assembly Output Generated for Weighted Vector Sum Loop Kernel xx

20 Chapter 1 Introduction This chapter introduces some features of the C6000 microprocessor and discusses the basic process for creating code and understanding feedback. Any reference to C6000 pertains to the C62x (fixed-point), C64x (fixed-point), and the C67x (floating-point) devices. Though most of the examples shown are fixed-point specific, all techniques are applicable to each device. Topic Page 1.1 TMS320C6000 Architecture TMS320C6000 Pipeline Code Development Flow to Increase Performance Understanding Feedback

21 TMS320C6000 Architecture / TMS320C6000 Pipeline 1.1 TMS320C6000 Architecture The C62x is a fixed-point digital signal processor (DSP) and is the first DSP to use the VelociTI architecture. VelociTI is a high-performance, advanced very-long-instruction-word (VLIW) architecture, making it an excellent choice for multichannel, multifunctional, and performance-driven applications. The C67x is a floating-point DSP with the same features. It is the second DSP to use the VelociTI architecture. The C64x is a fixed-point DSP with the same features. It is the third DSP to use the VelociTI architecture. The C6000 DSPs are based on the C6000 CPU, which consists of: Program fetch unit Instruction dispatch unit Instruction decode unit Two data paths, each with four functional units Thirty-two 32-bit registers ( C62x and C67x) Sixty-four 32-bit registers ( C64x) Control registers Control logic Test, emulation, and interrupt logic 1.2 TMS320C6000 Pipeline The C6000 pipeline has several features that provide optimum performance, low cost, and simple programming. Increased pipelining eliminates traditional architectural bottlenecks in program fetch, data access, and multiply operations. Pipeline control is simplified by eliminating pipeline locks. The pipeline can dispatch eight parallel instructions every cycle. Parallel instructions proceed simultaneously through the same pipeline phases. 1-2