A Novel Floating Point Comparator Using Parallel Tree Structure

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1 A Novel Floating Point Comparator Using Parallel Tree Structure Anuja T Samuel PG student ECE Dept,College of Engineeering, Guindy, Anna University, Chennai, Tamil Nadu, India anujatsamuel@gmail.com Jawahar Senthilkumar Associate Professor ECE Dept,College of Engineeering, Guindy, Anna University, Chennai, Tamil Nadu, India Abstract-In recent years, floating point numbers are widely adopted due to its good robustness against quantization errors and high dynamic range capabilities. In this paper, a novel single-precision floating point comparator design is proposed. A parallel prefix tree structure is literally the back bone of this comparator design. This is designed using Verilog code, simulated and synthesised using CADENCE ENCOUNTER tool with TSMC 180nm technology. The proposed comparator fully supports single precision floating-point comparisons, as defined in the IEEE 754 standard. The proposed floating point comparator design exploits the advantages of structural reusability. Cadence Encounter synthesis for a 32-b floating point comparator shows a worst case input-output delay of ns and a total power dissipation of 91.8µW using 0.18-μm TSMC technology. The replacement of NOR-NAND gate using OR gate in the decision module incurs the improvement in the performance which thereby outperforms the existing design. Keywords- Floating point number, parallel prefix tree, IEEE 754 format. I. INTRODUCTION. In Very Large Scale Integrated (VLSI) designs, comparators are the important data path elements for any general purpose architectures. The concept of floating point representations with capability of expanding it with the exponent component achieves greater range over inherently integer fixed point numbers. For an instance, to compute the distance between the galaxies, it is not necessary to keep all the 39 decimal places down to femtometre resolution while the first 9 digits which is most significant only matters. In computing, a technique for representing an approximation of a real number that can support a wide range of values is described by floating point. The word floating point refers to the fact that a number s radix point (decimal point or binary point) can float, means it can be placed anywhere relative to the significant digits of the number. Even though a variety of floating point representations have been used in computers over the years, since the 1990s, the most commonly accepted representation is that defined by the IEEE 754 standard. This standard specifies arithmetic and interchange formats and techniques for decimal and binary floating point arithmetic in computer programming environments (IEEE ). In this paper a single precision floating point comparator design is proposed. The IEEE 754 encoder design consists of a part of parallel prefix tree structure which is the key element used in the comparison resolution module. This reuse of structure leads to a prominent reduction in the area requirement. The proposed floating point comparator is a single precision IEEE754 compliant unit. The remainder of this paper is organized as follows. Section II presents the previous works related to the topic and the basic concepts. Section III is about the single precision floating point representation. Section IV covers the design details of the proposed comparator architecture and Simulation and Synthesis results are included in Section IV. Conclusions and suggestion for further improvement is given in Section V. II. RELATED PREVIOUS WORKS Comparators are the key design elements for most of the general purpose [5], application specific and signal processing architectures [6]. Even though there are previously published comparator implementations [7] - [9], these architectures often only refer to the comparator without providing concrete design details. An exception for this is the design of combined two s complement and floating point comparator [4]. Both number formats use the same novel magnitude comparator, which has logarithmic delay to save area. Since it allows the same hardware to be used to compare both two s complement and floating-point numbers, this design is useful in low-cost processors. In previously proposed binary comparator designs, both static [10], [11], and dynamic [10] designs are implemented which compares only fixed point numbers. For speed enhancement, some comparators combine a tree structure with a two phase domino clocking structure [11], [3]. After negating one input via two s complement, these designs add the two inputs. The output Carry signal is used as the greaterthan or less-than indicator (equality not supported). Since /15/$ IEEE

2 carry-out is the critical signal, the adder modules of the tree structures compute only the carry out signal for optimization. But heavy loading of the clock signal necessitates large drivers for the clock signals. Some energy-efficient architectures [13] [15] utilizes methods to reduce the switching activity. Comparison of two binary numbers one bit at a time, rippling from the most significant bit (MSB) to the least significant bit (LSB) is used by compute-on demand comparators. Each bit comparison outcome either represents the final decision of comparison if the bits are different or allows the comparison of the lower significant bit if the bits are equal. So the activation of a comparison cell is dependent only on the equivalency of all greater significant bits. Even though these architectures reduce the switching activity, for wide worst case operands they suffer from long worst case comparison delays. A new comparator is designed featuring wide-range and high-speed operation using only digital CMOS cells [1]. It utilizes a novel scalable parallel prefix tree structure that leverages the comparison outcome of the most significant bit. It precedes the operation only when the compared bits are equal towards the least significant bit. The advantage of this design is that the dynamic power dissipation is reduced while the transistor count is very high. In the proposed floating point comparator, a 6 transistor XOR gate is used for comparison and OR gate is designed for decision module which in turn reduces transistor count and power delay product. III. SINGLE PRECISION FLOATING POINT FORMAT The IEEE has standardized the computer representation of the binary floating-point numbers in IEEE 754. Almost all the modern machines are following this standard. The IEEE 754 standard defines: Arithmetic formats: sets of decimal and binary floating-point numbers, which consist of finite numbers (including signed zeros and subnormal numbers), infinities, and special "not a number" values Interchanging formats: encoding the bit strings that is used to exchange floating-point data in a compact and efficient form Operations: done on arithmetic formats Rounding rules: includes the properties to be satisfied while rounding numbers during conversions and arithmetic Handling the exceptions: indicates the exceptional conditions The IEEE single precision floating point standard representation requires a 32 bit word. The bits of it may be represented as numbered from 0 to 31, left to right shown in Fig.1. Sign Exponent Mantissa Fig.1. IEEE single precision floating point number format The format of the IEEE 754 standard consists of: Sign Bit: 1 bit sign signifies whether the floating point number is positive or negative. The positive number is indicated by 0 and negative number by 1 sign bit. Exponent: For single precision numbers, the exponent is 8 bit and it provides the exponent range from E (min) =-126 to E (max) =127 for signed a signed integer and can be an 8 bit unsigned integer from 0 to 255 which is the accepted biased form in IEEE 754 single precision definition. Mantissa: To the right of the binary point, true mantissa includes 23 fraction bits and an implicit leading bit to the left of the binary point with value 1 unless the exponent is stored with all zeros. Thus in the memory format only 23 fraction bits of the mantissa appears but the total precision is 24 bits. IV. PROPOSED DESIGN OF FLOATING POINT COMPARATOR The proposed floating point comparator is based on a parallel tree structure. The top level block diagram representation is shown in Fig.2. Decimal floating point numbers that to be compared are taken as the input to the system. The output of the system depends on the inputs. If A[31:0] input is greater than B[31:0], then the output signal G becomes high and if B[31:0] is high, the L signal goes high. Otherwise, the output signal E goes high signifies that the both input operands are equal in magnitude. INPUT: Decimal Floating Point Number Decimal to Binary Converter Decimal Part Exponent Part IEEE 754 Encoder Circuit Sign Bit Exponent Fraction Parallel Prefix Tree Comparator OUTPUT: G/L/E Fig.2. Block Diagram of proposed floating point comparator

3 A. IEEE 754 ENCODER DESIGN The input operands should be converted to the IEEE 754 standard format of floating point data. Here, a converter circuit is designed to encode the input floating point number to standard IEEE format. The conversion method for IEEE format is explained in Fig.3. Mantissa Part (Am) Exponent Part (Ae) XNA Module 8:3 Encoder IEEE 754 Encoder Input Port Select Specific bits Concatenation (Am[Q-1:0] &&Ae) Step 5: Assign the sign bit. Here sign bit is 0 because number is positive. Step 6: Group the result into 32 bit format which is in the form of sign, exponent, mantissa: Step 7: To simplify the comparator design, the sign bits of the input operands can be inverted before sending them to the magnitude comparator. This ensures the correctness of the output since if its not inverted sign bit will lead to faulty decision (0 corresponds to +ve and 1 corresponds to ve number). Both input operands first go to this conversion section and then to magnitude comparator for decision making. B. MAGNITUDE COMPARATOR SECTION The magnitude comparator design [1] is composed of two modules, comparison resolution module (CRM) and decision module (DM). The CR module is a MSB-to-LSB parallel-prefix tree structure performing bitwise comparison of two N-bit operands A and B. The block diagram representation of a 16-bit comparator is shown in Fig.4. Bias i/p 0 NOR4 NOR3 NOR2 NOR1 Sign bit (As) Exponent Inverter Fraction Concatenation To Floating point comparator A[15] B[15] A[14] B[14] NOR4 NOR3 NOR2 NOR1 A[0] B[0] Fig.3. IEEE 754 Encoder circuit The Algorithm for IEEE format conversion: For an instance, the decimal number input, Ad= Step 1: Convert decimal valued input into binary value which is Ab= Now Am= and Ae= Step 2: Move the radix point to the left such that there will be only one bit towards the left of the radix point in Am and this bit must be 1. Thus, Am becomes XNA Module: For this process, the Am input is given to the XNA module first, which is same as that using in the CRM and then to an 8:3 encoder section. This will give us the number of times that the radix point should be shifted (say q). Here there is 3 times shifting of radix point to the left i.e. q=3 Step 3: Add q value to 127 (bias value) to get the exponent value i.e. original exponent value is bias value + q. e= = 130 = and this is the Exponent part of floating point number. Step 4: Concatenate the number which is after the radix point and Ae is concatenated to get the mantissa part which is XOR15 XOR14.. XOR0 XOR Block A15 A14.. A0 A[15] B[15] A[14] B[14 AND Block A[0] B[0] M15 M14. M0 OR1 OR2 G L NOR E Fig.4. Block Diagram for 16-bit comparison

4 The parallel prefix tree structure [2] is divided into five hierarchical prefixing sets, where each group performs specific function whose output serves as input to the next group, and the fifth group produces the output on the right bus and the left bus. All cells within each group operate in parallel. Group 1 which performs XOR operation compares the N-bit operands A and B bit-by-bit, using a single level of N number of XOR gates. Group 2 comprises of NOR gates, which combine the termination flags for each of the four gates from group 1 to limit the fan-in and fan-out to a maximum of four. The group 2 cells either continue the comparison for bits of lesser significance if all four inputs are 0s, or terminate the comparison if a final decision can be made. Group 3 consists of NOR gates that has more logic levels compared to group 2 and with different inputs. It provides no comparison functionality; the sole purpose of group 3 is to limit the fan-in and fan-out regardless of operand bit width. Group 4 consists of AND gates, whose outputs control the select inputs of two-input multiplexors in group 5, which in turn drive both the left bus and the right bus. Group 5 consists of two-input, 2-b wide multiplexers. One input is (An, Bn) and the other is hardwired to 00. We define the 2-b as the leftbit code (An) and the right-bit code (Bn), where all left-bit codes and all right-bit codes combine to form the left bus and the right bus, respectively. The proposed comparator computes the output bits G, L or E by OR-ing all left bits and all right bits separately, as shown in the decision module (Fig.1), using an OR-NOR gate network, unlike in [1] where a NOR-NAND-NOR network is used. Table II. Comparison Table for Area(µ ) Design 8-bit 16-bit 32-bit Existing [1] Modified Fig.6. Area comparison chart Table III. Comparison Table for Delay(ns) Design 8-bit 16-bit 32-bit Existing [1] Modified VI. SIMULATION AND SYNTHESIS RESULTS The 8,16 bit and 32 bit binary comparator is designed and simulated using NOR-NAND network in DM as in [1] and using OR gate (proposed modification). The power, area and delay comparisons of both designs are given in Table. I, Table. II and Table. III. and in Fig.5, Fig.6 and Fig.7. Table I. Comparison Table for Power Design 8-bit 16-bit 32-bit Existing [1] Modified Fig.7. Delay comparison chart The comparison of the above results clearly shows that the proposed modification in the design leads to a prominent improvement in the system performance. Even though there is a slight penalty in delay for 32-bit comparator, the area and power minimizes, which leads to improved power delay product performance. The proposed architecture of single precision floating point comparator using zero detectors in DM is designed and simulated using Digital Cadence tool with TSMC 180nm library. The SimVision window showing the simulation output is given in Fig.8. Fig.5 Power comparison chart

5 The Encounter RTL compiler tool also generated the worst case delay report, power report including both dynamic and leakage power and area report. These power (leakage and dynamic), area and delay estimates are concluded in the below given Table. IV. Fig.8. Simulation output of the comparator After simulation, synthesis is performed with the Encounter RTL compiler. The worst case delay is estimated for the critical path when both the inputs are equal in magnitude. This critical path for the worst case input is shown in Fig.9. For the single precision comparator worst case path is from input port bd [5] (5 th bit in the decimal part of input b) to equal output port. This is the longest path which is responsible for the worst case delay of the system. Table. IV Consolidated results Estimates Value Leakage Power.11µW Dynamic Power µW Worst case delay 3.041ns Cell Area The design of the proposed floating point comparator is implemented in various devices such as Virtex-6 XC6VHX255T and Cyclone II EP2C35F672C6 to verify the working. The synthesis results of both the devices are tabulated in Table. V. for comparison. Table. V Device Synthesis Comparison Device Logic Cells No. of IO pins tpd(ns) Cyclone-II EP2C35F672C6 54/33,216 (.16%) 133/475 (33%) 14.66ns Virtex-6 XC6VHX255T 66/ 15,8400 (.042%) 133/440 (30%) 4.338ns VIII. CONCLUSION Fig.9. Critical path for worst case input The RTL diagram of the single precision floating point comparator obtained is shown in Fig. 10. This paper proposes the design of a novel single precision floating point comparator. The proposed modification in the design incurs the maximized performance over conventional design. Power, area and delay estimates are shown for IEEE 754 compliant single precision comparator using Digital Cadence tool with TSMC 180nm technology. Results indicate that the proposed comparator can be used in low power high speed systems. Since the proposed design is scalable we could use the same concept for double precision floating point numbers as further improvement. REFERENCES [1] S. A. Hafeez, A. G. Ross and B. Parhami, Fellow IEEE Scalable Digital CMOS Comparator Using a Parallel Prefix Tree, IEEE Transaction on Very Large Scale Integration (VLSI) Systems November, [2] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs, 2nd ed. New York: Oxford, [3] F. Frustaci, S. Perri, M. Lanuzza, and P. Corsonello, Energyefficient single-clock-cycle binary comparator, Int. J. Circuit Theory Appl., vol. 40, no. 3, pp , Mar [4] J. E. Stine and M. J. Schulte, A combined two s complement and floating-point comparator, in Proc. Int. Symp. Circuits Syst., vol , pp Fig.10. RTL diagram [5] J. L. Hennessy and D. A. Patterson, Computer Architecture a Quantitative Approach. Morgan Kaufmann Publishers, 2002.

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