Review: Summary of Pipelining Basics

Transcription

1 Review: ummary of Pipelining asics C152 Computer Architecture and Engineering Lecture 14 Pipelining Control Continued Introduction to Advanced Pipelining October 18, 1999 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) Pipelines pass control information down the pipe just as data moves down pipe Foarding/talls handled by local control Hazards limit performance tructural: need more HW resources ata: need foarding, compiler scheduling Control: early evaluation &, delayed branch, prediction Increasing length of pipe increases impact of hazards; pipelining helps instruction bandwidth, not latency lecture slides: Lec14.1 Lec14.2 Recap: Pipeline Hazards Recap: Pipelined Processor for slides I-Fet ch C OpFetch OpFetch tore tructural Hazard IFetch C Inst. Valid cd ex ubbles talls Ex mem wb I-Fet ch C OpFetch Jump IF C EX IFetch C IF C EX IF C EX Control Hazard RAW (read after write) ata Hazard WAW ata Hazard (write after write) IF C OF Ex IF C OF Ex R WAR ata Hazard (write after read) Lec14.3 Next eparate control at each stage talls propagate backwards to freeze previous stages ubbles in pipeline introduced by placing Noops into local stage, stall previous stages. A ata. Equal Lec14.4

2 The ig Picture: Where are We Now The Five Classic Components of a Computer Processor Input Control ory atapath Output Recap: ata tationary Control The ain Control generates the control signals during /ec Control signals for (ExtOp, ALUrc,...) are used 1 cycle later Control signals for (Wr ranch) are used 2 cycles later Control signals for Wr (to Wr) are used 3 cycles later /ec Wr Today s Topics: Recap last lecture Review IP R3000 pipeline Administrivia Advanced Pipelining upercalar, VLIW/EPIC IF/I ister ain Control ExtOp ALUrc ALUOp st W ranch r to Wr I/Ex ister ExtOp ALUrc ALUOp st W ranch r to Wr Ex/ ister W rranch to Wr /Wr ister to Wr Lec14.5 Lec14.6 atapath + ata tationary Control Let s Try it Out Inst. fun op rs rt ecode rs rt v wb me ex im A v wb me v wb ata. 10 lw r1, r2(3 14 addi r2, r2, 3 20 sub r3, r4, r5 30 ori r8, r9, 17 these addresses are octal Next Lec14.7 Lec14.8

3 tart: Fetch 10 Inst. n n n n ecode rs rt im Fetch 14, ecode 10 Inst. lw r1, r2(3 ecode 2 rt n n n im Next A 10 ata IF. 10 lw r1, r2(3 14 addi r2, r2, 3 20 sub r3, r4, r5 30 ori r8, r9, 17 Next A 14 ata I IF. 10 lw r1, r2(3 14 addi r2, r2, 3 20 sub r3, r4, r5 30 ori r8, r9, 17 Lec14.9 Lec14.10 Fetch 20, ecode 14, 10 Inst. addi r2, r2, 3 ecode 2 rt lw r1 35 n n Fetch 24, ecode 20, 14, 10 Inst. sub r3, r4, r5 ecode 4 5 addi r2, r2, 3 3 lw r1 n Next r2 20 ata. EX 10 lw r1, r2(3 I 14 addi r2, r2, 3 IF 20 sub r3, r4, r5 30 ori r8, r9, 17 Next r2 24 r2+35 ata. 10 lw r1, r2(3 EX 14 addi r2, r2, 3 I 20 sub r3, r4, r5 IF 30 ori r8, r9, 17 Lec14.11 Lec14.12

4 Fetch 30, cd 24, Ex 20, 14, 10 Inst. beq r6, r7 100 ecode 6 7 Next sub r3 r4 r5 30 r2+3 ata Note elayed ranch: always execute ori after beq addi r2 lw r1 [r2+35]. 10 lw r1, r2(3 14 addi r2, r2, 3 EX 20 sub r3, r4, r5 I IF 30 ori r8, r9, 17 Lec14.13 Fetch 100, cd 30, Ex 24, 20, 14 Inst. ori r8, r9 17 ecode 9 xx Next beq 100 r6 r7 100 sub r3 r4-r5 addi r2 r2+3 ata. r1[r2+35] 10 lw r1, r2(3 14 addi r2, r2, 3 20 sub r3, r4, r5 EX I 30 ori r8, r9, 17 IF Lec14.14 Fetch 104, cd 100, Ex 30, 24, 20 Fetch 110, cd 104, Ex 100, 30, 24 Inst. ecode Inst. ecode Next ata. 10 lw r1, r2(3 14 addi r2, r2, 3 20 sub r3, r4, r5 EX 30 ori r8, r9, 17 Next ata. 10 lw r1, r2(3 14 addi r2, r2, 3 20 sub r3, r4, r5 30 ori r8, r9, 17 Fill it in yourself! I Lec14.15 Fill it in yourself! EX Lec14.16

5 Fetch 114, cd 110, Ex 104, 100, 30 Inst. ecode. Administrivia ail Lab 5 breakdowns to your TAs by tonight! Get started on Lab 5: Pipelining is difficult to get right! e sure that we will test gotcha cases in our mystery programs Wednesday: advanced pipelining Out-of-order execution/register renaming Reorder buffers ata 10 lw r1, r2(3 14 addi r2, r2, 3 Next 20 sub r3, r4, r5 30 ori r8, r9, 17 Fill it in yourself! Lec14.17 Lec14.18 Recap: ata Hazards Hazard etection Avoid some by design eliminate WAR by always fetching operands early (C) in pipe eleminate WAW by doing all s in order (last stage, static) etect and resolve remaining ones stall or foard (if possible) uppose instruction i is about to be issued and a predecessor instruction j is in the instruction pipeline. A RAW hazard exists on register ρ if ρ Rregs( i ) Wregs( j ) Keep a record of pending writes (for inst s in the pipe) and compare with operand regs of current instruction. When instruction issues, reserve its result register. When on operation completes, remove its write reservation. IF C EX RAW ata Hazard IF C EX WAW ata Hazard IF C EX IF C OF Ex IF C OF Ex R RAW ata Hazard A WAW hazard exists on register ρ if ρ Wregs( i ) Wregs( j ) A WAR hazard exists on register ρ if ρ Wregs( i ) Rregs( j ) Lec14.19 Lec14.20

6 Record of Pending Writes In Pipeline isters Resolve RAW by foarding (or bypassing) s alu mem m s IAU npc I mem op rs rt A im n op n op n op Current operand registers Pending writes hazard < ((rs ex) & regw ex ) OR ((rs mem) & regw me ) OR ((rs & regw wb) wb ) OR ((rt & regw ex) ex ) OR ((rt & regw mem) me ) OR ((rt wb ) & regw wb ) Lec14.21 s Foard mux alu mem m IAU npc I mem op rs rt A im n op n op n op s etect nearest valid write op operand register and foard into op latches, bypassing remainder of the pipe Increase muxes to add paths from pipeline registers ata Foarding ata ypassing Lec14.22 What about memory operations Compiler Avoiding Load talls: º If instructions are initiated in order and operations always occur in the same stage, there can be no hazards between memory operations! op Rd Ra Rb º What does delaying on arithmetic operations cost cycles hardware º What about data dependence on loads R1 <- R4 + R5 R2 <- [ R2 + I ] R3 <- R2 + R1 elayed Loads º Can recognize this in decode stage and introduce bubble while stalling fetch stage (hint for lab 5!) º Tricky situation: R1 <- [ R2 + I ] [R3+34] <- R1 Handle with bypass in memory stage! op Rd Ra Rb Rd Rd to reg file A T R scheduled unscheduled 54% gcc 31% 42% spice 14% 65% tex 25% 0% 20% 40% 60% 80% % loads stalling pipeline Lec14.23 Lec14.24

7 What about Interrupts, Traps, Faults External Interrupts: Allow pipeline to drain, Load with interrupt address Faults (within instruction, restartable) Force trap instruction into IF disable writes till trap hits must save multiple s or + state Recall: Precise Exceptions tate of the machine is preserved as if program executed up to the offending instruction All previous instructions completed Offending instruction and all following instructions act as if they have not even started ame system code will work on different implementations Exception/Interrupts: Implementation questions 5 instructions, executing in 5 different pipeline stages! Who caused the interrupt tage Problem interrupts occurring IF Page fault on instruction fetch; misaligned memory access; memory-protection violation I Undefined or illegal opcode EX Arithmetic exception E Page fault on data fetch; misaligned memory access; memory-protection violation; memory error How do we stop the pipeline How do we restart it o we interrupt immediately or wait How do we sort all of this out to maintain preciseness Lec14.25 Lec14.26 Exception Handling s alu mem m IAU npc I mem lw $2,20($ A im n op s Excp detect bad instruction address detect bad instruction Excp Excp Excp detect overflow detect bad data address Allow exception to take effect Lec14.27 Another look at the exception problem Time ata TL ad Inst Inst TL fault Overflow Program Flow IFetch cd Use pipeline to sort this out! IFetch cd IFetch cd Pass exception status along with instruction. Keep track of s for every instruction in pipeline. on t act on exception until it reache stage Handle interrupts through faulting noop in IF stage When instruction reaches end of E stage: ave E, Interrupt vector addr Turn all instructions in earlier stages into noops! IFetch cd Lec14.28

8 Resolution: Freeze above & ubble elow FYI: IP R3000 clocking discipline s IAU npc I mem op rs rt bubble freeze phi1 phi2 2-phase non-overlapping clocks Pipeline stage is two (level sensitive) latches A im n op alu mem m n op n op Flush accomplished by setting invalid bit in pipeline Edge-triggered phi1 phi2 phi1 s Lec14.29 Lec14.30 IP R3000 Instruction Pipeline Recall: ata Hazard on r1 Inst Fetch ecode. Read ALU / E.A ory Write TL I-Cache RF Operation Resource Usage TL I-cache RF TL ALUALU E.A. TL -Cache -Cache I n s t r. O r d e r Time (clock cycles) IF I/RF EX E add r1,r2,r3 sub r4,r1,r3 and r6,r1,r7 or r8,r1,r9 xor r10,r1,r11 ALU Im m ALU Im m ALU Im m Im ALU m ALU Im m Write in phase 1, read in phase 2 > eliminates bypass from With IP R3000 pipeline, no need to foard from stage Lec14.31 Lec14.32

9 IP R3000 ulticycle Operations Is CPI 1 for our pipeline op Rd Ra Rb Use control word of local stage to step through multicycle operation Remember that CPI is an Average # cycles/inst mul Rd Ra Rb A tall all stages above multicycle operation in the pipeline rain (bubble) stages below it IFetch cd IFetch cd IFetch cd Rd Rd to reg file Ex: ultiply, ivide, Cache iss R T Alternatively, launch multiply/divide to autonomous unit, only stall pipe if attempt to get result before ready - This means stall mflo/mfhi in decode stage if multiply/divide still executing - Extra credit in Lab 5 does this Lec14.33 CPI here is 1, since the average throughput is 1 instruction every cycle. What if there are stalls or multi-cycle execution Usually CPI > 1. How close can we get to 1 IFetch cd Lec14.34 Case tudy: IP R4000 (200 Hz) Case tudy: IP R tage Pipeline: IF first half of fetching of instruction; selection happens here as well as initiation of instruction cache access. I second half of access to instruction cache. RF instruction decode and register fetch, hazard checking and also instruction cache hit detection. EX execution, which includes effective address calculation, ALU operation, and branch target computation and condition evaluation. F data fetch, first half of access to data cache. second half of access to data cache. TC tag check, determine whether the data cache access hit. write back for loads and register-register operations. 8 tages: What is impact on Load delay ranch delay Why 7:2&\FOH /RG/WHQF\ 7+5((&\FOH %UQFK/WHQF\ FRQGLWLRQVHYOXWHG GXULQJKVH 'HO\VORWOXVWZRVWOOV %UQFKOLNHO\FQFHOVGHO\VORWLIQRWWNHQ '6 '6 7& '6 7& '6 :% 7& '6 :% 7& '6 Lec14.35 Lec14.36

10 IP R4000 Floating Point FP Adder, FP ultiplier, FP ivider Last step of FP ultiplier/ivider uses FP Adder HW 8 kinds of stages in FP units: tage Functional unit escription A FP adder antissa A stage FP divider ivide pipeline stage E FP multiplier Exception test stage FP multiplier First stage of multiplier N FP multiplier econd stage of multiplier R FP adder Rounding stage FP adder Operand shift stage U Unpack FP numbers IP FP Pipe tages FP Instr Add, ubtract U +A A+R R+ ultiply U E+ N N+A R ivide U A R 28 +A +R, +R, +A, +R, A, R quare root U E (A+R) 108 A R Negate U Absolute value U FP compare U A R tages: First stage of multiplier A antissa A stage N econd stage of multiplier ivide pipeline stage R Rounding stage E Exception test stage Operand shift stage U Unpack FP numbers Lec14.37 Lec14.38 R4000 Performance Improving Instruction Level Parallelism (ILP) Not ideal CPI of 1: Load stalls (1 or 2 clock cycles) ranch stalls (2 cycles + unfilled slots) FP result stalls: RAW data hazard (latency) FP structural stalls: Not enough FP hardware (parallelism) eqntott espresso gcc li doduc nasa7 ora spice2g6 su2cor tomcatv ILP: Overlap execution of unrelated instructions gcc 17% control transfer 5 instructions + 1 branch eyond single block to get more instruction level parallelism Loop level parallelism one opportunity First W, then HW approaches LX Floating Point as example easurements suggests R4000 performance FP execution has room for improvement ase Load stalls ranch stalls FP result stalls FP structural stalls Lec14.39 Lec14.40

11 FP Loop: Where are the Hazards Loop: L F0,0(R1) ;F0vector element A F4,F0,F2 ;add scalar from F2 0(R1),F4 ;store result UI R1,R1,8 ;decrement pointer 8 (W) NEZ R1,Loop ;branch R1!zero NOP ;delayed branch slot,qvwuxfwlrq,qvwuxfwlrq /WHQF\LQ URGXFLQJUHVXOW XVLQJUHVXOW FORFNF\FOHV )3$/8R $QRWKHU)3$/8R )3$/8R 6WRUHGRXEOH /RGGRXEOH )3$/8R /RGGRXEOH 6WRUHGRXEOH,QWHJHUR,QWHJHUR :KHUHUHWKHVWOOV" Lec14.41 FP Loop howing talls 1 Loop: L F0,0(R1) ;F0vector element 2 stall 3 A F4,F0,F2 ;add scalar in F2 4 stall 5 stall 6 0(R1),F4 ;store result 7 UI R1,R1,8 ;decrement pointer 8 (W) 8 NEZ R1,Loop ;branch R1!zero 9 stall ;delayed branch slot,qvwuxfwlrq,qvwuxfwlrq /WHQF\LQ URGXFLQJUHVXOW XVLQJUHVXOW FORFNF\FOHV )3$/8R $QRWKHU)3$/8R )3$/8R 6WRUHGRXEOH /RGGRXEOH )3$/8R 9 clocks: Rewrite code to minimize stalls Lec14.42 Revised FP Loop inimizing talls Unroll Loop Four Times (straightfoard way) 1 Loop: L F0,0(R1) 2 stall 3 A F4,F0,F2 4 UI R1,R1,8 5 NEZ R1,Loop ;delayed branch 6 8(R1),F4 ;altered when move past UI 6Z%1(QG6'E\FKQJLQJGGUHVVRI6',QVWUXFWLRQ,QVWUXFWLRQ /WHQF\LQ URGXFLQJUHVXOW XVLQJUHVXOW FORFNF\FOHV )3$/8R $QRWKHU)3$/8R )3$/8R 6WRUHGRXEOH /RGGRXEOH )3$/8R 6 clocks: Unroll loop 4 times code to make faster 1 Loop:L F0,0(R1) F\FOHVWOO 2 A F4,F0,F2 F\FOHVVWOO 3 0(R1),F4 ;drop UI & NEZ 4 L F6,-8(R1) 5 A F8,F6,F2 6-8(R1),F8 ;drop UI & NEZ 7 L F10,-16(R1) 8 A F12,F10,F2 9-16(R1),F12 ;drop UI & NEZ 10 L F14,-24(R1) 11 A F16,F14,F (R1),F16 13 UI R1,R1,#32 ;alter to 4*8 14 NEZ R1,LOOP 15 NOP Rewrite loop to minimize stalls [ FORFNF\FOHVRUHULWHUWLRQ $VVXPHV5LVPXOWLOHRI Lec14.43 Lec14.44

12 Unrolled Loop That inimizes talls Getting CPI < 1: Issuing ultiple Instructions/Cycle 1 Loop:L F0,0(R1) 2 L F6,-8(R1) 3 L F10,-16(R1) 4 L F14,-24(R1) 5 A F4,F0,F2 6 A F8,F6,F2 7 A F12,F10,F2 8 A F16,F14,F2 9 0(R1),F4 10-8(R1),F (R1),F12 12 UI R1,R1,#32 13 NEZ R1,LOOP 14 8(R1),F16 ; FORFNF\FOHVRUHULWHUWLRQ :KHQVIHWRPRYHLQVWUXFWLRQV" What assumptions made when moved code OK to move store past UI even though changes register OK to move loads before stores: get right data When is it safe for compiler to do such changes Two main variations: uperscalar and VLIW uperscalar: varying no. instructions/cycle (1 to 6) Parallelism and dependencies determined/resolved by HW I Power 604, un Ultraparc, EC Alpha 21164, HP 7100 Very Long Instruction Words (VLIW): fixed number of instructions (16) parallelism determined by compiler Pipeline is exposed; compiler must schedule delays to get right result Explicit Parallel Instruction Computer (EPIC)/ Intel 128 bit packets containing 3 instructions (can execute sequentially) Can link 128 bit packets together to allow more parallelism Compiler determines parallelism, HW checks dependencies and fowards/stalls Lec14.45 Lec14.46 Getting CPI < 1: Issuing ultiple Instructions/Cycle Unrolled Loop that inimizes talls for calar uperscalar LX: 2 instructions, 1 FP & 1 anything else Fetch 64-bits/clock cycle; Int on left, FP on right Can only issue 2nd instruction if 1st instruction issues ore ports for FP registers to do FP load & FP op in a pair Type Pipetages Int. instruction IF I EX E FP instruction IF I EX E Int. instruction IF I EX E FP instruction IF I EX E Int. instruction IF I EX E FP instruction IF I EX E 1 cycle load delay expands to 3 instructions in instruction in right half can t use it, nor instructions in next slot Lec Loop: L F0,0(R1) L to A: 1 Cycle 2 L F6,-8(R1) A to : 2 Cycles 3 L F10,-16(R1) 4 L F14,-24(R1) 5 A F4,F0,F2 6 A F8,F6,F2 7 A F12,F10,F2 8 A F16,F14,F2 9 0(R1),F4 10-8(R1),F (R1),F12 12 UI R1,R1,#32 13 NEZ R1,LOOP 14 8(R1),F16 ; clock cycles, or 3.5 per iteration Lec14.48

13 Loop Unrolling in uperscalar Limits of uperscalar Integer instruction FP instruction Clock cycle Loop: L F0,0(R1) 1 L F6,-8(R1) 2 L F10,-16(R1) A F4,F0,F2 3 L F14,-24(R1) A F8,F6,F2 4 L F18,-32(R1) A F12,F10,F2 5 0(R1),F4 A F16,F14,F2 6-8(R1),F8 A F20,F18,F2 7-16(R1),F (R1),F16 9 UI R1,R1,#40 10 NEZ R1,LOOP 11-32(R1),F20 12 Unrolled 5 times to avoid delays (+1 due to ) 12 clocks, or 2.4 clocks per iteration Lec14.49 While Integer/FP split is simple for the HW, get CPI of 0.5 only for programs with: Exactly 50% FP operations No hazards If more instructions issue at same time, greater difficulty of decode and issue Even 2-scalar > examine 2 opcodes, 6 register specifiers, & decide if 1 or 2 instructions can issue VLIW: tradeoff instruction space for simple decoding The long instruction word has room for many operations y definition, all the operations the compiler puts in the long instruction word can execute in parallel E.g., 2 integer operations, 2 FP ops, 2 ory refs, 1 branch - 16 to 24 bits per field > 7*16 or 112 bits to 7*24 or 168 bits wide Need compiling technique that schedules across several branches Lec14.50 Loop Unrolling in VLIW ory ory FP FP Int. op/ Clock reference 1 reference 2 operation 1 op. 2 branch L F0,0(R1) L F6,-8(R1) 1 L F10,-16(R1) L F14,-24(R1) 2 L F18,-32(R1) L F22,-40(R1) A F4,F0,F2 A F8,F6,F2 3 L F26,-48(R1) A F12,F10,F2 A F16,F14,F2 4 A F20,F18,F2 A F24,F22,F2 5 0(R1),F4-8(R1),F8 A F28,F26,F2 6-16(R1),F12-24(R1),F (R1),F20-40(R1),F24 UI R1,R1,#48 8-0(R1),F28 NEZ R1,LOOP 9 Unrolled 7 times to avoid delays 7 results in 9 clocks, or 1.3 clocks per iteration Need more registers in VLIW(EPIC > 128int + 128FP) oftware Pipelining Observation: if iterations from loops are independent, then can get more ILP by taking instructions from different iterations oftware pipelining: reorganizes loops so that each iteration is made from instructions chosen from different iterations of the original loop (- Tomasulo in W) oftwarepipelined iteration Iteration 0 Iteration 1 Iteration 2 Iteration 3 Iteration 4 Lec14.51 Lec14.52

14 oftware Pipelining Example efore: Unrolled 3 times 1 L F0,0(R1) 2 A F4,F0,F2 3 0(R1),F4 4 L F6,-8(R1) 5 A F8,F6,F2 6-8(R1),F8 7 L F10,-16(R1) 8 A F12,F10,F2 9-16(R1),F12 10 UI R1,R1,#24 11 NEZ R1,LOOP ymbolic Loop Unrolling aximize result-use distance Less code space than unrolling Fill & drain pipe only once per loop After: oftware Pipelined 1 0(R1),F4 ; tores [i] 2 A F4,F0,F2 ; Adds to [i-1] 3 L F0,-16(R1); Loads [i-2] 4 UI R1,R1,#8 5 NEZ R1,LOOP W Pipeline Time Loop Unrolled Time vs. once per each unrolled iteration in loop unrolling overlapped ops Lec14.53 oftware Pipelining with Loop Unrolling in VLIW ory ory FP FP Int. op/ Clock reference 1 reference 2 operation 1 op. 2 branch L F0,-48(R1) T 0(R1),F4 A F4,F0,F2 1 L F6,-56(R1) T -8(R1),F8 A F8,F6,F2 UI R1,R1,#24 2 L F10,-40(R1) T 8(R1),F12 A F12,F10,F2 NEZ R1,LOOP 3 oftware pipelined across 9 iterations of original loop In each iteration of above loop, we: - tore to m,m-8,m-16 (iterations I-3,I-2,I-1) - Compute for m-24,m-32,m-40 (iterations I,I+1,I+2) - Load from m-48,m-56,m-64 (iterations I+3,I+4,I+ 9 results in 9 cycles, or 1 clock per iteration Average: 3.3 ops per clock, 66% efficiency Note: Need less registers for software pipelining (only using 7 registers here, was using 1 Lec14.54 Trace cheduling Parallelism across IF branches vs. LOOP branches Two steps: Trace election - Find likely sequence of basic blocks (trace) of (statically predicted or profile predicted) long sequence of straight-line code Trace Compaction - queeze trace into few VLIW instructions - Need bookkeeping code in case prediction is wrong Compiler undoes bad guess (discards values in registers) ubtle compiler bugs mean wrong answer vs. pooer performance; no hardware interlocks ummary Hazards limit performance tructural: need more HW resources ata: need foarding, compiler scheduling Control: early evaluation &, delayed branch, prediction ata hazards must be handled carefully: RAW data hazards handled by foarding WAW and WAR hazards don t exist in 5-stage pipeline IP I instruction set architecture made pipeline visible (delayed branch, delayed load) Exceptions in 5-stage pipeline recorded when they occur, but acted on only at (end of E) stage ust flush all previous instructions ore performance from deeper pipelines, parallelism Lec14.55 Lec14.56