ENCM 501 Winter 2015 Tutorial for Week 5

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1 ENCM 501 Winter 2015 Tutorial for Week 5 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 11 February, 2015

2 ENCM 501 Tutorial 11 Feb 2015 slide 2/11 Goals for today Do some calculations related to related to actual and potential memory system capacities. Examine some details of the cache structure presented in Slide Set 4, and look at the effects of changing some of its design parameters.

3 ENCM 501 Tutorial 11 Feb 2015 slide 3/11 Most of the cost of a DIMM comes from the DRAM chips The title of this slide is a quote from Assignment 4. That assertion was made without any supporting evidence. Assignment 4 also says, A current [retail] price for desktop memory is about $160 for a 2-module kit with a total capacity of 16 GB, which is true, according to prices given on several large vendors web sites. What kind of related evidence would support the assertion that most of the cost of a DIMM comes from the DRAM chips?

4 ENCM 501 Tutorial 11 Feb 2015 slide 4/11 Virtual address spaces on x86-64 On current x86-64 processors, registers containing addresses are 64 bits wide, and address arithmetic is done with 64-bit integers. But in circuits like TLBs, caches, and DRAM controllers, addresses are not that wide. The virtual address space available to 64-bit Linux and Mac OS X applications runs from 0x to 0x0000 7fff ffff ffff. What is the size in GB of this virtual address space? (Remark: The default virtual address space for 64-bit Windows is smaller, but still huge compared to current DRAM capacities.)

5 ENCM 501 Tutorial 11 Feb 2015 slide 5/11 Tags in set-associative caches (1) Addresses are split like this for access to a set-associative cache: search tag index block offset Each data block is supported by a dirty bit, valid bit and stored tag: D V stored tag data block In cache access, how is the index used? What is the point of comparing the search tag to all the stored tags in a set? (By the way, you can think of a direct-mapped cache as 1-way set-associative!)

6 ENCM 501 Tutorial 11 Feb 2015 slide 6/11 Tags in set-associative caches (2) Suppose the example cache of Slide Set 4 is used in a system in which DRAM addresses range from 0x to 0x3fff ffff. What is the capacity of the DRAM system? How many different possible bit patterns could be written into a stored tag when the cache and DRAM are operating?

7 ENCM 501 Tutorial 11 Feb 2015 slide 7/11 General structure of a set-associative cache (1) Does the number of sets have to be a power of two? Why or why not? Does the number of ways have to be a power of two? Why or why not? Does the block size have to be a power of two? Why or why not?

8 ENCM 501 Tutorial 11 Feb 2015 slide 8/11 General structure of a set-associative cache (2) Addresses were split this way in the example cache: block search tag index offset This split would allow correct operation of a similar 2-way cache with the same capacity and block size, but would be horrible for performance: 31 index search tag What is so bad about the above address split? block offset

9 ENCM 501 Tutorial 11 Feb 2015 slide 9/11 Changes of sizes in the example 2-way cache Suppose we cut the block size in half, to 256 bits. To maintain the same capacity, what are all the necessary changes? Suppose we want to keep the block size at 512 bits, and double the overall cache capacity. What are all the necessary changes?

10 ENCM 501 Tutorial 11 Feb 2015 slide 10/11 N-way set associativity: 4 or more ways Suppose we want to maintain capacity, but have 3-way set-associativity. Why is this impossible? What changes are there to tag and index sizes if we maintain capacity and block size, and go to 4 ways? How much of an effect does that have on the total number of bits needed for tag storage? How many bits per set would be needed to perfectly track LRU information within each set?

11 ENCM 501 Tutorial 11 Feb 2015 slide 11/11 Adjusting set associativity to manipulate index width. Suppose we want to maintain capacity and block size, and for some reason we really want the index and block offset fields to fit into bits 11 0 of an address. What should N, the number of ways be?

Slide Set 5. for ENCM 501 in Winter Term, Steve Norman, PhD, PEng

Slide Set 5. for ENCM 501 in Winter Term, Steve Norman, PhD, PEng Slide Set 5 for ENCM 501 in Winter Term, 2017 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Winter Term, 2017 ENCM 501 W17 Lectures: Slide