RTL Fast Convolution using the Mersenne Number Transform

Transcription

1 RTL Fast Convolution using the Mersenne Number Transform Oscar N. Bria and Horacio A. Villagarcía CeTAD - - Argentina Abstract VHDL is a versatile high level language for the secification and simulation of hardware comonents. Here a functional VHDL model is resented for erforming fast convolution based on Mersenne's number theoretic transform. For filtering a rather long inut sequence x( n) we can decomosed it into a number of short segments, each of which can be rocessed individually. The outut y( n) then becomes a combination of artial convolutions. The suerosition rincile for linear oerators is used here. Each artial convolution can be solved using the Discrete Fourier Transform (DFT) imlementing a fast FFT (Fast Fourier Transform) algorithm. This DFT aroach is the most oular. In this aer we use the Mersenne Number Transform (MNT) as an alternative for the DFT in the framework of a register transfer level (RTL) imlementation of the filter oeration. Even when the MNT does not have a fast algorithm it can be see that RTL in the natural level of abstraction for the imlementation of the MNT. This work is conceived as art of an academic exercise in the use of VHDL for modeling a DSP algorithm all the way from the mathematical secification to the circuit imlementation. Deartamento de Informática - Facultad de Ciencias Exactas 1

2 Introduction VHDL can be used in the first stes of circuit design as a model descrition tool [RTWG]. Here VHDL is used for functional modeling a method: the use of the Mersenne number transform for comuting integer circular convolution (ICC). Convolution, in articular ICC, is basic for many DSP alications [OSc]. Besides the direct imlementation, DFT based aroaches (using FFT) are the most oular. The DFT is just one of the block transforms with the aealing convolution roerty. But the FFT aroach have the following drawbacks: The FFT is formulated for comlex sequences. Some tricks are available for real sequences but lead to comlications in rocedure. The FFT uses comutations involving weighting factor that are irrational numbers. There is an inherent need to tolerate aroximation. Most of the multilications needed in comuting the FFT are not by ``easy'' numbers. Number-theoretic transforms are based on comutations in a finite ring, and can be used to comute convolutions and correlations. In articular, the MNT has the following ``good'' roerties [PRFN]: MNT involves multilications that are only by factors of the form 2 r. Then multilication is solved by rotating the bits in the datum by r bit ositions. This means a traditional rotate oeration over a shift-register. MNT involves additions that are module M (a Mersenne number). It can be solved using one's comlement arithmetic 1. Multily two MNTs together, Ck = Ak Bk is not more logically comlex than ordinary multilication. Those roerties suggest than the MNT is naturally well suited for ASIC/FPGA VLSI maing. Even when a functional descrition is resented here, a artitioning guideline has to be adoted. here an object based to-down (OBTD) aroach is used for artitioning the model into sub-ieces. Mersenne Number Transform In this section we follow Proakis et. al. [PRFN]. Two sequences a n and b n can be convoluted by first ``transforming'' a n and b n, then multilying the transforms together oint to oint, and finally inverse transforming the roduct. Many rectangular transform 1 One's comlement arithmetic can be imlemented by the end - around carry technique. Deartamento de Informática - Facultad de Ciencias Exactas 2

3 can be chosen, leading to the so called BDA-tye algorithm. The traditional transform used is the DFT, which is also in the BDA-tye class. The DFT is oular because the transform can be comuted quickly by FFT. Let M x 1where is a rime number. M is called a Mersenne number 2. The order of x with resect to M is exactly. Let x = 2, then 2 1mod 2 1. This is worth looking at the owers of 2, module M, in binary notation 3. In fact, 2 m mod M, is a word with 1 zeros and a 1 in bit osition m 4. The Mersenne number transform (MNT) of the sequence { a 0, a 1,, a 1 } is defined as, A k = 2 a nk 2 n n = 0 M The inverse Mersenne number transform can be defined given a number N (guaranteed to be integer by Euler's theorem) defined as, 1 M N = = 2 2 It can be roved that the above defined number transform has the convolution roerty, but there is no FFT-like algorithm for comuting the Mersenne transform. But the arithmetic is so simle that in fact can be solved by shift oerations and addition including end-around carry (i.e., one's comlement number reresentation). The ability to relace multilications by comlex transcendental quantities by multilication by owers of 2 (simly imlemented by shift oerations) is the rincial advantage of MNT over DFT (even when a FFT algorithm is used). Besides, the result of the comuted convolution via MNT is always exact without round-off; but this can be a disadvantage because there is not any ossibility for round-off 5 and this can force the use of a an inconveniently large module (i.e., word length). Integer Circular Convolution with MNT The rocedure for comuting any Υ -transform convolution has always the same three stes: a direct transform, a two-oerand multily ste, and finally an inverse transform. 2 If M is rime is called a Mersenne rime, but in this discussion M need not to be rime. 3 Note the fact that the word length is always a rime number. 4 The notation m means m mod. 5 Because exact comutation is not always required. Deartamento de Informática - Facultad de Ciencias Exactas 3

4 ( ( ) ( )) Υ 1 Υ a Υ b n n Therefore, for comuting the ICC it is necessary to multily oint to oint two transforms in that mod M arithmetic ( ). When two Mersenne number transform are multilied together Ck = Ak Bk, the roduct C k has 2 bits. Calling C L the least significant bits, and C H the remaining bits of C k, then, C C + C mod M k L H where the add oeration is made in one's comlement arithmetic. Let M = 127 (or = 7 ). Suose a n = { 1,2, 3, 4, 3,2, 1} 1) Transforming, we get A k = { } B k = { 2, 3, 4,9, 17, 33, 62}.,,,,,, and 2) Multilying A k by B k we get C k = { 32, 40, 57,21,21, 57, 40}. 6 {,,,,,, } and b n = ) Inverse-transforming with N we obtain the exected result c n = { 2, 3, 5, 7, 7, 5, 3}. Object Based To Down Structure for ICC with MNT Even in a functional descrition, a artitioning guideline has to be adoted due to ractical reasons. The artitioning guideline is object based to down (OBTD) [VhdT]. This aroach is articularly useful for structuring the future imlementation. The key in OBTD is the definition of objects (eventual final comonents) that can be reused by other rojects. An atomic object has two imortant characteristics: it is simle to imlement in a reasonable sized architecture and it is sufficient indeendent that it can be exhaustively tested after every modification. In VHDL, objects can be groued into ractical ackages. The so called ICC is the to object. Down from it the following objects and ackages can be identified: ICC object MNT ackage: Direct and Inverse MNT OPS ackage: These are common MNT oerators Rotate object Crush object CA1 ackage: 1 s comlement arithmetic oerators Sum object Product object Croduct object 6 In this examle we are using decimal instead of one's comlement notation for the seek of simlicity. Deartamento de Informática - Facultad de Ciencias Exactas 4

5 The names of the ackages and functionality of the object is almost self-exlanatory: OPS is the ackage of the basic oerations for the imlementation of the direct as well as the inverse MNT. Rotate is a classical rotate oeration over a register, and Crush is the structure for a multile oeration. This ackage can be reused. C1A imlements one's comlement arithmetics. Sum is a two-oerand sum, Product is a two-oerand multily, and Croduct imlement the multilication of a variable number by a constant number (this is useful for the inverse transform). This ackage can be reused. To Level VHDL Model VHDL functional model refers to writing VHDL code for the objects. The goal is to write some code and get a simulation running, but not to get some synthesized gates. In this stes it is ossible to use any other suitable language or system, C, Eiffel, Signal, Matlab 7, Khoros, etc. Nevertheless, we choose to use VHDL because: It is a standard language from which, if desired, it is ossible automatic gate synthesis (in general from a given subset of the language); and it is, at a time, a descrition, behavioral, and simulation language. Hence, SCOUT [Com2], the comanion VHDL simulation environment for Comass Tools [Com1] 8, is used for the functional and structural descrition. The main characteristics of this ste are summarized here: 1. The VHDL model is writing following a down to schedule, based on the objects defined in the OBTD artitioning. 2. Almost every object is quick imlemented as a VHDL function or a VHDL rocedure. No concern about interfaces is taken but the data flow signals. 3. Sizing and timing are out of concern in the functional model. No clock is necessary for a functional descrition, but it is convenient to think about its future insertion in the system. 4. when defining a ackage it is natural to extend then to a more comlete set. This is the case for the ca1 arithmetic ackage: not only Sum, Product, and Croduct are imlemented but also a comlete set of ca1 oerators and related conversion functions for friendly interface. 5. Concurrence among objects, if any, is easily detected and described at this level. 6. Synchronization issues can be tested and the occurrence of deadlock can be revented 9. SCOUT has not automatic detection of those roblems [Tine]. In this case synchronization among the objects is quite simle, but synchronization inter object may be a more comlex subject articularly in C1A's ones. 7. All the objects are functionally tested with their own test bench. 8. ICC and its test bench are the final objects imlemented, and exhaustive behavioral verifications are erformed. 7 Matlab is a trademark of MathWorks Inc. 8 SCOUT and the Comass Tools here mentioned are trademarks of Comass Design Automation Inc. 9 Note that abstract synchronization and deadlocks do not deend on timing. Deartamento de Informática - Facultad de Ciencias Exactas 5

6 Detailed VHDL Design For the detailed VHDL design (logic or even circuit design) rior to synthesis there are many architectural alternatives. We resent in the aendix an examle with the Sum object. The functional definition of the Sum object as art of the C1A ackage can be see in the aendix as well as an alternative for the detailed VHDL design for the Sum object, using a FullAdder as a basic comonent. Actually, this ste is just an exlanation 10 with constrains from a to level of functional descrition to a down level of structural detail. This rocedure can be erformed more or less automatically deending of the availability of software and the degree and confidence of its maing erformance for the target technology. Linear Convolution and LIT system imlementation using the MNT Given an algorithm that imlement ICC it is comutationally ossible to imlement an integer linear convolution (ILC) algorithm ensuring that the circular convolution has the effect of linear convolution. Whether a circular convolution corresonding to the roduct o two N-oint MNTs is the linear convolution of the corresonding finite-length sequences deends on the length of the MNT in relation to the length of the finitelength sequences. We can interret these in terms of time aliasing (see [OSc]). Two basic aroaches are ossible: 1) The overla-add method. 2) The overla-save method. In many alication the inut signal for ractical uroses is of infinite duration. In both methods the solution to that roblem is to slit the signal into section or blocks. In the first aroach the filtered blocks are overlaed and added to construct the outut. In the second aroach the art of the circular convolution that corresond to exact linear convolution are identified and the rest discarded. The resulting outut segments are then concatenated together to form the outut. Both aroaches have been imlemented in VHDL conforming a new to object called Linear Time-Invariant System using Mersenne, LITMa object or, LITMs object. Actually this two object are indeendent of the Mersenne transform, and can be used in a DFT or any alternative context. Concluding Remarks We are convinced that designers will rely increasingly often on reusing revious designs, either created within their working lace or urchased as intellectual roerty from other sources. Another trend is the increasing number of comlex digital signal rocessing alications (e.g. interactive natural language rocessing). Then, the develoment of a DSP VHDL library with an OBTD structure is becoming a recious 10 Within the same language. Deartamento de Informática - Facultad de Ciencias Exactas 6

7 and strategic commodity. We resented here just a secimen of such a library, and defined at a to functional level. Besides the develoment of a concrete library comonent for DSP design, this effort is an academic exercise using the VHDL language as a owerful tool for secification, verification and reusability. We think it is an excellent case of study in which it is necessary a sound background in numerical analysis as well as in DSP. It remains, as a task for the final user, to comare the erformance and cost of this MNT aroach to traditional solutions for imlementing ICC when they are embedded in the framework of a selected IC technology for a articular DSP alication, and when final architectures are fixed. VHDL is a very flexible language, well suited for the descrition of algorithms from the to functional level, that correctly models concurrence, and that can be eventually used to generate scaled nets to synthesize circuits and fully integrate them on silicon. References [Com1] ASIC Synthesizer for VHDL Design. Comass Design Automation, Inc., [DePH] Discrete-Time Processing of Seech Signals. John Deller, John Proakis, and John Hansen. MacMillan, [StSh] ASIC System Design with VHDL: A Paradigm. Steven Leung and Michel Shanblatt. Kluwer, Academic Publishers, [LiSU] VHDL: Hardware Descrition and Design. Roger Lisett, Carl Schaefer, and Cary Ussery. Kluwer Academic Press, [OSc] Discrete-Time Signal Processing. Alan Oenheim and Roland Schafer. Prentice Hall, [PRFN] Advance Digital Signal Processing. John Proakis, Charles Rader, Fuyun Ling, and Chrysostomos Nikias. MacMillan, [RTWG] RASSP VHDL Modeling Terminology and Taxonomy. RASSP Taxonomy Working Grou (RTWG). URL:htt://rass.scra.org, [Com2] The VHDL Scout Handbook, Third Edition. Comass Design Automation, Inc., [Tine] ``Signal as a HDL for Image Processing.'' Fernando Tinetti. Anales de las 3ras Jornadas de la AUGM, [VhdT] ``VHDL Designer.'' VHDL Times, Vol.4 No.2. URL:\verb"htt://vhdl.org", Deartamento de Informática - Facultad de Ciencias Exactas 7

8 Aendix A: VHDL functional definition of the Sum object as art of the C1A ackage: ackage C1A is overloaded functions for bit_vector oerations function "+" (a,b: bit_vector) return bit_vector; end C1A; ackage body C1A is function "+" (a,b: bit_vector) return bit_vector is variable av,bv: bit_vector (1 to a'length); variable carry: bit; variable sum: bit_vector (1 to a'length); begin assert a'length=b'length reort "Oerands to overloaded '+' oerator with different lengths" severity failure; carry:='0'; av:=a; bv:=b; for j in 1 to 2 loo for i in a'length downto 1 loo sum(i):=av(i) xor bv(i) xor carry; carry:=(av(i) and bv(i)) or (av(i) and carry) or (bv(i) and carry); end loo; av:=sum; bv(a'length):=carry; carry:= '0'; j:=j+1; end loo; return sum; end; end C1A; VHDL design for the Sum object, using a FullAdder as a basic comonent: entity Sum is ort (A, B: in Bit_Vector(7-1 downto 0); Sum: out Bit_Vector(7-1 downto 0)); end Sum; architecture Structure of Sum is comonent FullAdder ort (X, Y: in Bit; Cin: in Bit; Cout: out Bit; Sum: out Bit); end comonent; Deartamento de Informática - Facultad de Ciencias Exactas 8

9 signal C, H: Bit_Vector(7-1 downto 0); signal Z: Bit := '0'; begin Stages: for i in 7-1 downto 0 generate end; LowBit: if i = 0 generate FA1: FullAdder ort ma (A(0), B(0), Z, C(0), H(0)); FA2: FullAdder ort ma (H(0), Z, C(7-1), C(0), Sum(0)); end generate; OtherBits: if i /= 0 generate FA1: FullAdder ort ma (A(i), B(i), C(i-1), C(i), H(i)); FA2: FullAdder ort ma (H(i), Z, C(i-1), C(i), Sum(i)); end generate; end generate; Deartamento de Informática - Facultad de Ciencias Exactas 9