Error Correction continued and start on FPGA architecture
|
|
- Corey Reeves
- 5 years ago
- Views:
Transcription
1 EECS 270 Fall 2014, Lecture 21 Page 1 of 7 Error Correction continued and start on FPGA architecture Today we ll finish up error correction and start in on FPGA architecture. But first we ll have an announcement and a bit of review from last time. Announcement: And review: GA4 problem 2 had an error a needed device was left off the list. Yes, it could have been built out of gates (and some of you who already did it may have done so) but that wasn t the intent of the question. 1. Draw the state transition diagram which corresponds to the following logic equations. Assume the initial state is 001 and that our states are one-hot encoded. o NS2=S2*A+S1*!A o NS1=S2*!A+S0 o NS0=S1*A o X=S1+S2 Question: how could you tell if this weren t one-hot encoded? 2. What is the Hamming Distance of the following set: A={11111, 00011, 10100}? What does that say about the potential error correction and detection if we knew the sender only sent data from set A?
2 EECS 270 Fall 2014, Lecture 21 Page 2 of 7 Error correction reviewed Parity gave as a method of detecting a one-bit flip. This is useful because we can, at the least, not use bad data, and we could perhaps even ask for the data to be resent. But what if we want to fix the data without needing to ask for a resend? It turns out we can do that if the set of messages we are using has a Hamming distance of 3 or more. Why is that? Let s review the specific scheme with 4 data bits and 3 parity bits A, B, C, D are data bits while X, Y, Z as parity bits Let P(x 1..x n ) be the function that generates even ones parity over the inputs x 1 to x n. Let X=P(A,B,C) Let Y=P(A,B,D) Let Z=P(A,C,D) From here, we re going to assume only one bit will go bad in a given message? What happens if more than one bit gets flipped? Our message will be received incorrectly. But let s ignore that case for now. Which parity bits will incorrect if the following bit were flipped in transmission? A B C D X Y Z So what s going on? How many bits of error correction would we need if we want to send X data bits with 1 bit of correction? The equation: P=# of parity bits, D= # of data bits.
3 EECS 270 Fall 2014, Lecture 21 Page 3 of 7 Other thoughts 1. How can we use that set to detect 2-bit errors? 2. How do we build the encoder (takes in 4 data bits, generates 7 bit message)? 3. How do we build the decoder (takes in 7 bit message, generates corrected 4-bit data)? -- This is question 1 of GA4. Moving forward on error correction The most obvious question is: how do we make codes for more than 4 data bits? And the answer is fairly simple. If the goal is to make it so that we have 8 data bits, the equation says we need 5 parity bits. But how to generate them? The basic theme is that each data bit must be: Covered by at least 2 parity bits Be covered by a set of parity bits that is unique that is no other data bit can be covered by exactly the same parity bits. An easy (and fairly standard) way to do this is to use the integers in binary. Start counting at 1. Have each number that is a power of 2 (1, 2, 4, 8, etc.) be a parity bit. The other bits are data bits. Notice the powers of 2 have exactly one 1 in them. Of course, all numbers have a unique set of 1 s (not shared with any other number. And finally, when we receive the data, we check which parity bits are different than we d expect. We just OR their numbers together and see which bit was flipped. So if we find 0001 and 0100 were different than expected, we d say that 0101 was the bit that was flipped! Notice that if we just do 1 bit of data, we have standard triple redundancy. What is the set of legal codes? Notice if we want just 4 bits of data, we have the Hamming(7,4) scheme discussed above _ And a few last words The schemes we ve used here have been generating sets. What I mean is that the sender is only sending data that meets certain requirements the parity bits are generated in a fixed way based on the data bits. And so there are so sets of bits that the sender will send, and some it won t send. In the case of even one s parity over 2 data bits, the set of things that might be sent are {000, 110, 101, 011}. That set has a Hamming Distance of 2. The Hamming(7,4) scheme and the Hamming (15,11) scheme both generate sets that have a Hamming Distance of 3. Why can we only do detection of a 1 bit error with a set that has a Hamming Distance of 2? Why can we detect 2 bits of error with a Hamming Distance of 3? Why can we correct 1 bit of error? What Hamming distance would we need if we wanted to correct 2 bits of data?
4 EECS 270 Fall 2014, Lecture 21 Page 4 of 7 FPGA internals: Lookup tables. Let s start looking at the internals of a Field Programmable Gate Array (FPGA). Basic issue: we want programmable hardware but we can t just move transistors around they are fixed in location. So how do we make it so we can create a real hardware device (not immolated in software)? Answer: We use memory. Memory is one thing that we can easily change on the fly. Consider the following truth table of an XNOR gate where F=x XNOR y. We can implement it as a memory. We can even implement 2 logic functions if the memory is two-bits wide (i.e. word size is 2). Create a memory that implements the following (from the text) k p s w
5 EECS 270 Fall 2014, Lecture 21 Page 5 of 7
6 EECS 270 Fall 2014, Lecture 21 Page 6 of 7
7 EECS 270 Fall 2014, Lecture 21 Page 7 of 7
ENEE x Digital Logic Design. Lecture 3
ENEE244-x Digital Logic Design Lecture 3 Announcements Homework due today. Homework 2 will be posted by tonight, due Monday, 9/2. First recitation quiz will be tomorrow on the material from Lectures and
More informationThe Data Link Layer. CS158a Chris Pollett Feb 26, 2007.
The Data Link Layer CS158a Chris Pollett Feb 26, 2007. Outline Finish up Overview of Data Link Layer Error Detecting and Correcting Codes Finish up Overview of Data Link Layer Last day we were explaining
More informationEECS150 - Digital Design Lecture 20 - Finite State Machines Revisited
EECS150 - Digital Design Lecture 20 - Finite State Machines Revisited April 2, 2009 John Wawrzynek Spring 2009 EECS150 - Lec20-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
More informationEECS Components and Design Techniques for Digital Systems. Lec 07 PLAs and FSMs 9/ Big Idea: boolean functions <> gates.
Review: minimum sum-of-products expression from a Karnaugh map EECS 5 - Components and Design Techniques for Digital Systems Lec 7 PLAs and FSMs 9/2- David Culler Electrical Engineering and Computer Sciences
More informationCS/MA 109 Fall Wayne Snyder Computer Science Department Boston University
CS/MA 9 Fall 25 Wayne Snyder Department Boston University Today (Friday the 3 th!): Error-detecting and error-correcting codes. Next week: Cryptography From last time to this time Compression takes advantage
More informationFrom last time to this time
/7/6 CS/MA 9 Fall 26 Wayne Snyder Department Boston University Today and Wednesday: Error-detecting and error-correcting codes Wednesday & Friday: Cryptography From last time to this time Compression takes
More informationError Detection. Hamming Codes 1
Error Detection Hamming Codes 1 Error detecting codes enable the detection of errors in data, but do not determine the precise location of the error. - store a few extra state bits per data word to indicate
More information12/2/2016. Error Detection May Not Be Enough. ECE 120: Introduction to Computing. Can We Use Redundancy to Correct Errors?
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Error Correction, Hamming Codes, and SEC-DED Codes Error Detection May Not Be
More informationErrors. Chapter Extension of System Model
Chapter 4 Errors In Chapter 2 we saw examples of how symbols could be represented by arrays of bits. In Chapter 3 we looked at some techniques of compressing the bit representations of such symbols, or
More informationModel EXAM Question Bank
VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI Department of Information Technology Model Exam -1 1. List the main difference between PLA and PAL. PLA: Both AND and OR arrays are programmable
More informationCSE 123: Computer Networks Alex C. Snoeren. HW 1 due Thursday!
CSE 123: Computer Networks Alex C. Snoeren HW 1 due Thursday! Error handling through redundancy Adding extra bits to the frame Hamming Distance When we can detect When we can correct Checksum Cyclic Remainder
More informationError-Correcting Codes
Error-Correcting Codes Michael Mo 10770518 6 February 2016 Abstract An introduction to error-correcting codes will be given by discussing a class of error-correcting codes, called linear block codes. The
More informationSigned umbers. Sign/Magnitude otation
Signed umbers So far we have discussed unsigned number representations. In particular, we have looked at the binary number system and shorthand methods in representing binary codes. With m binary digits,
More informationCh. 7 Error Detection and Correction
Ch. 7 Error Detection and Correction Error Detection and Correction Data can be corrupted during transmission. Some applications require that errors be detected and corrected. 2 1. Introduction Let us
More informationCS 43: Computer Networks. 16: Reliable Data Transfer October 8, 2018
CS 43: Computer Networks 16: Reliable Data Transfer October 8, 2018 Reading Quiz Lecture 16 - Slide 2 Last class We are at the transport-layer protocol! provide services to the application layer interact
More informationError correction in Flash memory 1. Error correction in Flash memory. Melissa Worley. California State University Stanislaus.
Error correction in Flash memory 1 Error correction in Flash memory Melissa Worley California State University Stanislaus Senior Seminar 24 October 2010 Error correction in Flash memory 2 Abstract In this
More informationLecture 6: Reliable Transmission. CSE 123: Computer Networks Alex Snoeren (guest lecture) Alex Sn
Lecture 6: Reliable Transmission CSE 123: Computer Networks Alex Snoeren (guest lecture) Alex Sn Lecture 6 Overview Finishing Error Detection Cyclic Remainder Check (CRC) Handling errors Automatic Repeat
More informationTopic Notes: Building Memory
Computer Science 220 ssembly Language & Comp. rchitecture Siena College Fall 2011 Topic Notes: Building Memory We ll next see how we can use flip-flop devices to construct memory. Buffers We ve seen and
More informationELG3175 Introduction to Communication Systems. Introduction to Error Control Coding
ELG375 Introduction to Communication Systems Introduction to Error Control Coding Types of Error Control Codes Block Codes Linear Hamming, LDPC Non-Linear Cyclic BCH, RS Convolutional Codes Turbo Codes
More informationEC500. Design of Secure and Reliable Hardware. Lecture 1 & 2
EC500 Design of Secure and Reliable Hardware Lecture 1 & 2 Mark Karpovsky January 17 th, 2013 1 Security Errors injected by the attacker (active attacks) Reliability Errors injected by random sources e.g.
More informationError Detection And Correction
Announcements Please read Error Detection and Correction sent to you by your grader. Lab Assignment #2 deals with Hamming Code. Lab Assignment #2 is available now and will be due by 11:59 PM on March 22.
More information1 Shapes of Power Functions
MA 1165 - Lecture 06 1 Wednesday, 1/28/09 1 Shapes of Power Functions I would like you to be familiar with the shape of the power functions, that is, the functions of the form f(x) = x n, (1) for n = 1,
More informationChapter 10 Error Detection and Correction 10.1
Chapter 10 Error Detection and Correction 10.1 10-1 INTRODUCTION some issues related, directly or indirectly, to error detection and correction. Topics discussed in this section: Types of Errors Redundancy
More informationCommunication Fundamentals in Computer Networks
Lecture 7 Communication Fundamentals in Computer Networks M. Adnan Quaium Assistant Professor Department of Electrical and Electronic Engineering Ahsanullah University of Science and Technology Room 4A07
More information(Refer Slide Time: 2:20)
Data Communications Prof. A. Pal Department of Computer Science & Engineering Indian Institute of Technology, Kharagpur Lecture-15 Error Detection and Correction Hello viewers welcome to today s lecture
More informationWritten exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when
More informationCMSC 2833 Lecture 18. Parity Add a bit to make the number of ones (1s) transmitted odd.
Parity Even parity: Odd parity: Add a bit to make the number of ones (1s) transmitted even. Add a bit to make the number of ones (1s) transmitted odd. Example and ASCII A is coded 100 0001 Parity ASCII
More informationDue dates are as mentioned above. Checkoff interviews for PS2 and PS3 will be held together and will happen between October 4 and 8.
Problem Set 3 Your answers will be graded by actual human beings (at least that ' s what we believe!), so don' t limit your answers to machine-gradable responses. Some of the questions specifically ask
More informationCS101 Lecture 04: Binary Arithmetic
CS101 Lecture 04: Binary Arithmetic Binary Number Addition Two s complement encoding Briefly: real number representation Aaron Stevens (azs@bu.edu) 25 January 2013 What You ll Learn Today Counting in binary
More information4.7 Approximate Integration
4.7 Approximate Integration Some anti-derivatives are difficult to impossible to find. For example, 1 0 e x2 dx or 1 1 1 + x3 dx We came across this situation back in calculus I when we introduced the
More informationproblem maximum score 1 10pts 2 8pts 3 10pts 4 12pts 5 7pts 6 7pts 7 7pts 8 17pts 9 22pts total 100pts
University of California at Berkeley College of Engineering epartment of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 2/21/03 Exam I Solutions Name: I number: This is a
More informationDiscrete structures - CS Fall 2017 Questions for chapter 2.1 and 2.2
Discrete structures - CS1802 - Fall 2017 Questions for chapter 2.1 and 2.2 1. (a) For the following switch diagrams, write the corresponding truth table and decide whether they correspond to one of the
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Building Memory
Computer Science 324 Computer rchitecture Mount Holyoke College Fall 2007 Topic Notes: Building Memory We ll next look at how we can use the devices we ve been looking at to construct memory. Tristate
More informationCHAPTER 1 Encoding Information
MIT 6.02 DRAFT Lecture Notes Spring 2011 Comments, questions or bug reports? Please contact 6.02-staff@mit.edu CHAPTER 1 Encoding Information In this lecture and the next, we ll be looking into compression
More informationCHAPTER 7. Copyright Cengage Learning. All rights reserved.
CHAPTER 7 FUNCTIONS Copyright Cengage Learning. All rights reserved. SECTION 7.1 Functions Defined on General Sets Copyright Cengage Learning. All rights reserved. Functions Defined on General Sets We
More informationMemory and Programmable Logic
Memory and Programmable Logic Mano & Ciletti Chapter 7 By Suleyman TOSUN Ankara University Outline RAM Memory decoding Error detection and correction ROM Programmable Logic Array (PLA) Programmable Array
More informationAnnouncement. (CSC-3501) Lecture 3 (22 Jan 2008) Today, 1 st homework will be uploaded at our class website. Seung-Jong Park (Jay)
Computer Architecture (CSC-3501) Lecture 3 (22 Jan 2008) Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark 1 Announcement Today, 1 st homework will be uploaded at our class website Due date is the beginning
More informationBasics of Information Worksheet
Basics of Information Worksheet Concept Inventory: Notes: Measuring information content; entropy Two s complement; modular arithmetic Variable-length encodings; Huffman s algorithm Hamming distance, error
More informationOverview. CSE372 Digital Systems Organization and Design Lab. Hardware CAD. Two Types of Chips
Overview CSE372 Digital Systems Organization and Design Lab Prof. Milo Martin Unit 5: Hardware Synthesis CAD (Computer Aided Design) Use computers to design computers Virtuous cycle Architectural-level,
More informationAdvanced Computer Networks. Rab Nawaz Jadoon DCS. Assistant Professor COMSATS University, Lahore Pakistan. Department of Computer Science
Advanced Computer Networks Department of Computer Science DCS COMSATS Institute of Information Technology Rab Nawaz Jadoon Assistant Professor COMSATS University, Lahore Pakistan Advanced Computer Networks
More informationMusic. Numbers correspond to course weeks EULA ESE150 Spring click OK Based on slides DeHon 1. !
MIC Lecture #7 Digital Logic Music 1 Numbers correspond to course weeks sample EULA D/A 10101001101 click OK Based on slides 2009--2018 speaker MP Player / iphone / Droid DeHon 1 2 A/D domain conversion
More informationLecture 6: Signed Numbers & Arithmetic Circuits. BCD (Binary Coded Decimal) Points Addressed in this Lecture
Points ddressed in this Lecture Lecture 6: Signed Numbers rithmetic Circuits Professor Peter Cheung Department of EEE, Imperial College London (Floyd 2.5-2.7, 6.1-6.7) (Tocci 6.1-6.11, 9.1-9.2, 9.4) Representing
More informationOutline. Parity-based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication. Outline
Parity-based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication Khanh N. Dang and Xuan-Tu Tran Email: khanh.n.dang@vnu.edu.vn VNU Key Laboratory for Smart Integrated Systems
More informationCSE 123: Computer Networks
Student Name: PID: UCSD email: CSE 123: Computer Networks Homework 1 Solution (Due 10/12 in class) Total Points: 30 Instructions: Turn in a physical copy at the beginning of the class on 10/10. Problems:
More informationSome announcements. Announcements for game due (via ) on Wednesday, March 15 Homework 6 due on March 15 Exam 3 on March 17
Hamming Codes Some announcements Announcements for game due (via email) on Wednesday, March 15 Homework 6 due on March 15 Exam 3 on March 17 Today s Goals Learn about error correcting codes and how they
More informationumber Systems bit nibble byte word binary decimal
umber Systems Inside today s computers, data is represented as 1 s and 0 s. These 1 s and 0 s might be stored magnetically on a disk, or as a state in a transistor. To perform useful operations on these
More information1. Draw general diagram of computer showing different logical components (3)
Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the
More information2015 Paper E2.1: Digital Electronics II
s 2015 Paper E2.1: Digital Electronics II Answer ALL questions. There are THREE questions on the paper. Question ONE counts for 40% of the marks, other questions 30% Time allowed: 2 hours (Not to be removed
More informationDescribe the two most important ways in which subspaces of F D arise. (These ways were given as the motivation for looking at subspaces.
Quiz Describe the two most important ways in which subspaces of F D arise. (These ways were given as the motivation for looking at subspaces.) What are the two subspaces associated with a matrix? Describe
More informationThe Gray Code. Script
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 9 Lecture Title:
More informationLECTURE 4. Logic Design
LECTURE 4 Logic Design LOGIC DESIGN The language of the machine is binary that is, sequences of 1 s and 0 s. But why? At the hardware level, computers are streams of signals. These signals only have two
More informationEECS 140 Laboratory Exercise 5 Prime Number Recognition
1. Objectives EECS 140 Laboratory Exercise 5 Prime Number Recognition A. Become familiar with a design process B. Practice designing, building, and testing a simple combinational circuit 2. Discussion
More informationECE 341 Midterm Exam
ECE 341 Midterm Exam Time allowed: 90 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (10 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a)
More informationR07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April
SET - 1 II B. Tech II Semester, Supplementary Examinations, April - 2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions
More information1 Counting triangles and cliques
ITCSC-INC Winter School 2015 26 January 2014 notes by Andrej Bogdanov Today we will talk about randomness and some of the surprising roles it plays in the theory of computing and in coding theory. Let
More information1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]
HW 3 Answer Key 1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tri-state buffers and inverters and thus you
More informationLink Layer: Error detection and correction
Link Layer: Error detection and correction Topic Some bits will be received in error due to noise. What can we do? Detect errors with codes Correct errors with codes Retransmit lost frames Later Reliability
More informationLecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1
Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The
More informationHorn Formulae. CS124 Course Notes 8 Spring 2018
CS124 Course Notes 8 Spring 2018 In today s lecture we will be looking a bit more closely at the Greedy approach to designing algorithms. As we will see, sometimes it works, and sometimes even when it
More informationCHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES This chapter in the book includes: Objectives Study Guide 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders
More informationFAULT TOLERANT SYSTEMS
FAULT TOLERANT SYSTEMS http://www.ecs.umass.edu/ece/koren/faulttolerantsystems Part 6 Coding I Chapter 3 Information Redundancy Part.6.1 Information Redundancy - Coding A data word with d bits is encoded
More informationCSE 380 Computer Operating Systems
CSE 380 Computer Operating Systems Instructor: Insup Lee University of Pennsylvania Fall 2003 Lecture Note on Disk I/O 1 I/O Devices Storage devices Floppy, Magnetic disk, Magnetic tape, CD-ROM, DVD User
More informationEECS 150 Homework 7 Solutions Fall (a) 4.3 The functions for the 7 segment display decoder given in Section 4.3 are:
Problem 1: CLD2 Problems. (a) 4.3 The functions for the 7 segment display decoder given in Section 4.3 are: C 0 = A + BD + C + BD C 1 = A + CD + CD + B C 2 = A + B + C + D C 3 = BD + CD + BCD + BC C 4
More informationECE 550D Fundamentals of Computer Systems and Engineering. Fall 2017
ECE 550D Fundamentals of Computer Systems and Engineering Fall 2017 Combinational Logic Prof. John Board Duke University Slides are derived from work by Profs. Tyler Bletsch and Andrew Hilton (Duke) Last
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c/su06 CS61C : Machine Structures Lecture #14: Combinational Logic, Gates, and State 2006-07-20 CS 61C L14 Combinational Logic (1) Andy Carle What are Machine Structures? Software
More informationRecitation Session 6
Recitation Session 6 CSE341 Computer Organization University at Buffalo radhakri@buffalo.edu March 11, 2016 CSE341 Computer Organization Recitation Session 6 1/26 Recitation Session Outline 1 Overview
More information9.1 Linear Inequalities in Two Variables Date: 2. Decide whether to use a solid line or dotted line:
9.1 Linear Inequalities in Two Variables Date: Key Ideas: Example Solve the inequality by graphing 3y 2x 6. steps 1. Rearrange the inequality so it s in mx ± b form. Don t forget to flip the inequality
More informationChapter 10 Error Detection and Correction. Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Chapter 10 Error Detection and Correction 0. Copyright The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Note The Hamming distance between two words is the number of differences
More informationDesigning Information Devices and Systems II Fall 2017 Miki Lustig and Michel Maharbiz Discussion 1B
EEC 16B esigning Information evices and ystems II Fall 2017 Miki Lustig and Michel Maharbiz iscussion 1B igit Bases (N) p is used to indicate that the number N is expressed in base p. For example, (N)
More informationProgrammable Logic Devices (PLDs)
Programmable Logic Devices (PLDs) 212: Digital Design I, week 13 PLDs basically store binary information in a volatile/nonvolatile device. Data is specified by designer and physically inserted (Programmed)
More informationBoolean Logic CS.352.F12
Boolean Logic CS.352.F12 Boolean Algebra Boolean Algebra Mathematical system used to manipulate logic equations. Boolean: deals with binary values (True/False, yes/no, on/off, 1/0) Algebra: set of operations
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers L14 Memory 1 General Table Lookup Synthesis
More informationEECS 270 Midterm Exam
EECS 270 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1 /11 2 /4
More informationSlide Set 1. for ENEL 339 Fall 2014 Lecture Section 02. Steve Norman, PhD, PEng
Slide Set 1 for ENEL 339 Fall 2014 Lecture Section 02 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2014 ENEL 353 F14 Section
More informationSTEVEN R. BAGLEY THE ASSEMBLER
STEVEN R. BAGLEY THE ASSEMBLER INTRODUCTION Looking at how to build a computer from scratch Started with the NAND gate and worked up Until we can build a CPU Reached the divide between hardware and software
More informationDATA STORAGE. Chapter One. Chapter Summary. Comments
Chapter One DATA STORAGE Chapter Summary This chapter presents the rudiments of data storage within digital computers. It introduces the basics of digital circuitry and how a simple flip-flop can be used
More informationWELCOME TO. ENGR 303 Introduction to Logic Design. Hello my name is Dr. Chuck Brown
Chapter 1 WELCOME TO Introduction to Logic Design Hello my name is Dr. Chuck Brown Please sign in and then find a seat. The person next to you will be your lab partner for the course so choose wisely and
More information4. Error correction and link control. Contents
//2 4. Error correction and link control Contents a. Types of errors b. Error detection and correction c. Flow control d. Error control //2 a. Types of errors Data can be corrupted during transmission.
More informationPART III. Data Link Layer MGH T MGH C I 204
PART III Data Link Layer Position of the data-link layer Data link layer duties LLC and MAC sublayers IEEE standards for LANs Chapters Chapter 10 Error Detection and Correction Chapter 11 Data Link Control
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationCSE 143 Lecture 22. Huffman Tree
CSE 4 Lecture Huffman slides created by Ethan Apter http://www.cs.washington.edu/4/ Huffman Tree For your next assignment, you ll create a Huffman tree Huffman trees are used for file compression file
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Spring 2002 Original Lab By: J.Wawrzynek and N. Weaver Later revisions by
More informationDATA LINK LAYER UNIT 7.
DATA LINK LAYER UNIT 7 1 Data Link Layer Design Issues: 1. Service provided to network layer. 2. Determining how the bits of the physical layer are grouped into frames (FRAMING). 3. Dealing with transmission
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Eamination ECE 4F - Digital Systems Eaminers: S. Brown, J.
More informationUNCA CSCI 255 Exam 1 Spring February, This is a closed book and closed notes exam. It is to be turned in by 1:45 PM.
UNCA CSCI 255 Exam 1 Spring 2017 27 February, 2017 This is a closed book and closed notes exam. It is to be turned in by 1:45 PM. Communication with anyone other than the instructor is not allowed during
More informationChapter 3. The Data Link Layer. Wesam A. Hatamleh
Chapter 3 The Data Link Layer The Data Link Layer Data Link Layer Design Issues Error Detection and Correction Elementary Data Link Protocols Sliding Window Protocols Example Data Link Protocols The Data
More informationLecture 4: CRC & Reliable Transmission. Lecture 4 Overview. Checksum review. CRC toward a better EDC. Reliable Transmission
1 Lecture 4: CRC & Reliable Transmission CSE 123: Computer Networks Chris Kanich Quiz 1: Tuesday July 5th Lecture 4: CRC & Reliable Transmission Lecture 4 Overview CRC toward a better EDC Reliable Transmission
More informationCS43: Computer Networks Reliable Data Transfer. Kevin Webb Swarthmore College October 5, 2017
CS43: Computer Networks Reliable Data Transfer Kevin Webb Swarthmore College October 5, 2017 Agenda Today: General principles of reliability Next time: details of one concrete, very popular protocol: TCP
More informationPiecewise Defined Functions
Piecewise Defined Functions Most of the functions that we ve looked at this semester can be expressed as a single equation. For example, f(x) =3x 2 5x +2,org(x) = x 1, or h(x) =e 3x 1. Sometimes an equation
More informationUniversity of Alexandria Faculty of Engineering Division of Communications & Electronics
University of Alexandria Faculty of Engineering Division of Communications & Electronics Subject Name: Microprocessors Lecturer: Dr. Mohammed Morsy Academic Year: 2012 2013 Assistants: Eng. Ahmed Bedewy
More informationFault Tolerance & Reliability CDA Chapter 2 Additional Interesting Codes
Fault Tolerance & Reliability CDA 5140 Chapter 2 Additional Interesting Codes m-out-of-n codes - each binary code word has m ones in a length n non-systematic codeword - used for unidirectional errors
More informationOutline. Announcements. Homework 2. Boolean expressions 10/12/2007. Announcements Homework 2 questions. Boolean expression
Outline ECS 10 10/8 Announcements Homework 2 questions Boolean expressions If/else statements State variables and avoiding sys.exit( ) Example: Coin flipping (if time permits) Announcements Professor Amenta
More information(Refer Slide Time 3:31)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 5 Logic Simplification In the last lecture we talked about logic functions
More informationCS 640 Introduction to Computer Networks. Role of data link layer. Today s lecture. Lecture16
Introduction to Computer Networks Lecture16 Role of data link layer Service offered by layer 1: a stream of bits Service to layer 3: sending & receiving frames To achieve this layer 2 does Framing Error
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationLecture 11 Overview. Last Lecture. This Lecture. Next Lecture. Medium Access Control. Flow and error control Source: Sections , 23.
Last Lecture Lecture 11 Overview Medium Access Control This Lecture Flow and error control Source: Sections 11.1-11.2, 23.2 Next Lecture Local Area Networks 1 Source: Sections 13 Data link layer Logical
More informationOutline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?
Outline EECS 5 - Components and Design Techniques for Digital Systems Lec Putting it all together -5-4 David Culler Electrical Engineering and Computer Sciences University of California Berkeley Top-to-bottom
More informationCombinational Circuits
Combinational Circuits Q. What is a combinational circuit? A. Digital: signals are or. A. No feedback: no loops. analog circuits: signals vary continuously sequential circuits: loops allowed (stay tuned)
More information1KOd17RMoURxjn2 CSE 20 DISCRETE MATH Fall
CSE 20 https://goo.gl/forms/1o 1KOd17RMoURxjn2 DISCRETE MATH Fall 2017 http://cseweb.ucsd.edu/classes/fa17/cse20-ab/ Today's learning goals Explain the steps in a proof by mathematical and/or structural
More information