VHDL vs. BSV: A case study on a Java-optimized processor

Transcription

1 VHDL vs. BSV: A case study on a Java-optimized processor April 18, 2007

2 Outline Introduction Goal Design parameters

3 Goal Design parameters What are we trying to do? Compare BlueSpec SystemVerilog (BSV) vs. VHDL using the design of a Java-optimized processor. Which approach is better in terms of: design time code lines area/performance modularity flexibility portability simulation and debugging support

4 Goal Design parameters Design features The following features are required for both the VHDL and BSV versions: micro-programmed, stack machine core predictable rather than high-performance (RT systems) identical interface to the rest of the system given instruction set (bytecodes) fixed micro-instruction set (for ease of programming) identical executable image (loaded classes) same back-end (synthesis) tools same implementation platform (FPGA)

5 in brief The initial design (a version of JOP) RT-level VHDL, synthesizable Four stages pipeline: 1. bytecode fetch 2. micro-instruction fetch 3. decode and fetch operands 4. execute and write-back 1KB method cache (one method at a time)

6 overview Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6 forward bcfifo BC2 microa mififo jump table dififo fofifo bypass wbfifo Fetch Bytecode Fetch micro-i Decode Fetch operands Execute Writeback micro- ROM SP OPD PC BC- Cache load cache JPC MwA VP Registers MD MrA Stack const bus interface (OPB)

7 Micro-code aspects Introduction microcode.asm types.bsv bluejasm generator.bsv bsv compiler -sim genrom micro- ROM BC2 microa jump table stack The encoding of the micro-instructions does not affect the assembler! The actual encoding is interesting for optimization purposes only.

8 Design time (0 1) VHDL An almost complete re-implementation of an existing design, targeting improved performance and altered micro-instruction set. Tools such as binary image generator and micro-assembler were rewritten. (6 months) BSV Based on the VHDL experience and tools, but with limited prior knowledge of the language. Deeper, more generic pipeline. (3 months)

9 Code lines (0 2) Introduction Only the used modules were considered, no testing code included. VHDL = ca lines. Shorter pipeline, state centric description, explicit handling of clock, explicit handling of signals, poor state control (inferred latches). BSV = ca in BSV, and ca after compiling it into RTL Verilog. Longer pipeline, rule based description, transparent clocking, user defined types, parametrized modules, implicit type packing/unpacking, strict state control (explicit registers). Rule centric descriptions let the compiler explore and choose a schedule, as opposed to state centric, fixed schedule solutions.

10 Synthesis Results: Toolchain used: Xilinx ISE 9.1 Although the BSV output gives correct behavioral simulation results and synthesizes, the synthesized model yields incorrect results! Cannot make a fair quantitative comparison! (2 2) VHDL poor register control (Inferred latches), simpler processor, shorter pipeline smaller area, slower clock BSV explicit register instantiation, longer pipeline, rather general primitive library (RegFile is a five ports distributed RAM) relies heavily on the performance of the synthesis tool harder to control the timing, larger area, faster clock

11 Test and Debug (2 3) VHDL requires simulation and examining waveforms, a painful and time consuming process BSV more software-like. Generate a standalone simulator (an executable), use debug messages. Generate waveforms. Writing test suites is supported through StmtFSM (statements FSM) module. Finally, the Verilog output can be simulated. Linking final signals back to program structures is however harder.

12 (2 4) VHDL support for modular designs, parameters, generate BSV offers more powerful parametrisation for types, modules, functions. Test for simple types, use them with complex ones. Example: sfifo: Searchable FIFO, of a generic type, with an instance specific equality function.

13 Searchable FIFO Introduction 1 import ConfigReg ::*; 2 import RWire ::*; 4 interface SFIFO #( type alpha_t, type search_t ); 5 // standard FIFO stuff 6 method Action enq ( alpha_t x); 7 method Action deq (); 8 method alpha_t first (); 9 method Action clear (); 10 // additional methods 11 method Bool find ( search_t x); 12 method Bool find2 ( search_t x); 13 endinterface 15 // a single element SFIFO implementation 16 // first, deq < find, find2, enq < clear 17 module mksfifo1 #( function Bool searchf ( search_t s, alpha_t x)) 18 ( SFIFO #( alpha_t, search_t )) provisos (Bits #( alpha_t,asz ), Eq #( alpha_t )) 20 Reg #( alpha_t ) f0 <- mkconfigregu ; 21 Reg #( Bool ) vf0 <- mkconfigreg ( False ); 22 PulseWire edge1 <- mkpulsewire (); 24 method Action enq ( alpha_t x) if (! vf0 ); 25 vf0 <= True ; 26 f0 <= x; 27 endmethod

14 29 method Action deq () if(vf0 ); 30 edge1. send (); 31 vf0 <= False ; 32 endmethod 34 method alpha_t first () if(vf0 ); 35 return f0; 36 endmethod 38 method Action clear (); 39 vf0 <= False ; 40 endmethod 42 method Bool find ( search_t sv ); 43 Bool nvf0 = edge1? False : vf0 ; 44 return ( nvf0 && searchf (sv, f0 )); 45 endmethod 47 method Bool find2 ( search_t sv ); 48 Bool nvf0 = edge1? False : vf0 ; 49 return ( nvf0 && searchf (sv, f0 )); 50 endmethod 51 endmodule 53 // Observe that enq and deq can never occur at the same time!

15 (2 5) An example: Add a new micro-instruction! VHDL specific pipeline, complicated, low level changes: change the decode stage and its interface change the execute stage (add muxes, registers, FUs...) changed the micro-assembler to generate the new codes BSV more generic pipeline, simpler, higher level changes: add a new micro-instruction type change the decode stage possibly the execute stage if a new FU is needed Clear possibility for micro-instruction folding.

16 Sample micro-instruction type and coding: 1 typedef enum {Add, Sub, Or, Shl,...} ALOp 2 deriving (Bits, Eq ); 4 typedef union tagged { 5 struct { } Nop ; 6 struct { } Pop ; 7 struct { ALOp op; } Alop ; 8 struct { Bit #(5) opd ; } Bz; } Jmicroi deriving ( Bits, Eq ); However if Bits is left out from deriving, the compiler requires the presence of custom pack/unpack functions: 1 instance Bits #( Jmicroi, 8); 3 function Bit #(8) pack ( Jmicroi inst ); 4 case ( inst ) matches 5 tagged Nop {}: return b ; 6 tagged Pop {}: return b ; 7 tagged ALop {op:.n }: return { b0001, pack (n )}; 8 tagged Bz { opd :.n}: return { b010, pack (n )}; default : return b ; 11 endcase 12 endfunction : pack

17 14 function Jmicroi unpack ( Bit #(8) x); 15 case (x [7:5]) 16 b000 : if (x [4] ==0) 17 case (x [3:0]) b0000 : return tagged Nop {}; 20 endcase 21 else 22 return tagged ALop {op: unpack (x [3:0])}; 23 b010 : return tagged Bz { opd : unpack (x [4:0])}; 24 endcase 25 endfunction : unpack 27 endinstance

18 (3 5) VHDL A few mixed language simulators combining SystemC, C, VHDL, Verilog,... Many VHDL/Verilog design environments, including free simulators. BSV Exporting BSV modules to Verilog is awkward. The other way around is easy. Combining C, Verilog, BSV is easy. However, only one company providing BSV, no free versions.

19 BSV is for VHDL/Verilog what C is for ASM No big surprise: higher abstraction descriptions are faster to write and more flexible! BSV over VHDL: + halved design time + more flexible/maintainable - harder to identify and influence timing problems - in infancy/limited tool support? acceptable area/performance penalties