Siloed Reference Analysis

Transcription

1 Siloed Reference Analysis Xing Zhou 1. Objectives: Traditional compiler optimizations must be conservative for multithreaded programs in order to ensure correctness, since the global variables or memory locations whose address can escape from local scope might be accessed in other threads concurrently. The goal of this project is to enable the optimization opportunity on escaping memory locations while still guarantee correctness for multithreaded programs. 2. Motivational Example: If we can prove that from 10 to 30, there is no concurrent thread that can possibly write to G, we can remove attached to lock(), and LPRE can be done, as shown in Figure 1. 30: tmp2=g ; Siloed Reference Analysis 30: tmp2=g; LPRE 30: tmp2=tmp1; Figure 1. Eliminate χs to enable optimizations To prove absence of concurrent modification, the compiler must understand the concurrency structure of the program. As the example shown below, main() creates a new thread with the entry routine foo(). As in foo(), global variable G cannot have concurrent modification because although there is a def to G in main(), it happens before the new thread being spawned. In contrast, global variable X may have concurrent modification. Thus for this particular example (suppose we have whole program information), χ of G can be removed while χ of X cannot. int main() { 10: G=; 20: pthread_create(foo); 30: X=; } void foo() { X = χ(x) 30: tmp2=g ; }

2 Figure 2. Modifications in different regions 3. Definitions: a. Opaque function calls: the callee function body is not compiled in IPA. b. Understandable opaque function calls: opaque functions with understandable sideeffects, such as arithmetical functions, and synchronizations c. Synchronizations: a special subset of understandable opaque functions. Currently only pthread synchronizations primitives are recognized. d. Memory locations: variables (LDID/STID ST) and the objects pointed by pointers (ILOAD/ISTORE). To unify the representation of memory locations, alias tags are used as virtual memory locations. e. Siloed reference: if in PU f, memory location X cannot be modified concurrently by other threads, the read to X is said to be siloed read in PU f. On the other hand, memory location Y cannot be used (read) concurrently by other threads, the write to X is said to be siloed write in PU f. In this document, siloed reference only refers to siloed read. 4. Main Data Structures: a. PCG_NODE: the PU node in PCG, corresponding to IPA_NODE in IPA_CALL_GRAPH. Figure 3. Structure of class PCG_NODE

3 Key fields in PCG_NODE: _flags: derived from PCG_NODE_BASE. It is a bit-vector with 3 possible flags: o PCG_SPAWNER: indicates that this PU may call pthread_create either directly or indirectly; o PCG_SPAWNEE: indicates that this PU may be executed in a child thread (the entry of the child thread or called in child thread); o PCG_FOLLOW: indicates that this PU may be called after pthread_create is called (either directly or indirectly) in some execution path. Note that the above flags can be applied to a PU the same time. _store_set: the set of alias tags for statements with memory write (STID/ISTORE) _follow_store_set: the set of alias tags for statements with memory write and can be reached from a callsite whose callee routine is either pthread_create or a PU with PCG_SPAWNER tag set. _siloed_ref_set: the alias tag set of the memory locations that are siloed in this PU. The memory locations must occurs in this PU Propagate_up():derived from PCG_NODE_BASE. Propagate flag(s) (PCG_SPAWNER) upwards (from callee to caller) in IPA_CALL_GRAPH. Propagate_down():derived from PCG_NODE_BASE. Propagate flag(s) (PCG_SPAWNEE and PCG_FOLLOW) downwards (from caller to callee) in IPA_CALL_GRAPH. b. IPA_PCG: Procedural Concurrency Graph Figure 4. Structure of class IPA_PCG i. _pcg_node_vec: vector of PCG_NODEs contained. ii. _ipa_node_to_pcg_node_map: map from IPA_NODE to its corresponding PCG_NODE. iii. st_to_node_vec_map: map from ST to a list of PCG_NODEs. Used to handle indirect calls. iv. The construction of PCG is done within the constructor of IPA_PCG. 1. Flow_insensitive_traverse(): do flow insensitive traverse for the PU to build _store_set.

4 2. Flow_sensitive_traverse(): do flow sensitive traverse for the PU to build _follow_store_set. v. Collect_siloed_references(): collect the siloed reference set for each PU. vi. Get_siloed_references():return the siloed reference set for each PU. Used to write BE summary c. IPA_PCG *IPA_Concurrency_Graph: a global pointer to the PCG instance. 5. Interface: The main interfaces of siloed reference analysis are in class IPA_PCG. The analysis should be done in IPA_LINK and the analysis results are written into BE summary. There is a global pointer to the PCG instance: IPA_Concurrency_Graph. The interface functions are listed below: a. Constructor: PCG construction. It can be used to create a PCG instance to initialize IPA_Concurrency_Graph in Perform_Interprocedural_Analysis() during IPA_LINK. b. Collect_siloed_references(): do siloed reference analysis after IPA_Concurrency_Graph is initialized. c. Get_siloed_references(): get the set of siloed reference alias tags for each PU. 6. Algorithm: a. Step 1: Compute _flags of PCG_NODE for each PU (build PCG) i. PCG_SPAWNER flag: If PU may call pthread_create directly, set PCG_SPAWNER flag for its PCG_NODE ii. Propagate PCG_SPAWNER flag: If the PCG_NODE for PU has PCG_SPAWNER flag set, set PCG_SPAWNER flag for all of callers PCG_NODEs (call graph needed). Do this recursively until PCG is not changed. iii. PCG_SPAWNEE flag: If PU occurs as an argument of pthread_create, set PCG_SPAWNEE flag for its PCG_NODE iv. Propagate PCG_SPAWNEE flag: If the PCG_NODE for PU has PCG_SPAWNEE flag set, set PCG_SPAWNEE flag for all of callees PCG_NODEs (call graph needed). Do this recursively until PCG is not changed. v. PCG_FOLLOW flag: For each PU with PCG_SPAWNER flag set but without PCG_SPAWNEE flag set, start from each callsite with the callee is either pthread_create or a PU with PCG_SPAWNER flag set, do a DFS search to find every reachable callsite. Set PCG_FOLLOW flag for callee PUs of all the reachable callsites. vi. Propagate PCG_FOLLOW flag: If the PCG_NODE for PU has PCG_FOLLOW flag set, set PCG_FOLLOW flag for all of callees PCG_NODEs (call graph needed). Do this recursively until PCG is not changed.

5 b. Step 2: Compute interference set: compute the set of memory locations that can be modified in the concurrent part of the program. i. For each PU with PCG_SPAWNEE or PCG_FOLLOW flag set, traverse function body to collect the memory locations (alias tag) that can be modified, e.g., the operand of STID and ISOTRE. ii. For each PU with PCG_SPAWNER flag set, start from each callsite with the callee is either pthread_create or a PU with PCG_SPAWNER flag set, do a DFS search to find all the reachable statements. Collect the memory locations (alias tag) that can be modified in any reachable statements. iii. The whole program interference set is the union of the interference sets of all PUs. iv. Note: only collect the alias tag of the following cases: 1. Real occurrences of memory write, e.g., STID and ISOTRE. 2. χ list of opaque functions, except synchronizations. Please note that the alias tags of entry χs, χ lists of PUs with source and χ lists of synchronizations are not inserted into the interference set. c. Step 3: Compute siloed references in each PU and write into BE summary. i. If a PU has none of the 3 flags set, any memory locations are siloed in this PU. ii. Otherwise, traverse the function body of this PU, collect the alias tags of the memory locations read in this PU. For each alias tag, if it is aliased with any alias tag in the whole program interference set, it is not siloed. Otherwise it is siloed. iii. Write the alias tags of siloed references for each PU into the BE summary. 7. Testing: Splash-II benchmark suit is used to evaluate the efficiency of siloed reference analysis. However, due to Whirl_SSA bugs (siloed reference analysis requires Whirl_SSA enabled in IPL/IPA), not all the benchmarks of Splash-II can be compiled successfully. Table 1 shows static statistics of optimization opportunities enabled by siloed reference analysis. Table 1. Static statistics of optimization opportunities Benchmark Discription LPRE enabled Siloed memory locations fmm Fast Multipole n-body barnes n-body Simulation 3 32 volrend 3D Rendering 2 9 water-nsquared Molecular Dynamics fft Complex 1-D FFT 1 25

6 radix Integer Sort Future work: a. How to use the siloed reference result to update the mod/ref set in BE b. Flow-sensitive, region based siloed reference analysis. This requires modeling the semantics of synchronization primitives, including barrier and join. In order to distinguish different barrier objects, dynamic disambiguation might be needed. c. Sparse algorithm based on SSA representations. Reference: [1] Joisha et al, A technique for the effective and automatic reuse of classical compiler optimizations on multithreaded code, POPL 2011