Intel Atom Processor Z600 Series

Transcription

1 Intel Atom Processor Z600 Series Specification Update For the Intel Atom Processor Z670 on 45-nm Process Technology March 2012 Revision 002 Document Number:

2 Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See for details. The processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. For Enhanced Intel SpeedStep Technology: See the Processor Spec Finder at or contact your Intel representative for more information Intel, Intel Atom and Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2012, Intel Corporation. All Rights Reserved. 2 Specification Update

3 Contents Preface...5 Summary Tables of Changes...7 Identification Information Errata Specification Changes Specification Clarifications Documentation Changes Specification Update 3

4 Revision History Revision Version Description Revision Date Initial release April Removed BN33 Added BN35~BN40 March Specification Update

5 Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. Affected Documents Document Title Document Number/ Location Intel Atom Processor Z600 Series Datasheet Related Documents Document Title Document Number/ Location AP-485, Intel Processor Identification and the CPUID Instruction Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 1: Basic Architecture Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 2A: Instruction Set Reference Manual A-M Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 2B: Instruction Set Reference Manual N-Z Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3A: System Programming Guide Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3B: System Programming Guide Intel 64 and IA-32 Intel Architecture Optimization Reference Manual Intel 64 and IA-32 Architectures Software Developer s Manual Documentation Changes (see note 1) processor/applnots/ htm products/processor/manuals/ inde.htm NOTE:[Documentation changes for the Intel 64 and IA-32 Architecture Software Developer's Manual Volumes 1, 2A, 2B, 3A, and 3B is posted in a separate document, the Intel 64 and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link developer.intel.com/products/ processor/manuals/ inde.htm to access this documentation.] ACPI Specifications Intel SM35 Epress Chipset Datasheet Intel SM35 Epress Chipset Specification Update Specification Update 5

6 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, for e.g., core speed, L3 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a comple design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification. Note: Errata remain in the specification update throughout the product s lifecycle, or until a particular stepping is no longer commercially-available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.). 6 Specification Update

7 Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fi some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables use the following notations: Codes Used in Summary Tables Stepping X: Errata eists in the stepping indicated. Specification Change or Clarification that applies to this stepping. (No mark) or (Blank bo): This erratum is fied in listed stepping or specification change does not apply to listed stepping. Page (Page): Page location of item in this document. Status Doc: Plan Fi: Fied: : Document change or update will be implemented. This erratum may be fied in a future stepping of the product. This erratum has been previously fied. There are no plans to fi this erratum. Row Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document. Specification Update 7

8 Errata Summary Table # Title Steppings Impacted C-0 Status BN1 BN2 BN3 BN4 BN5 BN6 BN7 BN8 BN9 BN10 BN11 BN12 BN13 BN14 BN15 BN16 IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly Writes to IA32_DEBUGCTL MSR May Fail when FREEZE_LBRS_ON_PMI is Set Address Reported by Machine-Check Architecture (MCA) on L2 Cache Errors May be Incorrect Pending 87 FPU Eceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts Benign Eception after a Double Fault May Not Cause a Triple Fault Shutdown IA32_MC1_STATUS MSR Bit [60] Does Not Reflect Machine Check Error Reporting Enable Correctly Performance Monitoring Event for Outstanding Bus Requests Ignores AnyThread Bit IRET under Certain Conditions May Cause an Unepected Alignment Check Eception Thermal Interrupts are Dropped During and While Eiting Intel Deep Power Down State Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode Performance Monitoring Counter with AnyThread Bit set May Not Count on a Non-Active Thread GP and Fied Performance Monitoring Counters With AnyThread Bit Set May Not Accurately Count Only OS or Only USR Events PMI Request is Not Generated on a Counter Overflow if Its OVF Bit is Already Set in IA32_PERF_GLOBAL_STATUS Processor May Use an Incorrect Translation if the TLBs Contain Two Different Translations For a Linear Address A Write to an APIC Register Sometimes May Appear to Have Not Occurred An TPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after the Processor has Issued a Stop- Grant Special Cycle BN17 The Processor May Report a #TS Instead of a #GP Fault BN18 Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unepected Interrupt BN19 MOV To/From Debug Registers Causes Debug Eception BN20 Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations 8 Specification Update

9 Errata Summary Table # Title Steppings Impacted C-0 Status BN21 Values for LBR/BTS/BTM will be Incorrect after an Eit from SMM BN22 Incorrect Address Computed For Last Byte of FXSAVE/ FXRSTOR Image Leads to Partial Memory Update BN23 A Thermal Interrupt is Not Generated when the Current Temperature is Invalid BN24 Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unepected Thermal Interrupts BN25 Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior BN26 Fault on ENTER Instruction May Result in Unepected Values on Stack Frame BN27 With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Eception May Take Single Step Trap before Retirement of Instruction BN28 An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Eception BN29 Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Eceptions and May Push the Wrong Address Onto the Stack BN30 BTS (Branch Trace Store) and PEBS (Precise Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer BN31 Single Step Interrupts with Floating Point Eception Pending May Be Mishandled BN32 Unsynchronized Cross-Modifying Code Operations Can Cause Unepected Instruction Eecution Results BN33 The erratum not applicable therefore removed BN34 Processor Throttling at 87.5% May Cause System Hang BN35 THERMTRIP# Will Not Assert Prior to RESET# De-assertion BN36 Eternal STPCLK# Throttling May Cause System Hang During Thermal Event BN37 C6 Request May Cause a Machine Check if the Other Logical Processor is in C4 or C6 Specification Update 9

10 Errata Summary Table # Title Steppings Impacted C-0 Status BN38 EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine BN39 Integrated Graphics Unit Does Not Automatically Disable Legacy PCI Interrupts When MSI Are Enabled BN40 Outbound MSI From the PMU May Result in Live Lock And/ or System Hang When Simultaneously Occurring With an Inbound I/O Read Specification Changes No. SPECIFICATION CHANGES None for this revision of specification update. Specification Clarifications No. SPECIFICATION CLARIFICATIONS None for this revision of specification update. Documentation Changes No. DOCUMENTATION CHANGES None for this revision of specification update. 10 Specification Update

11 Identification Information Component Identification via Programming Interface The processor stepping can be identified by the following register contents: Reserved Etended Family 1 Etended Model 2 Reserved Processor Type 3 Family Code 4 Model Number 5 Stepping ID 6 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3: b 0010b 00b b 0001b NOTE: 1. The Etended Family, Bits [27:20] are used in conjunction with the Family Code, specified in Bits [11:8], to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium 4, or Intel Core processor family. 2. The Etended Model, Bits [19:16] in conjunction with the Model Number, specified in Bits [7:4], are used to identify the model of the processor within the processor s family. 3. The Processor Type, specified in Bits [13:12] indicates whether the processor is an original OEM processor, or a dual processor (capable of being used in a dual processor system). 4. The Family Code corresponds to Bits [11:8] of the EDX register after RESET, Bits [11:8] of the EAX register after the CPUID instruction is eecuted with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 5. The Model Number corresponds to Bits [7:4] of the EDX register after RESET, Bits [7:4] of the EAX register after the CPUID instruction is eecuted with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan. 6. The Stepping ID in Bits [3:0] indicates the revision number of that model. See table above for the processor stepping ID number in the CPUID information. When EAX is initialized to a value of 1, the CPUID instruction returns the Etended Family, Etended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register. Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is eecuted with a 2 in the EAX register. Specification Update 11

12 Component Marking Information The processor stepping can be identified by the following component markings: Figure 1-1. Processor Top-side Markings (Eample) GRP1LINE1 GRP1LINE1 GRP2LINE1 GRP3LINE1 Legend: GRP1LINE1: GRP2LINE1: GRP3LINE1: GRP4LINE1: Legend: GRP1LINE1: GRP2LINE1: GRP3LINE1: GRP4LINE1: Mark Tet (Engineering Mark) SPEED (eample: 1.50GHz) {FPO} QDF ES INTEL{M}{C}'YY{e1} Mark Tet (Production Mark) PROC# SPEED (eample: Z GHZ) {FPO} SSPEC INTEL{M}{C}'YY{e1} 2D Matri Mark Table 1-1. Processor Identification Stepping QDF Number CPUID Core Frequency (GHz) / DDR2 (MHz) Notes C-0 SLC2P / 800 Intel Atom Z670 Processor 12 Specification Update

13 Errata BN1. IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly The IO_SMI bit in SMRAM s location 7FA4H is set to 1 by the CPU to indicate a System Management Interrupt (SMI) occurred as the result of eecuting an instruction that reads from an I/O port. Due to this erratum, the IO_SMI bit may be incorrectly set by: A SMI that is pending while a lower priority event is eecuting A REP I/O read A I/O read that redirects to MWAIT Implication: SMM handlers may get false IO_SMI indication. Workaround:The SMM handler has to evaluate the saved contet to determine if the SMI was triggered by an instruction that read from an I/O port. The SMM handler must not restart an I/O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I/O port address. BN2. Writes to IA32_DEBUGCTL MSR May Fail when FREEZE_LBRS_ON_PMI is Set When the FREEZE_LBRS_ON_PMI, IA32_DEBUGCTL MSR (1D9H) bit [11], is set, future writes to IA32_DEBUGCTL MSR may not occur in certain rare corner cases. Writes to this register by software or during certain processor operations are affected. Implication: Under certain circumstances, the IA32_DEBUGCTL MSR value may not be updated properly and will retain the old value. Intel has not observed this erratum with any commercially available software. Workaround:Do not set the FREEZE_LBRS_ON_PMI bit of IA32_DEBUGCTL MSR. BN3. Address Reported by Machine-Check Architecture (MCA) on L2 Cache Errors May be Incorrect When an L2 Cache error occurs (Error code 0010A or 0110A reported in IA32_MCi_STATUS MSR bits [15:0]), the address is logged in the MCA address register (IA32_MCi_ADDR MSR). Under some scenarios, the address reported may be incorrect. Implication: Software should not rely on the value reported in IA32_MCi_ADDR MSR for L2 Cache errors. Workaround:None identified Specification Update 13

14 BN4. Pending 87 FPU Eceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts Interrupts that are pending prior to the eecution of the STI (Set Interrupt Flag) instruction are normally serviced immediately after the instruction following the STI. An eception to this is if the following instruction triggers a #MF. In this situation, the interrupt should be serviced before the #MF. Because of this erratum, if following STI, an instruction that triggers a #MF is eecuted while STPCLK#, Enhanced Intel SpeedStep Technology transitions or Thermal Monitor events occur, the pending #MF may be serviced before higher priority interrupts. Implication: Software may observe #MF being serviced before higher priority interrupts. BN5. Benign Eception after a Double Fault May Not Cause a Triple Fault Shutdown According to the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3A, Eception and Interrupt Reference, if another eception occurs while attempting to call the double-fault handler, the processor enters shutdown mode. Due to this erratum, any benign faults while attempting to call double-fault handler will not cause a shutdown. However Contributory Eceptions and Page Faults will continue to cause a triple-fault shutdown. Implication: If a benign eception occurs while attempting to call the double-fault handler, the processor may hang or may handle the benign eception. Intel has not observed this erratum with any commercially available software. Workaround:None identified BN6. IA32_MC1_STATUS MSR Bit [60] Does Not Reflect Machine Check Error Reporting Enable Correctly IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at the time of the last update to the IA32_MC1_STATUS MSR. Due to this erratum, IA32_MC1_STATUS MSR bit [60] instead reports the current value of the IA32_MC1_CTL MSR enable bit. Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the enable bit in the IA32_MC1_CTL MSR at the time of the last update. Workaround:None identified 14 Specification Update

15 BN7. Performance Monitoring Event for Outstanding Bus Requests Ignores AnyThread Bit The Performance Monitoring Event of Outstanding Bus Requests will ignore the AnyThread bit (IA32_PERFEVTSEL0 MSR (186H)/ IA32_PERFEVTSEL1 MSR (187H) bit [21]) and will instead always count all transactions across all logical processors, even when AnyThread is clear. Implication: The performance monitor count may be incorrect when counting only the current logical processor s outstanding bus requests on a processor supporting Hyper- Threading Technology. BN8. IRET under Certain Conditions May Cause an Unepected Alignment Check Eception In IA-32e mode, it is possible to get an Alignment Check Eception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected. This erratum can occur if the EFLAGS value on the stack has the AC flag set, and the interrupt handler's stack is misaligned. In IA-32e mode, RSP is aligned to a 16-byte boundary before pushing the stack frame. Implication: In IA-32e mode, under the conditions given above, an IRET can get a #AC even if alignment checks are disabled at the start of the IRET.This erratum can only be observed with a software generated stack frame. Workaround:Software should not generate misaligned stack frames for use with IRET. BN9. Thermal Interrupts are Dropped During and While Eiting Intel Deep Power Down State Thermal interrupts are ignored while the processor is in Intel Deep Power Down State as well as during a small window of time while eiting from Intel Deep Power Down State. During this window, if the PROCHOT signal is driven or the internal value of the sensor reaches the programmed thermal trip point, then the associated thermal interrupt may be lost. Implication: In the event of a thermal event while a processor is waking up from Intel Deep Power Down State, the processor will initiate an appropriate throttle response. However, the associated thermal interrupt generated may be lost. Specification Update 15

16 BN10. Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode During the transition from real mode to protected mode, if an SMI (System Management Interrupt) occurs between the MOV to CR0 that sets PE (Protection Enable, bit 0) and the first far JMP, the subsequent RSM (Resume from System Management Mode) may cause the lower two bits of CS segment register to be corrupted. Implication: The corruption of the bottom two bits of the CS segment register will have no impact unless software eplicitly eamines the CS segment register between enabling protected mode and the first far JMP. Intel 64 and IA-32 Architectures Software Developer s Manual Volume 3A: System Programming Guide, Part 1, in the section titled Switching to Protected Mode recommends the far JMP immediately follows the write to CR0 to enable protected mode. Intel has not observed this erratum with any commercially available software. BN11. Performance Monitoring Counter with AnyThread Bit set May Not Count on a Non-Active Thread A performance counter with the AnyThread bit (IA32_PERFEVTSEL0 MSR (186H)/ IA32_PERFEVTSEL1 MSR (187H) bit [21], IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] for IA32_FIXED_CTR0, bit [6] for IA32_FIXED_CTR1, bit [10] for IA32_FIXED_CTR2) set should count that event on all logical processors on that core. Due to this erratum, a performance counter on a logical processor which has requested to be placed in the Intel Deep Power Down State may not count events that occur on another logical processor. Implication: The performance monitor count may be incorrect when the logical processor is asleep but still attempting to count another logical processor s events. This will only occur on processors supporting Hyper-Threading Technology (HT Technology). BN12. GP and Fied Performance Monitoring Counters With AnyThread Bit Set May Not Accurately Count Only OS or Only USR Events A fied or GP (general purpose) performance counter with the AnyThread bit (IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] for IA32_FIXED_CTR0, bit [6] for IA32_FIXED_CTR1, bit [10] for IA32_FIXED_CTR2; IA32_PERFEVTSEL0 MSR (186H)/ IA32_PERFEVTSEL1 MSR (187H) bit [21]) set may not count correctly when counting only OS (ring 0) events or only USR (ring >0) events. The counters will count correctly if they are counting both OS and USR events or if the AnyThread bit is clear. Implication: A performance monitor counter may be incorrect when it is counting for all logical processors on that core and not counting at all privilege levels. This erratum will only occur on processors supporting multiple logical processors per core. 16 Specification Update

17 BN13. PMI Request is Not Generated on a Counter Overflow if Its OVF Bit is Already Set in IA32_PERF_GLOBAL_STATUS If a performance counter overflows and software does not clear the corresponding OVF (overflow) bit in IA32_PERF_GLOBAL_STATUS MSR (38Eh) then future overflows of that counter will not trigger PMI (Performance Monitoring Interrupt) requests. Implication: If software does not clear the OVF bit corresponding to a performance counter then future counter overflows may not cause PMI requests. Workaround:Software should clear the IA32_PERF_GLOBAL_STATUS.OVF bit in the PMI handler. BN14. Processor May Use an Incorrect Translation if the TLBs Contain Two Different Translations For a Linear Address The TLBs may contain both ordinary and large-page translations for a 4-KByte range of linear addresses. This may occur if software modifies a PDE (page-directory entry) that is marked present to set the PS bit (this changes the page size used for the address range). If the two translations differ with respect to page frame, permissions, or memory type, the processor may use a page frame, permissions, or memory type that corresponds to neither translation. Implication: Due to this erratum, software may not function properly if it sets the PS flag in a PDE and also changes the page frame, permissions, or memory type for the linear addresses mapped through that PDE. Workaround:Software can avoid this problem by ensuring that the TLBs never contain both ordinary and large-page translations for a linear address that differ with respect to page frame, permissions, or memory type. BN15. A Write to an APIC Register Sometimes May Appear to Have Not Occurred With respect to the retirement of instructions, stores to the uncacheable memory based APIC register space are handled in a non-synchronized way. For eample if an instruction that masks the interrupt flag, e.g. CLI, is eecuted soon after an uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the interrupt masking operation may take effect before the actual priority has been lowered. This may cause interrupts whose priority is lower than the initial TPR, but higher than the final TPR, to not be serviced until the interrupt enabled flag is finally set, i.e. by STI instruction. Interrupts will remain pending and are not lost. Implication: In this eample the processor may allow interrupts to be accepted but may delay their service. Workaround:This non-synchronization can be avoided by issuing an APIC register read after the APIC register write. This will force the store to the APIC register before any subsequent instructions are eecuted. No commercial operating system is known to be impacted by this erratum. Specification Update 17

18 BN16. An TPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after the Processor has Issued a Stop-Grant Special Cycle According to the FSB (Front Side Bus) protocol specification, no FSB cycles should be issued by the processor once a Stop-Grant special cycle has been issued to the bus. If TPR update transactions are enabled by clearing the IA32_MISC_ENABLES[bit 23] at the time of Stop-Clock assertion, an TPR update transaction cycle may be issued to the FSB after the processor has issued a Stop Grant Acknowledge transaction. Implication: When this erratum occurs in systems using C-states C2 (Stop-Grant State) and higher the result could be a system hang. Workaround:The IA32 firmware must leave the TPR update transactions disabled (default). BN17. The Processor May Report a #TS Instead of a #GP Fault A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS eception) instead of a #GP fault (general protection eception). Implication: Operating systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. BN18. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unepected Interrupt If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and mask all interrupts at the same or lower priority. Workaround:Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector was programmed as masked. This ISR routine must do an EOI to clear any unepected interrupts that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious vector should not be used when writing the LVT. 18 Specification Update

19 BN19. MOV To/From Debug Registers Causes Debug Eception When in V86 mode, if a MOV instruction is eecuted to/from a debug registers, a general-protection eception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug eception (#DB) is generated instead. Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to eecute a MOV on debug registers in V86 mode, a debug eception will be generated instead of the epected general-protection fault. Workaround:In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is generally set and used by debuggers. The debug eception handler should check that the eception did not occur in V86 mode before continuing. If the eception did occur in V86 mode, the eception may be directed to the general-protection eception handler. BN20. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations An eternal A20M# pin if enabled forces address Bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte. However, if all of the following conditions are met, address Bit 20 may not be masked. Paging is enabled Linear address has bit-20 set Address references a large page A20M# is enabled Implication: When A20M# is enabled and an address references a large page the resulting translated physical address may be incorrect. This erratum has not been observed with any commercially-available operating system. Workaround:Operating systems should not allow A20M# to be enabled if the masking of address Bit 20 could be applied to an address that references a large page. A20M# is normally only used with the first megabyte of memory. BN21. Note: Values for LBR/BTS/BTM will be Incorrect after an Eit from SMM After a return from SMM (System Management Mode), the CPU will incorrectly update the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as a BTM on the system bus will also be incorrect. This issue would only occur when one of the three above-mentioned debug support facilities are used. Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Specification Update 19

20 BN22. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address eceeds the 64-KB limit while the processor is operating in 16-bit mode or if a memory address eceeds the 4- GB limit while the processor is operating in 32-bit mode. Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as epected but the memory state may be only partially saved or restored. Workaround:Software should avoid memory accesses that wrap around the respective 16-bit and 32-bit mode memory limits. BN23. A Thermal Interrupt is Not Generated when the Current Temperature is Invalid When the DTS (Digital Thermal Sensor) crosses one of its programmed thresholds it generates an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Due to this erratum, if the DTS reaches an invalid temperature (as indicated IA32_THERM_STATUS MSR bit[31]) it does not generate an interrupt even if one of the programmed thresholds is crossed and the corresponding log bits become set. Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is crossed. BN24. Programming the Digital Thermal Sensor (DTS) Threshold May Cause Unepected Thermal Interrupts Software can enable DTS thermal interrupts by programming the thermal threshold and setting the respective thermal interrupt enable bit. When programming DTS value, the previous DTS threshold may be crossed. This will generate an unepected thermal interrupt. Implication: Software may observe an unepected thermal interrupt occur after reprogramming the thermal threshold. Workaround:In the ACPI/OS implement a workaround by temporarily disabling the DTS threshold interrupt before updating the DTS threshold value. BN25. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior Returning back from SMM mode into real mode while EFLAGS.VM is set in SMRAM may result in unpredictable system behavior. Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commercially available software. Workaround:SMM software should not change the value of EFLAGS.VM in SMRAM. 20 Specification Update

21 BN26. Fault on ENTER Instruction May Result in Unepected Values on Stack Frame The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if eecution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unepected values (that is, residual stack data as a result of processing the fault). Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction. Please refer to Procedure Calls For Block-Structured Languages in the Intel 64 and IA-32 Architectures Software Developer s Manual-Vol.1, Basic Architecture, for information on the usage of the ENTER instructions. This erratum is not epected to occur in Ring-3. Faults are usually processed in Ring-0 and stack switch occurs when transferring to Ring-0. Intel has not observed this erratum on any commercially available software. BN27. With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Eception May Take Single Step Trap before Retirement of Instruction If an FP instruction generates an unmasked eception with the EFLAGS.TF=1, it is possible for eternal events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the eecution of the original FP instruction completes. Implication: A single step trap will be taken when not epected. Specification Update 21

22 BN28. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Eception A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints until after eecution of the following instruction. This is intended to allow the sequential eecution of MOV SS/POP SS and MOV [r/e]sp, [r/e]bp instructions without having an invalid stack during interrupt handling. However, an enabled debug breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is followed by an instruction that signals a floating point eception rather than a MOV [r/e]sp, [r/e]bp instruction. This results in a debug eception being signaled on an unepected instruction boundary since the MOV SS/POP SS and the following instruction should be eecuted atomically. Implication: This can result in incorrect signaling of a debug eception and possibly a mismatched Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV [r/e]sp, [r/e]bp, there may be a mismatched Stack Segment and Stack Pointer on any eception. Intel has not observed this erratum with any commercially available software, or system. Workaround:As recommended in the Intel 64 and IA-32 Architectures Software Developer s Manual, the use of MOV SS/POP SS in conjunction with MOV [r/e]sp and [r/e]bp will avoid the failure since the MOV [r/e]sp and [r/e]bp will not generate a floating point eception. Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum. BN29. Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Eceptions and May Push the Wrong Address Onto the Stack Normally, when the processor encounters a Segment Limit or Canonical Fault due to code eecution, a #GP (General Protection Eception) fault is generated after all higher priority interrupts and eceptions are serviced. Due to this erratum, if RSM (Resume from System Management Mode) returns to eecution flow that results in a Code Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher priority Interrupt or Eception (for eample NMI (Non-Maskable Interrupt), Debug break(#db), Machine Check (#MC), etc.). If the RSM attempts to return to a noncanonical address, the address pushed onto the stack for this #GP fault may not match the non-canonical address that caused the fault. Implication: Operating systems may observe a #GP fault being serviced before higher-priority interrupts and eceptions. Intel has not observed this erratum on any commerciallyavailable software. 22 Specification Update

23 BN30. BTS (Branch Trace Store) and PEBS (Precise Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer If the BTS/PEBS buffer is defined such that: The difference between BTS/PEBS buffer base and BTS/PEBS absolute maimum is not an integer multiple of the corresponding record sizes BTS/PEBS absolute maimum is less than a record size from the end of the virtual address space The record that would cross BTS/PEBS absolute maimum will also continue past the end of the virtual address space A BTS/PEBS record can be written that will wrap at the 4-G boundary (IA32) or 2^64 boundary (EM64T mode), and write memory outside of the BTS/PEBS buffer. Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary (EM64T mode), and defines the buffer such that it does not hold an integer multiple of records can update memory outside the BTS/PEBS buffer. Workaround:Define BTS/PEBS buffer such that BTS/PEBS absolute maimum minus BTS/PEBS buffer base is integer multiple of the corresponding record sizes as recommended in the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3. BN31. Single Step Interrupts with Floating Point Eception Pending May Be Mishandled In certain circumstances, when a floating point eception (#MF) is pending during single-step eecution, processing of the single-step debug eception (#DB) may be mishandled. Implication: When this erratum occurs, #DB will be incorrectly handled as follows: #DB is signaled before the pending higher priority #MF (Interrupt 16) #DB is generated twice on the same instruction Specification Update 23

24 BN32. Unsynchronized Cross-Modifying Code Operations Can Cause Unepected Instruction Eecution Results The act of one processor, or system bus master, writing data into a currently eecuting code segment of a second processor with the intent of having the second processor eecute that data as code is called cross-modifying code (XMC). XMC that does not force the second processor to eecute a synchronizing instruction, prior to eecution of the new code, is called unsynchronized XMC. Software using unsynchronized XMC to modify the instruction byte stream of a processor can see unepected or unpredictable eecution behavior from the processor (that is, eecuting the modified code). Implication: In this case, the phrase unepected or unpredictable eecution behavior encompasses the generation of most of the eceptions listed in the Intel 64 and IA- 32 Architectures Software Developer s Manual, Volume 3A: System Programming Guide, including a General Protection Fault (#GP) or other unepected behaviors. Workaround:In order to avoid this erratum, programmers should use the XMC synchronization algorithm as detailed in the Intel 64 and IA-32 Architectures Software Developer s Manual, Volume 3A: System Programming Guide, Section: Handling Self- and Cross- Modifying Code. BN33. The erratum not applicable therefore removed BN34. Processor Throttling at 87.5% May Cause System Hang At certain processor core ratios, a request for 87.5% throttling (on-demand clock modulation duty cycle) may cause the processor to hang. Implication: Due to this erratum, the system may hang. Workaround:A Power Management Unit firmware code change has been identified and may be implemented as a workaround for this erratum. Throttling at 87.5% will not be supported and any requests for 87.5% will be re-directed to 75%. BN35. THERMTRIP# Will Not Assert Prior to RESET# De-assertion Potentially catastrophic temperature should be detected and signaled using the THERMTRIP# mechanism after PWRGD assertion. Due to this erratum, THERMTRIP# functionality is not supported during the period from PWRGD assertion to RESET# deassertion. After RESET# de-assertion, THERMTRIP# functions correctly. Implication: Due to this erratum, THERMTRIP# will not function until after RESET# de-assertion. 24 Specification Update

25 BN36. Eternal STPCLK# Throttling May cause System Hang During Thermal Event During a TM1 thermal event when eternal STPCLK# throttling is enabled through software, the time between STPCLK# assertion and STOP GRANT may not be enough for the processor to de-assert STPCLK# and eecute instructions. Implication: When this erratum occurs, the system will hang. Workaround:Software should not enable software-controlled STPCLK# throttling. BN37. C6 Request May Cause a Machine Check if the Other Logical Processor is in C4 or C6 A machine check may be generated if a logical processor requests the C6 C-state and the other logical processor is in either C4 or C6 C-states. Implication: This erratum may result in unepected machine-check eceptions. Workaround:It is possible for the BIOS to contain a workaround for this erratum. BN38. EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine If core C6 is entered after the start of an interrupt service routine but before a write to the APIC EOI (End of Interrupt) register, and the core is woken up by an event other than a fied interrupt source the core may drop the EOI transaction the net time APIC EOI register is written and further interrupts from the same or lower priority level will be blocked. Implication: EOI transactions may be lost and interrupts may be blocked when core C6 is used during interrupt service routines. Workaround:Software should check the ISR register and enter CD1 only if any interrupt is in service BN39. Integrated Graphic Unit Does Not Automatically Disable Legacy PCI Interrupts When MSI Are Enabled The integrated graphic unit fails to disable legacy PCI interrupts when MSI (Message Signaled Interrupts) are enabled. Implication: Due to this erratum, the processor will fail to be compliant with the PCI specification. This erratum does not apply to operating systems that cannot enable MSI or eplicitly disable legacy PCI interrupts when MSI are enabled. Specification Update 25

26 BN40. Outbound MSI from The PMU May Result in Live Lock And /or System Hang When Simultaneously Occurring With an Inbound I/O Read The Power Management Unit (PMU) is capable of generating Message Signaled Interrupts (MSI) to the processor. In specific corner cases, an outbound MSI from the PMU may occur simultaneously with an inbound I/O read and may result in live lock and/or a system hang. Implication: When this erratum occurs, the processor may live lock and/or result in a system hang. The PMU will not be able to support MSI for display power up and therm trip events. Workaround:It is possible for the firmware and graphics driver to contain a workaround for this erratum. With this workaround, the PMU MSIs will be disabled and hence PMU supported therm trip feature will not be available. 26 Specification Update

27 Specification Changes There are no specification changes in this revision of the specification update. Specification Update 27

28 Specification Clarifications There are no specification clarifications in this revision of the specification update. 28 Specification Update

29 Documentation Changes There are no document changes in this revision of the specification update. Specification Update 29