PROGRAMMABLE LCD CONTROLLER/DRIVER

Transcription

1 µpd5 PROGRAMMABLE LCD CONTROLLER/DRIVER Document No. IEA-5A (nd edition) (O. D. No. IEM-5E) Data Published March 99 P Printed in Japan

2 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M 9. 5

3 Main revisions in this edition Pages Description Chapter µpd5 µpd5b Deletion of description related to µcom-na

4 CONTENTS CHPATER GENERAL.... General.... Internal Segment Decoder segment decoder segment decoder..... The Input of serial data.... The Commands of µpd MODE SET SYNCHRONIZED TRANSFER UNSYNCHRONIZED TRANSFER PAUSE TRANSFER BLINKING ON..... BLINKING OFF..... DISPLAY ON..... DISPLAY OFF WITH SEGMENT DECODER..... WITHOUT SEGMENT DECODER..... LOAD DATA POINTER..... WRITE DATA MEMORY..... OR DATA MEMORY..... AND DATA MEMORY CLEAR DATA MEMORY..... WRITE BLINKING DATA MEMORY..... OR BLINKING DATA MEMORY..... AND BLINKING DATA MEMORY CLEAR BLINKING DATA MEMORY... CHAPTER EXAMPLES OF APPLICATIONS Matters Attended to in a Program System Using µpd5b Interface with µpd5b and µpd The connection of µpd5 and LCD..... Structure of the display data within the program memory of µpd5b..... Program example How to set wait time... APPENDIX A BIAS OF LCD AND THE NUMBER OF TIME SHARING DRIVES... 5 APPENDIX B TIME SHARING DRIVE AND THE MAXIMUM NUMBER OF DISPLAY ELEMENTS. APPENDIX C DISPLAY TIMING AND SEGMENT DRIVE SIGNALS... 9 APPENDIX D LCD POWER SOURCE CIRCUITS... - i -

5 CHAPTER GENERAL. General µpd5 is an LCD (Liquid Crystal Display) controller/driver which is programmable by software. Figure-. shows the pin configurations for µpd5. Figure -. shows a functional block diagram. The µpd5 interfaces with the CPU through a serial ports, in a microcomputer application system, for directly controlling LCD by static -, - or -time sharing. It also incorporates a segment decoder for generating specific segment patterns and can also control blinking operations. Figure-. Pin Configurations S S S S S S5 S S S S9 S S CLI S S S5 S S S S S COM COM COM COM N.C. CL SYNC VLC VLC VLC VSS VDD SCK SI CS BUSY C/D RESET S9 S S S S5 S VDD S S S S S9 S

6 S S S9 S S COM COM COM COM VLC LCD DRIVER VLC VLC LCD TIMING CONTROL DISPLAY DATA LATCH SYNC CL CL VDD OSC SEGMENT DECODER DATA MEMORY DATA POINTER BLINKING DATA MEMORY Figure -. Block Diagram CHAPTER GENERAL VSS RESET CS COMMAND/DATA REGISTER C/D WRITE CONTROL COMMAND DECODER BUSY SERIAL INTERFACE SI SCK

7 CHAPTER GENERAL. Internal Segment Decoder µpd5 incorporates -segment type and -segment type decoders, taking in serial data at the SI pin, and generating patters as shown in Figure -. and Figure segment decoder A -segment decoder, which performs - or -time sharing drive can generate numeric characters to 9, five kinds of sings and blank display codes. When the LCD display is made with the segment decoder output (display code), the LCD configuration shown in Figure -. should be used. With LCD that is not configured like this, different display patterns are appeared. Figure -. -segment Type LCD Make the connection in the following configuration for a -time sharing type of LCD. SEG-N + COM,, SEG-N + SEG-N,,,,,, COM COM a f b g e c d DP SEG N :b, c, DP SEG N + :a, d, g SEG N + :e, f COM :a, b, f COM :c, e, g COM :d, DP

8 CHAPTER GENERAL In the case of -time sharing, make the following connection. SEG-N,,, COM COM,, COM COM SEG-N + a f b g e c d DP SEG N :a, b, c, DP SEG N + :d, e, f, g COM :a, f COM :b, g COM :c, e COM :d, DP

9 CHAPTER GENERAL Figure -. -Segment Data memory Data memory Data (HEX) Display pattern -time sharing N + N + N -time sharing N + N Data (HEX) Display pattern -time sharing N + N + N -time sharing N + N 5 D F 9 B E A A B F C 5 D 5 B 5 D A F 5 E E F 5

10 CHAPTER GENERAL.. -segment decoder A -segment decoder, which performs -time sharing drive, can generate kinds of alphanumeric chracters, kinds of signs and blank display codes. Figure -5. -Segment Type In the case of a -segment type, only the -time sharing can be used. The relation between SEGMENT and COMMON is realized by the following connection. SEG - N + SEG - N +,,,,,,,,,,,,,,, COM COM COM SEG - N + SEG - N COM Figure -. -Segment Type LCD a f g h i b e j l m d n k c DP SEG SEG SEG SEG COM COM COM COM N + :a, b, c, DP N :h, i, j, k, n N + :d, e, f N + :g, j, l, m :a, g, h :b, i, j, f :c, e, k, l :d, m, n, DP Shown next is the configuration of input data, display pattern and the display data written in the data memory. In the case of a -segment type, the least significant bits (D to D) are decoded, whereas the least significant bits (D to D) are decoded in the -segment type. In this case, the input data and display pattern of the -segment type correspond to the -bit ASCII code. The beginning write address for the display data should be Address N.

11 CHAPTER GENERAL Figure -. -Segment 5 F A A Display pattern Data memory N+ Data (HEX) 5 9 A B C D E F N+ N+ N A F 5 B Display pattern Data memory N+ N+ N+ N 5 5 E C A E E A A C Display pattern Data memory N+ N+ N+ N 5 C E E E C E E 5 A 5 9 D Display pattern Data memory N+ N+ N+ N 5 E E C A Most significant bits Least significant bits

12 CHAPTER GENERAL.. The Input of serial data Serial data is synchronized by the serial clock in units of bits and inputted to the SI pin at the top of MSB. As BUSY becomes low when CS becomes low, synchronization is made with SCK when the BUSY signal becomes high after internal processing (SCK counter and data pointer are cleared), and the first bit (MSB) is transferred. Serial data is transferred to the serial register in units of bit by the rise of SCK. Inputting sight serial clock transitions causes all -bit data to be transferred to the serial register. Upon the rise of the th serial clock BUSY becomes low, the state of C/D pin is fetched, and it is determined whether the -bit data is a command or data. Then, the contents of the serial register are fetched by the command/data register. When two bytes or more of serial data are inputted continuously, CS should be left low until the input of all the bytes is completed. Every time the input of one byte is completed, BUSY becomes low. As BUSY becomes high when serial data is fetched by the command/data register from the serial register, the next serial data can be inputted. When CS is raised after the input of all serial data is completed, the contents of the data memory are displayed. Do not raise CS while a byte is being transferred (i. e. in the state where the serial clock is not input through eight transitions). When it is necessary to make the temporarily stop transfer due to a CPU interruption while several bytes are being transferred, make CS high after executing the PAUSE TRANSFER command. IF CS is made high in this case, transfer is not made from the data memory to the data display latch. To start the transfer of the serial data again, CS is made low like an ordinary transfer start. In this case, however, only the SCK counter is cleared and the data pointer keeps the contents before interruption. Therefore, when the start of the next serial data starts, the transferred data is processed as the subsequent data. Figure -. One-byte Input Serial data (SI pin) D D D5 D D D SCK CS BUSY High impedance High impedance C/D Figure -9. The Continuous Input of 5 Bytes Serial data Byte Byte Byte Byte Byte 5 CS BUSY

13 CHAPTER GENERAL. The Commands of µpd5.. MODE SET M M M F F This command sets the time sharings number for LCD display, the bias method and frame frequency. (a) M and M specify time sharing. M M time sharing drive time sharing drive time sharing drive Static drive (b) M specifies the bias method. M / bias method / bias method / Static (c) F and F sets the frame frequency. F F Scale ratio SYNCHRONIZED TRANSFER This command controls the re-writing of display data. Raising the CS signal usually re-writes the display data (i. e. the transfer of display data from the data memory to the display data latch). After this command is executed, the display data is re-written at the beginning of the alternating drive period (frame frequency times the number of time sharings) when the CS signal is raised... UNSYNCHRONIZED TRANSFER This command controls the re-writing of display data. After this command is executed, the display data is re-written upon raising the CS pin. 9

14 CHAPTER GENERAL.. PAUSE TRANSFER This commands inhibits the re-writing of display data. After this command is executed, data displayed at the rise of the first CS pin is not re-written, but it is retained until the second CS pin is raised. Furthermore, raising the first CS pin does not clear the data pointer. This command is used when the CS pin must be raised temporarily due to a CPU interrupt that occurred while the serial data is being inputted...5 BLINKING ON K This command sets the blinking state. The least significant bit K is used to set the blinking frequency. K fosc/ (Hz) fosc/ (Hz) fosc: Oscillation frequency.. BLINKING OFF Execution of this command stops the blinking operation... DISPLAY ON After this command is executed, the LCD display begins according to the display data of the display data latch... DISPLAY OFF Execution of this command makes non-selective the relation between all the common drive signals and the segment drive signals.

15 CHAPTER GENERAL As a result, the display is extinguished. This command does not affect the transfer of display data from the data memory to the display data latch...9 WITH SEGMENT DECODER Data inputted after this command is executed is sent to the segment decoder, and the code obtained by the segment decoder is written into the data memory... WITHOUT SEGMENT DECODER Data inputted after this command is executed is written into the data memory without passing the segment decoder... LOAD DATA POINTER D D D D D This command sets the immediate data D-D in the data pointer... WRITE DATA MEMORY D D D D This command stores the immediate data D-D in the data memory addressed by the data pointer, incrementing by (+) the contents of the data pointer... OR DATA MEMORY D D D D The contents of the data memory addressed by the data pointer and the immediate data D-D are ORed, and the result is stored in the data memory. The contents of the data pointer are incremented by (+).

16 CHAPTER GENERAL.. AND DATA MEMORY D D D D The contents of the data memory addressed by the data pointer and the immediate data D-D are ANDed; the result is stored in the data memory. The contents of the data pointer are incremented by (+)...5 CLEAR DATA MEMORY This command clears the contents of the data memory and the data pointer... WRITE BLINKING DATA MEMORY D D D D This command stores the immediate data D-D in the blinking data memory addressed by the data pointer, incrementing the contents of the data pointer by (+)... OR BLINKING DATA MEMORY D D D D The contents of the blinking data memory addressed by the data pointer and the immediate data D-D are ORed, the result is stored in the blinking data memory. The contents of the data pointer are incremented by (+)... AND BLINKING DATA MEMORY D D D D The contents of the blinking data memory addressed by the data pointer and the immediate data D-D are ANDed, the result is stored in the blinking data memory. The contents of the data pointer are incremented by (+).

17 CHAPTER GENERAL..9 CLEAR BLINKING DATA MEMORY This command clears the contents of the blinking data memory and the data pointer.

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19 CHAPTER EXAMPLES OF APPLICATIONS. Matters Attended to in a Program (a) The high-level signal to the CS pin must have clock cycles or more at the clock frequency. CS clock cycles or more (b) When the data is transferred, be sure to check the BUSY pin to confirm whether or not the data is transferable. (c) Be sure not to raise the chip select signal while the data is being transferred. Raising it during transfer may cause a malfunction. CS SCK. System Using µpd5b This section introduces an example where a CMOS -bit one-chip microcomputer (µpd5b) is used as the control system for the µpd5. In this example, it is presumed that the display panel which uses a -segment - digit LCD panel writes the data in the mode to use the segment decoder. In addition, it is presumed that this program does not test the BUSY signal outputted by µpd5, and that the serial data is sent... Interface with µpd5b and µpd5 Figure -. Interface with µpd5b P CS CL P C/D R P/SO SI CL P/SCK SCK RESET R CS µ PD5B µ PD5 5

20 CHAPTER EXAMPLES OF APPLICATIONS Shown below are the pin functions of µpd5b in this interface. P: Used for the chip Select signal. P: Specifies command/data for the serial data to be written. P/SO: Used for serial data output (command/data). P/SCK: Used for the serial clock output. The clock for µpd5 can be easily made only by connecting resistance to clock the pins (CL, CL). Example: R = kω fclk khz (TYP.) (VDD = 5. V) When it is necessary to adjust the clock with a variable resistance, use R= kω ± 5 %... The connection of µpd5 and LCD Figure -. Example of Connection for LCD Display S to S S to S S to S S9 to S S5 to S S to S S to S S to S COM to COM µpd5.. Structure of the display data within the program memory of µpd5b This section shows the structure of the data written in the program memory of µpd5b to display D5NEC, as shown in the example. Program memory Address 5H C ; D 5H B ; 5H B ; 5H B ; 5H B5 ; 5 55H CE ; N 5H C5 ; E 5H C ; C

21 CHAPTER EXAMPLES OF APPLICATIONS Write the data in µpd5 in the order 5H 5H of the program memory... Program example This section shows a program to control the µpd5 by dividing one into the INITIALIZE routine, data routine, the display routine of DP, weight routine and serial data transfer routine. This section shows a program which only controls µpd5. It is assumed, therefore, that the data memory of µpd5b has been initialized or the stack pointer has already been set. () INITIALIZE Routine In the INITIALIZE routine, each mode is set after the RESET for µpd5 is removed, the display RAM is cleared and the command of display start is trnasferred. Flowchart INIT C/D = CS = ; Command specification Chip Select setting WAIT ; BUSY = Wait MODE SET ; Mode setting SIOUT ; Serial data transfer (Command issue) WITH SEGMENT DECODER ; Segment decoder use SIOUT ; Command issue CLEAR DATA MEMORY ; Data RAM Clear SIOUT ; Command issue DISPLAY ON ; Display start SIOUT ; Command issue END

22 CHAPTER EXAMPLES OF APPLICATIONS Program list INIT: LAI EH OP ; C/D = CS = CALL WAIT ; WAIT BUSY LHLI FH LAI ; MODE SET ST ; COMMAND SET LAI ; CALL SIOUT ; COMMAND OUT LAI 5 ; ST ; WITH SEGMENT DECODER LAI ; CALL SIOUT ; LAI ; ST ; CLEAR DATA MEMORY LAI ; CALL SIOUT LAI ; ST ; DISPLAY ON CALL SIOUT ; INIT END In this program, CS is not raised after issuing the DISPLAY ON command. If it is necessary to raise CS, be sure to hold CS = for clocks or more. (The µpd5 clock) (In the case of UNSYNCHRONIZED TRANSFER MODE)

23 CHAPTER EXAMPLES OF APPLICATIONS () Data routine The data routine is used to write display data. Flowchart DATA C/D = CS = ; Command specification Chip Select setting WAIT LOAD DATA POINTER ; Data pointer setting SIOUT ; Command issue C/D = ; Data specification DATA ADDRESS SET ; Setting of the table address of the display data DATA SET ; Setting of the display data SIOUT ; Display data issue DATA ADDRESS- ; Display data address decrement NO TRANSFER END YES C/D = CS = ; Command specification END 9

24 CHAPTER EXAMPLES OF APPLICATIONS Program list DATA: LAI EH OP ; C/D =, CS = CALL WAIT LHLI FH ; LAI ; LOAD DATA POINTER ST ; (DP = ) LAI EH ; CALL SIOUT ; COMMAND OUT LAI CH OP ; C/D =, CS = LAI ; DATA NO. LHLI H ; () DATA ADDRESS ST DLS TABL: LADR H ; ST ; DATA TABLE ADDRESS SET LAI 5 ; LAMTL ; TABLE LOOK UP CALL SIOUT ; DATA OUT DDRS H ; DATA ADDRESS- JCP TABL LAI FH OP ; C/D =, CS = ;DATA END

25 CHAPTER EXAMPLES OF APPLICATIONS () DP display routine The DP display routine displays. between 5 and N as shown in Figure -. The use of this routine is not restricted to DP, but it can be applied to the change of each character. Flowchart DP C/D = CS = ; Command specification Chip Select specification WAIT LOAD DATA POINTER ; Data pointer setting SIOUT ; Command issue OR DATA MEMORY ; OR DATA MEMORY SIOUT ; Command issue C/D = CS = ; Command specification Chip Select non-selective RT Program list DP: LAI EH OP ; C/D =, CS = CALL WAIT LAI CH ; LOAD DATA POINTER ST ; (DP = C) LAI EH ; CALL SIOUT LAI ; ST ; OR DATA MEMORY LAI BH ; CALL SIOUT ; LAI FH OP ; C/D =, CS = RT ;DP END

26 CHAPTER EXAMPLES OF APPLICATIONS () Wait routine Because the BUSY signal outputted by µpd5 is not tested here, it is necessary to allow enough time until BUSY = is obtained before starting serial data transfer. Flowchart WAIT WAIT TIME ; Wait time setting WAIT TIME- ; Wait time loop NO TIME OVER YES RT Program list WAIT: LAI 5H ; WAIT TIME SET TAL LOOP: LAI FH ; WAIT TIME SET TAE DES ; WAIT JCP $- DLS ; WAIT JCP LOOP JHLT FH ; HL REG SET RT

27 CHAPTER EXAMPLES OF APPLICATIONS (5) Serial data transfer routine This routine transfers - bit serial data to the µpd5. Flowchart SIOUT (ST) DATA ; Data is set to the shift register DATA TARNSFER ; Shift operation start WAIT ; Wait routine RT Program list SIOUT: TAMSIO ; (ST) DATA SIO ; DATA TRANSFER CALL WAIT RT..5 How to set wait time The BUSY low level time (twlb) for the µpd5 is shown in the table below. MIN. MAX. Unit twlb (5)* /fc Where: fc is the clock frequency of the µpd5. -segment decoder is used. CS = /fc : (UNSYNCHRONIZED TRANSFER MODE) CS = ( + Alternating drive frequency)/fc : (SYNCHRONIZED TRANSFER MODE) In this case, alternating drive frequency = frame frequency x the number of time-shares signifies the case where BLINKING is used. When serial data is sent from CPU to µpd5, the BUSY signal need not be tested if the data is sent after Wait time of twlb MAX. The example below shows the setting of the actual Wait time in the above-mentioned Wait routine. Although µpd5 generates the clock through an internal oscillator (i. e. R connected to CL and CL), there is a drift in the clock frequency. (See Figure -.)

28 CHAPTER EXAMPLES OF APPLICATIONS Condition MIN. MAX. Unit Oscillation frequency R = kω ± 5% VDD = 5 V ± % 5 5 khz R = kω ± 5% VDD = V ± % 5 khz In considering the MAX. time of BUSY =, it is necessary to consider the case where the frequency is the lowest. Therefore the MAX. time of BUSY = under the conditions R = kω + 5 % VDD = 5 V + % BLINKING unused -segment decoder used UNSYNCHRONIZED TRANSFER mode is obtained according to the following expression: twlb (MAX.) /fc (MIN.) = /5 = 5 (µs) On the other hand, when Wait time is set without using a timer by the software of µpd5b, it is necessary to consider the case where the clock is the fastest. On the assumption that the system clock is generated by CR in µpd5b, the oscillation frequency has the following deviations. Condition MIN. MAX. Unit fcc R = kω ± % khz C = pf ± 5 % (VDD = 5 V ± %) It is therefore necessary to set the Wait routine with respect to fcc = khz. Because one machine cycle is [µs] at fc = khz in µpd5b, Wait of 5 (machine cycles) becomes necessary in order to pression indicates: 5 [µs] / [µs] =. = 5 (machine cycles) In order to set Wait time, the lowest clock of the µpd5 is combined with the fastest system clock of the CPU.

29 APPENDIX A BIAS OF LCD AND THE NUMBER OF TIME SHARING DRIVES Figure A-. shows the relationship between LCD bias and the number of time sharing drives. Figure A-. Relation between the Bias and the Number of Time Sharing Drives Bias Number of timeshares Static -time shares -time shares -time shares Static / / 5

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31 APPENDIX B TIME SHARING DRIVE AND THE MAXIMUM NUMBER OF DISPLAY ELEMENTS Shown below are each time sharing drive for the µpd5 and the maximum number of elements displayable in the static display. Number of time-sharing drives Static drive -time sharing drive -time sharing drive -time sharing drive Maximum number of displayable elements 9 Structure of LCD COM, S-S COM, COM, S-S COM-COM, S-S COM-COM, S-S Shown below is the maximum number of display digits for a - segment type or a -segment type. Number of time-sharing drives -segment LCD -segment LCD Static drive -time sharing drive -time sharing drive -time sharing drive digits + elements* digits + elements* digits + elements* digits + elements* digits + elements* digits + elements* digits + elements* digits + elements* Remarks: * These elements can be used as decimal points or indicators. As shown above, an increase in the number of time shares results in an increase in the number of controllable elements. Therefore, select the number of time shares according to what display is made in the application system and how many display elements are required. An insufficient number of display elements can be coped with by using several µpd5s. In the case of a static drive, there is no problem of cross-talk in a time sharing drive, and better display quality can be obtained.

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33 APPENDIX C DISPLAY TIMING AND SEGMENT DRIVE SIGNALS An LCD requires alternating drive by its nature. However, because an alternating drive loses balance temporarily the instant the display state changes due to a change in timing, the relation may be disturbed between a common drive signal and a segment drive signal. Therefore, a small direct portion may be imposed. (See Figure C-.) Figure C-. Segment Drive Signal Waveform Alternating drive Disturbance of alternating timing Segment drive signal CS (Data change timing) Although an LCD s life shortens when DC voltage is imposed for a long time, the life of LCD s being used today is not significantly affected by the instantaneous imbalance in an alternating drive as shown in Figure C-. Therefore, the LCD can be driven by the UNSYNCHRONIZED TRANSFER command. To synchronize a change in the display state with alternating timing, the SYNCHRONIZED TRANSFER command is used. After CS is raised and atter this command is executed, a change is made in the display data at the beginning of the next alternating timing. Figure C-. Segment Drive Signal Waveform Segment drive signal CS (Data change timing) 9

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35 APPENDIX D LCD POWER SOURCE CIRCUITS Figure D-(a), (b) and (c) show LCD power source circuits in Static, ½ bias and / bias. Figure. D- (a) Figure. D- (b) Figure. D- (c) Static / Bias / Bias VDD VDD VDD R C R C VLC VLC VLC R C R C VLC VLC VLC R C R C VLC VLC VLC Rx Rx Rx R = R R = R = R Remark: VLCD = VDD VLC VLCD : VLC = R + + : RX Example: In case of R = R = R = 5 kω,bias in. of -V drive and -time sharing drive becomes RX = kω Figure D-. LCD Equivalent Circuit µ PD5G VDD VLC CP VLC Analog Switch VLC Remark: CP = pattern capacity When represented in an equivalent circuit, LCD drive can be compared with the charging/discharging of CP as shown in Figure D-. Where drive voltage VLC to is made from an external split resistance, the charging/discharging waveform becomes dulled when this split resistance is large. Therefore, the effective value of voltage drops and contrast becomes poor.

36 APPENDIX D LCD POWER SOURCE CIRCUITS To better the contrast of LCD and improve visibility in such a case, connect a condenser, lower the impedance of the circuit and adjust the waveform.