Coupling Reverse Engineering and SAT to Tackle NP-Complete Arithmetic Circuitry Verification in O(# of gates)

Transcription

1 Coupling Reverse Engineering and SAT to Tackle NP-Complete Arithmetic Circuitry Verification in O(# of gates) Yi Diao*, Xing Wei*, Tak-Kei Lam** and Yu-Liang Wu* *Easy-Logic Technology Ltd., Hong Kong Science Park **Dept. of CSE, The Chinese University of Hong Kong Shatin, N.T., Hong Kong *{ydiao, xwei, Abstract There are situations (e.g. for reverse engineering or formal verification) circuit designers would need to extract complicated arithmetic circuitry deeply embedded inside a fully synthesized (or manually touched) million-gate flattened netlist without the knowing of module boundary and IO positions. Besides not knowing the IO and boundary, a formal verification task like comparing two netlists implementing (4A+3B) C and 4A C+3B C respectively is quite challenging for it is an NP-Complete Circuit- SAT problem too. To tackle this problem, we propose a novel Complementary Greedy Coupling (CGC) approach coupling reverse engineering and SAT techniques together for each of them only performs well at proving equality or inequality respectively. The scheme is quite powerful, being able to handle commonly implemented arithmetic modules (Ripple/CLA adders, MUX, various multipliers and their combinations) with runtime complexity nearly linear to the number of circuit gates. For an example, our scheme can verify two 32-bit multipliers (Wallace vs Modified- Booth) within 5 seconds (regardless of their equality or inequality), while running SAT alone might take centuries. We compared our tool Easy-LEC with the two on market commercial tools using the 182 open benchmarks posted for ICCAD CAD Contest Besides running at least 400 to 1400 times faster, our scheme also solves 32% to 45% more cases (93% vs 61% or 48%). I. Introduction In modern Very Large Scale Integration (VLSI) designs, it is often the case that over 60% of the overall design time is spent in the verification process. The (Reduced) Ordered Binary Decision Diagram (OBDD) [1] is known to be canonical for a Boolean function under a fixed variable ordering. However, OBDDs may be inappropriate to represent arithmetic logics, especially multipliers. The author in [1] proved that representing a multiplier in OBDD always requires exponential memory regardless of variable orderings. Binary Moment Diagrams (*BMDs) [2] and Multiplicative Power Hybrid Decision Diagrams (*PHDDs) [3] are efficient for wordlevel operations, but are less compact for representing Boolean logics. As both the CNF encoding [4,5] and SAT solving [6 8] techniques have been greatly improved in recent years, SAT are popularly adopted in today s equivalence checking tools. To check the equivalence between functions f and g by SAT solvers, a new function h = f g should be generated and converted into a set of CNF clauses. Now, the equivalence checking problem of f and g is reduced to a Circuit-SAT NP-complete problem of h such that if h is satisfiable then f and g are not equivalent. A satisfiable case is actually a much simpler situation, since a SAT solver can return any time it finds a satisfiable input pattern (usually pretty quick). However, the challenging situation is when f and g are equivalent and h is unsatisfiable. This is probably a case any SAT solver needs to check all possible input patterns which is exponential in nature. The reason is explained below. Although the decisions and learning procedures [9 11] have been shown to be quite efficient in the known SAT solvers [6 8]; however, it seems most modern SAT solvers highly rely on the successful locating of the internal equivalent points of the compared logics. It can be observed empirically that even for quite small circuits with very few internal equivalent points found, the solving time may grow exponentially in the worst case. For example, the comparison between multipliers designed in different styles such as non-booth Wallace versus Booth is one of such worst cases. Figure 1 [12] shows an example of comparing two multipliers by SAT solvers MiniSAT and Satz. Both solvers require exponential time in comparing these multipliers regardless of the parameter tuning efforts. Similarly, most known commercial tools might abort when verifying larger multiplier cases. Several approaches have been proposed in [13 22], which try to overcome the inability of SAT solvers for arithmetic circuitry verification. SMT solver [13] integrate different well-defined theories (Boolean logic, bit vectors, integer arithmetic, etc.) into a SAT decision procedure. However, it still models the problem as a decision

2 (a) Results for Satz 2.15 (b) Results for Minisat 2.0 with preprocessing procedure and is not efficient enough when verifying arithmetic logics. Some algebra based algorithms [14, 22] are also proposed. In [22] it can extract the function expression of an arithmetic macro by computing input signature from the known output signature without concerning its design style. However, these algorithms require prior knowledge of the input and output boundary of the macro first. This seems impractical in real industry problems where arithmetic macros are likely hidden inside flatten netlists. Hence, we propose to complement this weakness of circuit-sat by applying a so-called Complementary Greedy Coupling (CGC) methodology, which was sort of extended from the notion of Orthogonal Greedy Coupling proposed in [23]. Although proving the equality between f and g is sometimes a harder job for a SAT solver, it might not be a harder job for applying some other technique like a structural-analysis based reverse engineering. This is because in modern practical circuits, the optimal designs of arithmetic circuitry operators have been carefully studied and the finally adopted designs are quite limited in styles. As a matter of fact, different designs of the same arithmetic operator (e.g. multiplier) do still share certain common structural property ( structural DNA ), which should be unique and differentiable from other arithmetic operators. Making a proper usage of this expertise knowledge can help finding the exact IO boundary and proving the equality fast (near linear). However, this knowledge is not of much use in proving inequality for there could still exit unlimited possibility that certain new unknown design is invented and used later). We then leave the inequality proof to SAT, which can usually return fast. Applying this coupling, we can prevent the SAT solvers to be trapped into some unsatisfiable proof process and run forever. We call this a CGC approach for equivalence checking. We try to use the example of a multiplier equivalence checking to illustrate this CGC notion in Figure 2. Given that f and g represent two multipliers respectively. As shown in Figure 2(a), SAT solver can finish in polynomial time in the cases when f g, while may take an exponential runtime when f = g. However, if applying reverse engineering for this problem, contrarily, it is highly likely to solve the cases f = g in polynomial time, as shown in Figure 2(b). It is then achievable that if we use SAT solver to solve the cases f g, while let reverse engineering handle cases f = g, we can then solve the problem in a complementary way efficiently for all cases. Fig. 1. Relationship between the multiplier size, and the exponential runtime and number of decisions required by a SAT solver to compare multipliers [12] (a) SAT solver (b) Reverse Engineering (c) SAT solver + Reverse Engineering Fig. 2. Coupling SAT solver and Reverse Engineering (RE) After extracting the operators, we still need to extract arithmetic formulae from totally flattened netlists for a formula-level verification. We briefly illustrate our scheme by an example of verifying two flattened netlists f and g. They contain a sub-circuit implementing (4A + 3B) C and 4A C + 3B C respectively, where A, B, C are vector words, and 4A means 4 times A. In our scheme, we would (1) apply reverse engineering and logic synthesis techniques [24, 25] to extract all the arithmetic operator macros and replace them by equivalent operator symbols (e.g. +, or ); (2) evaluate the equivalence of the above two formulae with normalized macro symbols. This can be done by a few ways. We illustrate a method by *BMD [2] here (Fig 5); (3) normalize the equivalent formulae by replacing them with a same corresponding netlist pattern in both netlists f and g; (4) generate a CNF encoding representing h = f g with the formulae normalized if f and g are equivalent; (5) submit the CNF to a SAT solver. In step (3), as the equivalent arithmetic formula parts are already normalized to the same pattern in both netlists, the h encoding would be extremely trivial for any SAT solver to avoid being trapped into an exponential process and to solve in just a few seconds. The major challenging part is at step (1). Our algorithm is able to extract multipliers designed by the known

3 different ways (Array/Adder-tree multipliers, Carry Save Adders (CSAs), Wallace, modified or regular Booth) composed of one-bit adders (half and full adders) under an O(n 2 ) complexity bound, where n is the multiplier s bitwidth and the run time is almost linear with the number of gates used for the multipliers. Other common arithmetic macros (multiplexers, adders, large XOR trees) with various design variations (e.g. CLA adder, Ripple adder... ) can also be efficiently extracted from the netlists by our algorithm. In a pre-processed CNF form in step (5), a large number of internal equivalent points can be easily located, the SAT solver can then run extremely fast. E.g. it takes only five seconds on average to pre-process and solve for comparing a Wallace against a Booth multiplier, where each of them is of 32-bit. We attended the ICCAD CAD Contest 2014 [26] and won the first place. Our latest results is much better than that of the second place. We then ran our tool on the 182 open benchmarks posted by contest and compared it with two known commercial Logic Equivalence Checking (LEC) tools. With a time limit of 3 seconds set for each case in our tool, our algorithm can solve 93% circuits, with an average run time of 2 seconds per solved case. Besides solving more cases (93% vs 61% by X or 48% by Y), our tool runs at least 381 times faster than the tool X and 1358 times faster than tool Y. II. Difficulties in Comparing Arithmetic Blocks A macro is defined to be a block of logic which is a building component in Integrated Circuits (ICs) like adders, multipliers, multiplexers (MUX) or even a formula like (A + B) C. Macros, especially multipliers, usually bring great challenge to modern verification engines. In [18], the authors indicated that equivalence checkers could perform extremely well if the two designs contained a high degree of structural similarity. On the other hand, if no internal equivalences exist, modern equivalence checkers fail and verification can become impossible even for relatively small circuits. Figure 3 shows two functionally equivalent 4 4 multipliers that are implemented in different styles. The partial product of a Booth multiplier is illustrated in Equation 1, while the non-booth one in Equation 2 (each of a i and b j is the input bit of a multiplier operand). A direct equivalence checking by the current SAT solvers will likely fail to complete within a practical time limit. pp i,j =(a i a i 1 )(b j a i+1 )+ (a i a i 1 )(a i+1 a i )(b j 1 a i+1 ) (1) pp i,j = a i b j (2) Figure 4 illustrates an example that two differently implemented formula structures can also be equivalent. By analysing the experimental results, we have concluded the following obervations. (a) 4 4 Booth multiplier (b) 4 4 Non-Booth Wallace tree multiplier Fig. 3. Equivalent multipliers in different structures (a) (A + B) C (b) A C + B C Fig. 4. Equivalent macros formed by adders and multipliers Observation 1. The complexity of verifying an unsatisfiable n-input XOR-tree (n-input xor primitive) is O(2 n ) if no internal equivalence points can be found. Observation 2. It requires exponential time for a SAT solver to verify the equivalence of two m n multipliers implemented in Booth and non-booth Wallace trees respectively. This is empirically reflected in Figure 1 [12]. III. Formal Verification by Macro Level Function Checking It is observed that SAT solvers fail to verify arithmetic macros implemented in different structural styles effectively for there is not much internal equivalence among the CNF encoding due to structural difference. To address this problem, we have the following conjecture. Conjecture 1. Two equivalent functions represented in an identical implementation can be solved by SAT solver in polynomial time. The reasoning is that a SAT solver can traverse both functions and generate CNF clauses in topological order. Since the two functions are exactly in the same implementation form, the SAT solver can merge every pair CNF clauses which have the same inputs and sub functions. The result can thus be given by only one traversal in polynomial time.

4 We have identified the necessary steps to eliminate structural difference and thus to facilitate equivalence checking. They are: 1. Operator mapping, 2. Operand mapping, and 3. Formula equivalence checking and macro normalization. Macro mapping is to identify the function of a sub-circuit such as A B + C. An identified macro will undergo macro normalization in which it is re-implemented following a standard synthesis procedure. As a result, the same functions will always be structurally and logically equivalent despite their different formula representations. In order to accomplish macro normalization, the bit-vector variables in different formulae have to be matched. Finally, the re-synthesized netlists are translated into CNF claused and SAT engine is invoked to solve it. The whole algorithm flow is shown in figure 5. Fig. 5. Algorithm flow Before going into the details of our equivalence checking flow, an example is depicted in Figure 6 to introduce the concept. Suppose the two netlists, netlist1 and netlists2, are to be compared. They contain a non-booth multiplier and a Booth multiplier respectively. Firstly, the multipliers inside the netlists are identified. They are then restructured in the non-booth style and their formulae are rewritten in the standard form. The structural difference between the two netlists are then reduced to minimal; namely, their internal equivalence are maximized to speed up equivalence check. Lastly, the resynthesized netlists can be transformed into CNF clauses to be solved by a SAT solver. The major difficulties of our equivalence checking flow are: (1) to identify the boundaries and functions of the macros, (2) macro normalization, which needs to do logic restructuring and formula rewriting. We present our solutions for these problems in the following. A. Operator Macro Mapping We extend [24] and improve their idea to map general arithmetic macros composed of adders and multipliers. (a) before normalization Fig. 6. Multiplier normalization for SAT solvers (b) after normalization Although multipliers can be implemented in various structures, the most common implementations in practice are non-booth Wallace tree and Booth multipliers. Due to page limit, in this paper, we mainly describe the multiplier extraction for these two design styles. Both non-booth and Booth multipliers can be regarded as a structure of 1-bit half or full adders. This implies that an 1-bit half or full adder can be considered an atomic unit of the implementation, and the whole macro can be partitioned into numerous 1-bit adders. Every input signal of an 1-bit adder in a multiplier implementation is either a partial product or an output (carry or sum) of another 1-bit adder. The process to map adders, multipliers and their combinations can therefore be done and constructed from a basic structure: identified and connected 1-bit adders. Based on the above analysis, we know that the first step to map 1-bit adder based arithmetic macros is to traverse the whole netlist to identify all 1-bit half adders and 1-bit full adders. Then the 1-bit adders are connected to form 1-bit adder trees by the sum signals. Each 1-bit adder-tree represents an addition of the signals having the same bitweight. By the carry signals, these 1-bit adder-trees are then connected to form a 1-bit adder-forest to represent a candidate arithmetic macro. Finally, the weights of the macro output bits and input bits are determined according to the boundary of the forest. The output boundary of the forest is formed by the output of every tree. The input boundary of the forest is formed by the partial products of multipliers or the input bits of adders. The unique structural of the forest which include the number of trees, the size of each tree, the way that the trees are connected, and the types of signals lying on the boundaries, can be used to characterize a macro. We have successfully compiled the unique characteristics of the standard implementations of each of the common arithmetic macros. Hence, the type of the candidate arithmetic macro can be figured out instantly once the forest has been constructed. B. Operand Mapping In the process of identifying a macro, the corresponding formula is also identified at the same time. Suppose we are comparing two macros whose formulae are (A + B)

5 C and E (F + G) respectively. The first problem we have to solve is to determine the relationships between the variables in the formulae. We use the following heuristic to decide this operand mapping. We first encode all primary input. Then the mapping signature value of a bit is calculated by the encode value of the primary inputs driving the bit. For an adder, the operand bits of all weights should be mapped according to their sorted mapping signature values, while for a multiplier, only the operands need to be mapped in a similar way. For a macro with m operands of n-bit words, the complexity of an adder mapping is O(nm log m) and O(m log m) for a multiplier mapping. As m is usually quite small, the cost is nearly a constant or close to O(n). C. Formula Equivalence Checking and Normalization As discussed in the previous section, the function of a macro can be easily known after its operator and operand mappings. Then approaches like *BMD [2] can be used to do formula verification for although there can be unlimited number of ways to express a formula, every formula has a unique *BMD form. If there are no more logics left outside the macros, the equivalence checking process is done. Otherwise, the structural difference between functionally equivalent macros can still be reduced by repeating the above macro normalization. To perform an efficient macro normalization, after knowing the function formulae of macros, we still better pre-define a standard synthesis procedure and a standard formula expression for each common macro type and to transform each recognized macro to its predefined canonical form. For example, a non-booth style can be chosen as the standard style to synthesize multipliers, as shown in Figure 6. Then the CNF encoding of the new netlists can be solved by SAT solvers quickly. Besides solving the regular arithmetic formula cases, our scheme can also handle other data-path equivalent patterns such as MUX(s, (A B) : (C D))= MUX(s, (A : C)) MUX(s, (B : D)) as shown in Figure 7. Many other undescribed macros can also be treated similarly. D. Complexity Analysis for Mapping Multipliers From the results discussed in Section A, we have the following lemmas for mapping multipliers. Due to page limit, in this paper, we would skip some proofs and complexity analysis. Lemma 1. The complexity of constructing the addertrees and forest is linear with respect to the circuit size. Consequently, the partial products for each bit-weight can be identified in linear time. (a) Two multipliers and one multiplexer (b) One multiplier and two multiplexers Fig. 7. Equivalent macros formed by multiplexers and multipliers Lemma 2. The complexity of determining the input boundary of an n-bit multiplier (Booth or non-booth) is O(n 2 ) and is O(the circuit size). Proof. The number of partial products of an n-bit non- Booth multiplier is n n, and that of an n-bit Booth multiplier is n 2 (n + 1). After constructing the adder-trees and forest, the partial products for each bit-weight can be obtained. The input boundary of the multiplier can then be determined by visiting the partial products in the order of their corresponding bit-weights (details skipped for page limit). Therefore, the complexity of input boundary discovery is linear with the number of partial products, or is O(n 2 ) with respect to the multiplier s bit-width. Lemma 3. The complexity of mapping 1-bit adder based multipliers (array, non-booth Wallace or Booth) using our algorithm grows linearly with the circuit size. Because the arithmetic formulae used in practical circuits are relatively simple, the complexity of formula manipulation and operand mapping can be considered as a constant. Then, the complexity of macro normalization is linear with the circuit size. The overall complexity of our flow is therefore linear. This result is also justified by our experiments. IV. Experimental Results The experiments were performed on a Linux machine (Ubuntu with Linux kernel 3.2) powered by a 2.33GHz CPU and 2G memory. Our tool is named Easy- LEC. The executable file can be downloaded from [27]. A. Benchmark Information The set of open benchmarks released by Cadence s logic verification team for the 2014 CAD Contest at ICCAD [26] was adopted to evaluate our approach. Each of these benchmarks is a gate-level single-output combinational circuit. The benchmarks are divided into 24 test case suites.

6 Each suite contains three sample circuits, and ten test circuits synthesized using the same design styles. All circuits in the same suite implement similar arithmetic functions which only differ in their operands bit-widths. TABLE I Benchmark information [26] Case #primitives Function Style* Width ut a c + b c, NB 6 8 (a + b) c ut a b B ut a b B ut s(a b) s(c d), NB (sa sc) (sb sd) ut (signed)a b B, NB 9 24 ut (signed)a b B, NB ut a b B, NB ut a b B, NB ut a b B, NB ut (signed)a b B, NB a b c d ut a b, a b + c B, NB 9 28 a b + c d + e f ut (signed)a b B, NB ut fail to find any arithmetic macro ut a b B, NB hid a c + b c, B (a + b) c hid a b B, NB hid a + b y + z NB 4 13 hid (signed)a b B, NB 8 24 hid (signed)a b B, NB 6 11 hid a b B, NB hid a b B, NB hid a b + c, B, NB a b c d, a b e f hid a b B, NB hid fail to find any arithmetic macro *B/NB means for Booth/non-Booth multiplier Table I lists the characteristics of the benchmarks. Besides multiplication, some more complicated arithmetic functions also exist in the benchmarks. B. Comparison with The Contestants at ICCAD Contest 2014 We attended the ICCAD 2014 contest, which is about simultaneous CNF encoder optimization with SAT solver setting selection, and won the first place. Moreover, after continuous improvement, our latest results (25th Oct version) are even better. 12 case suites (ut2, ut32, hid1 hid10) are chosen by the organizer to evaluate the results. Figure 8 shows the comparison of our latest results with that of all other contestants. In the figure, cost represents the sum of cost (weighted CNF encoding time plus SAT solving time) of total 120 circuits (10 test circuits each from 12 cases). The number of solved circuits of each team is also indicated by the red curve. It can be seen that our cost is only 1/8 of the 2 nd team s cost and we can solve more problems (116 versus 57 in number or 97% versus 49%). Fig. 8. Contest results C. Comparison with Commercial Tools We also compared our tool with two famous commercial logic equivalence checking tools X (the latest version) and Y (the 2005 version). We did the comparison on the 14 open suits (ut1 ut41). For each suit, all the 13 circuits including the three sample circuits and ten test circuits are tested. For each circuit, each tool will terminate either after solving the SAT problem, or the time limit is reached. The two commercial tools would usually abort after running several thousands of seconds. In our approach, we use ABC to generate the CNF file after running our macro level functional checking algorithm. Glucose is used to solve the CNF file with default parameter setting. The results are shown in Table II. Columns #solved list the number of solved circuits. For all test suites except ut36 whose arithmetic logics failed to be extracted, our algorithm can solve most of the test circuits within seconds. On the other hand, it seems both commercial tools rely on some traditional logic checking technologies so that only cases with primitives gates but not complex arithmetic logics can be totally solved (ut1, ut2, ut5, and ut7 for X, ut1, ut5, ut7, and ut8 for Y). Columns avg time indicate the average runtime of each circuit regardless of whether it is solved or not. On these 182 open cases posted by Cadence for the Contest, our algorithm can solve 93% circuits (under our SAT time limit of 3 seconds per case), which is much better than the commercial tools (61% by X and 48% by Y) under a SAT time limit of 5000 seconds per case. Under this setup, our algorithm is at least 381 times faster than the commercial tool X and 1358 times faster than Y. Be noted that, as we can only extract the SAT run time from the commercial tools X (provided by company X), we are comparing our runtime of whole flow to the SAT time only of X. V. Conclusion Although modern SAT solvers, such as MiniSat, Glucose, Lingeling, are very efficient for formal verification

7 TABLE II Comparison with commercial tools Easy-LEC Commercial tool X Commercial tool Y Case #primitives #circuits #solved avg time(s)* #solved avg time(s)** #solved avg time(s)*** ut ut ut ut ut ut ut ut ut ut ut ut ut ut total avg ratio 1 93% 1 61% 381.3X 48% X * avg time is runtime of whole flow (arithmetic logic normalization, CNF encoding and SAT solving time) ** avg time is SAT solving time only (provided by company X) ***avg time is runtime of whole flow results of 25th Oct version on most random logics, these SAT solvers are likely to run exponentially for certain circuit structures regardless of parameter tuning by any methods (e.g. machine learning). Unfortunately, those hard to tackle structures are actually quite common in today s data-path circuits (e.g. multipliers or additions like A1+A2+...+An that contain certain XOR tree topology). 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8 TABLE III Detailed results of benchmark cases in 2014 CAD contest at ICCAD [26] case time* case time case time case time case time ut1/sample ut20/sample1 0.4 ut41/sample hid1/test hid6/test ut1/sample ut20/sample2 0.5 ut41/sample hid1/test hid6/test2 0.2 ut1/sample ut20/sample3 abort ut41/sample hid1/test hid6/test3 0.4 ut1/test ut20/test ut41/test hid1/test hid6/test ut1/test ut20/test10 abort ut41/test hid1/test hid6/test ut1/test ut20/test ut41/test hid1/test hid6/test ut1/test ut20/test ut41/test3 0.7 hid1/test hid6/test ut1/test ut20/test4 2.5 ut41/test hid1/test hid6/test ut1/test ut20/test ut41/test hid1/test hid6/test ut1/test ut20/test ut41/test hid1/test hid6/test ut1/test ut20/test ut41/test hid2/test hid7/test1 0.3 ut1/test ut20/test ut41/test8 1.4 hid2/test hid7/test ut1/test ut20/test ut41/test hid2/test hid7/test ut13/sample ut26/sample ut5/sample hid2/test hid7/test ut13/sample ut26/sample ut5/sample hid2/test hid7/test ut13/sample ut26/sample ut5/sample hid2/test6 0.3 hid7/test ut13/test ut26/test ut5/test hid2/test hid7/test ut13/test ut26/test ut5/test hid2/test hid7/test ut13/test ut26/test ut5/test hid2/test hid7/test ut13/test ut26/test ut5/test hid2/test hid7/test ut13/test ut26/test ut5/test hid3/test1 0.5 hid8/test ut13/test5 0.3 ut26/test ut5/test hid3/test hid8/test2 0.6 ut13/test6 0.4 ut26/test ut5/test hid3/test hid8/test ut13/test ut26/test ut5/test7 0.5 hid3/test hid8/test ut13/test ut26/test ut5/test hid3/test hid8/test ut13/test ut26/test ut5/test hid3/test hid8/test ut14/sample ut3/sample ut7/sample hid3/test hid8/test7 abort ut14/sample ut3/sample ut7/sample hid3/test hid8/test8 abort ut14/sample ut3/sample ut7/sample hid3/test hid8/test ut14/test ut3/test ut7/test hid3/test hid8/test ut14/test ut3/test ut7/test hid4/test hid9/test ut14/test ut3/test ut7/test hid4/test hid9/test ut14/test ut3/test ut7/test hid4/test3 0.8 hid9/test ut14/test ut3/test ut7/test hid4/test hid9/test4 0.6 ut14/test ut3/test ut7/test5 0.5 hid4/test hid9/test ut14/test ut3/test ut7/test hid4/test hid9/test ut14/test ut3/test ut7/test hid4/test hid9/test ut14/test8 0.8 ut3/test ut7/test hid4/test hid9/test ut14/test ut3/test ut7/test hid4/test hid9/test ut15/sample ut32/sample ut8/sample1 1.5 hid4/test hid9/test ut15/sample ut32/sample ut8/sample hid5/test hid10/test ut15/sample ut32/sample ut8/sample hid5/test hid10/test ut15/test ut32/test ut8/test hid5/test hid10/test ut15/test ut32/test ut8/test hid5/test hid10/test ut15/test ut32/test ut8/test hid5/test hid10/test ut15/test ut32/test ut8/test hid5/test hid10/test ut15/test ut32/test ut8/test hid5/test7 0.7 hid10/test ut15/test ut32/test ut8/test hid5/test hid10/test ut15/test ut32/test ut8/test6 1 hid5/test hid10/test9 abort ut15/test ut32/test7 0.9 ut8/test hid5/test hid10/test10 abort ut15/test ut32/test ut8/test ut15/test ut32/test ut8/test ut2/sample ut36/sample ut2/sample ut36/sample2 abort ut2/sample ut36/sample3 abort ut2/test ut36/test1 abort ut2/test ut36/test10 abort ut2/test ut36/test2 abort ut2/test ut36/test3 abort ut2/test4 0.9 ut36/test4 abort ut2/test ut36/test ut2/test ut36/test6 2.9 ut2/test ut36/test7 abort ut2/test ut36/test8 abort ut2/test ut36/test9 abort time*: time (in seconds) used to verify cases by Easy-LEC (version at 2014/10), report abort when failed All cases can be downloaded at contest.ee.ncu.edu.tw/cad-contest-at-iccad2014/problem a/default.html