Design of Delay Efficient Carry Save Adder

Transcription

1 Design of Delay Efficient Carry Save Adder K. Deepthi Assistant Professor,M.Tech., Department of ECE MIC College of technology Vijayawada, India M.Jayasree (PG scholar) Department of ECE MIC College of technology Vijayawada, India Abstract The logic operations used in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to have the data dependence and redundant logic operations. These redundant logic operations present in the conventional CSLA are eliminated and a new logic formulation for CSLA is used. An efficient CSLA is designed using optimized logic units. But the existing CSLA design is used to add only two binary numbers. Since, complexity of operations are increasing day by day it is inefficient to add more than 2 binary numbers. To add more than 2 binary numbers carry s are used. In the existing Carry s delay is more. So in this paper a carry which is used to add more than two binary numbers efficiently with less delay factor is designed using an efficient adder which uses optimized logics. Keywords Carry select look ahead adder(csla); Carry (csa); full adder; half sum generation unit; carry generation unit; full sum generation unit Introduction VLSI systems with low power, area, efficiency and high performance are increasingly used in portable mobile devices, wireless receivers and biomedical instrumentation. Addition is an obligatory operation that is crucial to processing the fundamental arithmetic operations. Adders are commonly found in the critical path of many building blocks of microprocessors and signal processing chips. Adders are very important not only for addition, but also for subtraction, multiplication, and division. Addition is one of the basic arithmetic operations. A fast and accurate operation of a digital system is greatly influenced by the performance of the adders. The most important for measuring the quality of adder designs in the past have great propagation delay, and consumes more area. In array processing and in multiplication and division, multi operand addition is often encountered. It is used extensively in many VLSI design paradigms and is by far the most frequently used operation in many general purpose systems and in application specific processors. It is dubbed as the heart of any microprocessor, DSP architecture, and data processing systems. A ripple carry adder is a simple design but carry propagation delay is of main concern. Carry Look Ahead adder and carry select adders are developed to reduce the delay. A conventional carry select adder uses dual RCA-RCA which generates pair of sum and carry words. But it is not efficient and redundancy problem occurs. A carry select adder is designed to overcome the dual RCA by using RCA with add-one circuit. But in this adder data dependence problem occurs. To overcome this problem an efficient Carry Select adder is designed by using an optimized logic formulation. This carry select adder is area, delay and power efficient. However this adder is used to add two binary numbers. As the complexity increases day by day there is a great need to add more than two binary numbers at a time. The proposed adder uses an architecture which is used to add more than two binary numbers at a time with less delay. The design of a high-speed multioperand adder called Carry-Save Adder (CSA) and it is very much useful in present technologies. METHODOLOGY i. Carry Save Adder Carry is very fast adder that does not propagate carry bits. The design of a high-speed multi operand adder called Carry-Save Adder (CSA) with efficient adder at last level designed in this paper by including delay efficiency factor. Available online: P a g e 993

2 The name carry save arises from the fact that we save the carry-out word instead of using it immediately to calculate a final sum. The main idea is that the carry has a higher power of 2 and thus is routed to the next column. Carry is used to add several operands together. Thus, it can prevent time-consuming carry propagation and speed up computation. It has various levels of rows of full adders. Full adder is used to reduce three inputs to 2 inputs. For an n bit adder the number of full adders at each level is n. If there are k numbers then there are k- 2 number of levels of full adders. In the carry-save addition, let the carry propagate only in the last step, while in all the other steps sum and a sequence of carries are generated separately. Thus, the basic carry (CSA) accepts three n-bit operands and gives two n-bit results. They are n- bit sum, and an n-bit carry. A second CSA accepts these 2 bit sequences and another input operand, and generates a new sum and carry. A Carry Save Adder can be able to reduce the number of operands to be added from three to two, without any carry propagation. The adder designed in this paper can be widely used for multipliers, dividers, address generation, ALU units and many other applications. ii. Architecture: The following figure gives the architecture of an 8- bit carry operand, and generates a new sum and carry. A CSA thus reduces the number of operands to be added from three to two, without any carry propagation. The sum and carry are recombined in normal addition to give correct result. The power of this technique is that any number of binary numbers can be added together in this manner. It is only the final recombination of the final carry and sum that involves a carry propagating addition. In the fastest method to add a large set of n- bit inputs using CSAs involves organizing the CSAs into a 3:2 tree structure. In the last level of carry we can use any adders like ripple carry adder, carry select adder, carry skip adder. But in the proposed design we are using an efficient adder which does not have any data dependences and redundant operations. iii Full adder Full adder is the basic unit of carry save adder. This adder is used to reduce the number of operands in the carry. This adder considers 3 inputs and results 2 outputs. Thus this adder is very crucial part in carry. Full adder module: A full adder is used to add more than 2 binary numbers. A one-bit full adder adds three one-bit numbers, written as X, Y, and Cin. X and Y are the operands, and Cin is a bit carried in. The circuit results a two-bit output carry and sum usually represented by the signals Cout and S. Full-adders can be cascaded to build a multi-bit binary adder. Sum=X xor Y xor Cin Cout =((X xor Y) and Cin) or (X and Y) Fig 1: 8 bit carry architecture In the carry-save addition method, the carry propagate in the last level only, while in all the other levels we generate a sum and a sequence of carries separately. Thus, the basic carry (CSA) considers three n-bit operands and generates two n-bit results, an n-bit sum, and an n-bit carry. A second CSA accept these 2 bit sequences and another input The block diagram of a full adder is shown in the following figure: X Y Cin FULL ADDER Fig 2: Block diagram of a full adder sum carry Available online: P a g e 994

3 iv. Efficient Adder design: The design flow of an efficient adder is shown in the following figure: b) Carry Generation unit : In this unit we generates the carries for all the bits by assuming carry input as 0 The logic expression for this unit is as follows: C01(i)=C01(i-1).S0(i)+C0(i) The logical implementation of this unit is as follows: Fig 3:Design flow of an efficient adder An efficient adder accepts sums and carries from previous alevels of full adders and generates final sum and carry outputs The design flow of efficient adder contains the following blocks: a)half sum generation unit: The half sum generation unit generates sum and carry irrespective of previous bits. b)carry generation unit: The carry generation unit generates carries by taking sum and carries from half sum generation unit. c)full sum generation unit: In the full sum generation unit final sums and carry output are generated. iv Blocks of an efficient adder: a) Half sum generation unit(hsg unit): This unit takes two n bit binary numbers and generates sum and carry for each bit of binary numbers. The logic operation involved in this unit is as follows S0(i)=A(i) xor B(i) C0(i)=A(i).B(i) The block diagram of HSG unit is as follows: c) Full sum generation unit: Fig 5: Carry generation unit The full sum generation unit generates the sum bits for all the input bits. It takes the input sums from half sum generation unit and carry bits from carry select unit and performs the full sum operation The logic expressions used in this unit are: S(i)=So(0) xor C(i-1) The architecture for this unit is as follows: Fig 6: full sum generation unit III COMPARISION RESULTS The design developed in this paper provides less delay compared to various other adders. This can be given in the following table System Carry Select Look Ahead adder Number of Number of Delay bits operands 8 bit 2 12ns 16 bit 2 18ns Fig 4: Half sum generation unit Designed carry 8 bit ns 16 bit ns Available online: P a g e 995

4 Table1. Comparison of CSLA and CSA adders From the table we can prove that the designed carry is used to add more than 2 binary operands with less delay. SIMULATION RESULTS: IV Experimental results 8 bit output: The following figure gives result of the sum and carry of 4 8-bit numbers. Fig 9: Synthesis report of 8 bit proposed system 16 bit synthesis report: The following figure gives the delay of designed 8-bit carry Fig 7: 8 bit output of multi operand addition 16 bit output: The following figure gives result of the sum and carry of 4 8-bit numbers. Fig 10: Synthesis report of 16 bit proposed system V. CONCLUSION Fig 8: 16 bit output of multi operand addition Synthesis reports 8 bit synthesis report: The following figure gives the delay of designed 8-bit carry We have analyzed that the logic operations involved in the conventional and BEC-based CSLAs to study the data dependence and to identify redundant logic operations. The ripple carry adder and carry select adders are used only to add 2 binary numbers.if we need to add more than 2 binary numbers they are inefficient and carry is efficient. At present carry s in the last level uses ripple carry adder or carry select adders or carry skip adders. But they results in great propagation delay. To reduce this we designed an efficient adder which has less data dependence and redundant logic operations in the last level. This reduces the overall delay of carry save adders. References [1] K. K. Parhi, VLSI Digital Signal Processing. New York, NY, USA:Wiley, [2] A. P. Chandrakasan, N. Verma, and D. C. Daly, Ultralow-power electronics for Available online: P a g e 996

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