Analysis of Performance and Designing of Bi-Quad Filter using Hybrid Signed digit Number System

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1 International Journal of Electronics and Computer Science Engineering 173 Available Online at ISSN: Analysis of Performance and Designing of Bi-Quad Filter using Hybrid Signed digit Number System Sugandha Agarwal 1, Krishna Raj 2 1 Electronics and Communication, Amity University, Viraj Khand -5 Gomti Nagar Lucknow , Uttar Pradesh, India 2 Electronics and communication department, HBTI, nawabganj Kanpur , Uttar Pradesh, India 1 sugandhaa7@gmail.com, 2 kraj_biet@yahoo.com Abstract: Speed of digital arithmetic processor depends mainly on the speed of adders. This paper provides a technique so that we can increase the speed of addition. Hybrid signed digit number representation perform addition in such a way that the carry propagation chain is limited to single digit position and hence are used to speed up arithmetic operation. Also hybrid signed digit reduces the critical path delay by parallelizing. Hybrid signed digit can be appropriate to use, when output is redundant representation. Keywords: Redundant arithmetic, critical path delay, Hybrid signed digit adder, Ripple carry adder, VHDL Simulation. 1-INTRODUCTION Multiply accumulate operation is the main block of the digital processor, that mainly depends upon the processing of adder and multiplier. In order to get the efficient result fast addition and multiplication procedures are adopted. As we know multiplication can be perform using multiple addition, therefore speed of any arithmetic process depends upon the speed of adders. Ripple carry adder form the basis of fast adder, which uses two s complement arithmetic. In Fairchild s application note we can find the practical implementation of adders [1]. Asynchronous adders were studied by Gilchrist [2]. Asynchronous means, it closes unnecessary waiting between adjacent arithmetic operations by unlocked control logic. Major disadvantages of asynchronous adder are its complexity of control logic. Various synchronous adders like Carry propagation length adder was studied by Reitwiesner [3] and Briley [4]. Conditional sum adder was proposed by Sklansky [5] and further advanced by Kruy [6]. Carry select adder was introduced by Bedrij [7]. Many researchers including Alexander [8], Avizienis [9], Ferrai [10], Lehman [11, 12], Mac sorley [13], Sklansky and Lehman and Weller [14] has studied carry propagation speed up techniques and their possible implementation. The researchers concluded that carry look adders is the result of parallel carry generation. Bartee and Chapman s [15] work on general purpose accumulator design which finds its great requirement in computers. Majerski [16] analyzed the carry skip distribution in adder design. Shedletsky [17], add on ideas on the end round carry adder design. Whereas Wino grad [18] and Spira [19] has studied the theoretical aspects of time limit, required for the machine operation. In, this paper I have design Bi-quad recursive digital filter using hybrid signed digit algorithm. The remaining portion of the paper are arranged as follows in section 2 we have describe the algorithm of HSD adder, section 3 describes the designing of Bi-quad digital filter, results are concluded in section HYBRID SIGNED DIGIT ADDER ALGORITHMS 2.1. Hybrid signed digit number Signed digit number systems are used to speed up arithmetic operation. One important property of signed digit number system is that in this each digit can assume any one of the three values {-1, 0, 1} [20]. In order, to reduce the carry propagation chain hybrid signed digit number representation was introduced, where we can set the maximum carry propagation length to any desired value between one and full word length. These

2 IJECSE,Volume1,Number 2 Sugandha Agarwal and Krishna Raj provide designer an optimized tradeoff between area and carry propagation time. In hybrid signed digit, we let some digit to be signed and some unsigned [21, 22]. Like, we can let every alternate or every second digit to be signed and all the remaining ones are unsigned. It is shown that the maximum length of carry propagation chain equals to (d+1), where d is the longest distance between the neighboring signed digit Equation of delay [23] When d=1 i.e. alternate signed digit 2.3. Unsigned hybrid signed digit adder Inputs to the cell are the bits ai-1, bi-1 and the incoming carry ci-2. The outputs are the carry out ci-1 and the final sum ei-1.carry ci-2 to this cell is broken in two parts, and wi-1 according to the rule C i-1 =V i-1-w i-1-1. (1) (2) Figure 1 VHDL simulation of HSD unsigned position adder cell

3 Analysis of Performance and Designing of Bi-Quad Filter using Hybrid Signed digit Number System 175 Figure 2 Waveform of HSD unsigned position adder cell 2.4. Signed hybrid signed digit adder The inputs to this cell are the signed digits xi, yi and the carry signals w i-1 and v i-1. A signed digit x is encoded in two bits x s, x a, with,-1, 0 and 1 encoded by 11, 00, and 01, respectively. The outputs of the cell are the carry signals v i, w i and the bits that represent the output signed digit (zi s, zi a ). (3) Figure 3 VHDL simulation of HSD signed position adder cell

4 IJECSE,Volume1,Number 2 Sugandha Agarwal and Krishna Raj Figure 4 VHDL simulation of HSD signed position adder cell 3. DESCRIBING THE DESIGNING OF Bi-QUAD DIGITAL FILTER 3.1. Bi-Quad Filter The bi-quad filter core is an implementation of an infinite impulse response (IIR) filter. It is a second order recursive linear filter, with two poles and two zeros. Bi-quad is an abbreviation of the word bi-quadratic because the transfer-function contains two quadratic functions. There are various structures for the realization of IIR filter, but the simplest of all is direct form realization. Where a k and b k are coefficient which determines the frequency response characteristic of the system Equation of Bi-quad filter (4) The corresponding signal flow graph is shown in figure 5. (5)

5 Analysis of Performance and Designing of Bi-Quad Filter using Hybrid Signed digit Number System 177

6 IJECSE,Volume1,Number 2 Sugandha Agarwal and Krishna Raj 3.3. Complexity of Bi-quad Filter Total of four adders and multiplier are required to realize a Bi-quad filter. Delay of ripple carry adder is directly proportional to the word length. Hence the total delay of ripple carry adder is equal to the product of total number of bit and total number of adders. Therefore for 32 bit total delay in Bi-quad filter delay is 4 32= 128 unit delay. Whereas, in hybrid signed digit adder the delay may be calculated as Since we assume alternate signed and unsigned digits. Hence according to the above equation the delay of hybrid signed digit adder equal to 6 units per adder which is independent of word length. Therefore for 32 bit Bi-quad filter delay is 6 4= 24 unit delay Table 1 Table showing possible outcomes at different values of No. of bits Graph 1 Graph between delay and No. of bits for Hybrid signed digit adder and Ripple carry adder

7 179 Analysis of Performance and Designing of Bi-Quad Filter using Hybrid Signed digit Number System 4. CONCLUSION The redundant arithmetic adopted in this paper, eliminates the carry propagation chain and therefore addition is much faster compared to any other previous techniques. For simplicity and general consideration we consider a Biquad digital filter. As, we deduce from the graph that hybrid signed digit adder is better than ripple carry adder as the delay in ripple carry adder is increased as the word length is increased, whereas in hybrid signed digit adder delay is constant independent of word length. Due to which addition operation is much faster using hybrid signed digit adder. But hybrid signed digit adder is only preferable when accuracy and efficiency is main criteria, but when we have less area or memory space occupancy ripple carry adder is used. Hybrid signed digit adder can has its implementation in image processing as well as video processing. REFERENCES [1] Fairchild Semiconductor Staff (1973), The TTL Applications Handbook, Mountain View, Calif. [2] Gilchrist, B. et al. (1955), Fast Carry Logic for Digital Computers, IRE Trans., Vol. EC-4, pp [3] Reitwiesner, G. W. (1960), The Determination of Carry Propagation Length for Binary Addition, IRE Trans., Vol. EC-9, No.1, pp [4] Briley, B. E. (1973), Some New Results on Average Worst Case Carry,, IEEE Trans. Computer., Vol. C-22, No.5, pp [5] Sklansky, J. (1960), Conditional Sum Addition Logic, IRE Trans., Vol. EC-9, No.2, pp [6] Kruy, J. F. (1965), A Fast Conditional Sum Adder Using Carry Bypass Logic, AFIPS Conf. Proceedings, Vol.27, pp [7] Bedrij, O. J. (1962), Carry Select Adders, IRE Trans., Vol. EC-11, No.3, pp [8] Alexander, I. (1967), Array Networks for a parallel Adder and It s Control, IEEE Trans. on Electr. Computers, Vol. EC-16, No.2. [9] Avizienis, A. (1968), Logic Nets for Carry and Borrow Propagation, Class Notes, Dept. of Engineering, University of California, Los Angeles. [10] Ferrari, D. (1968), Fast Carry-Propagation Iterative Networks, IEEE Trans. Computer, Vol. C-17, No.2, pp [11] Lehman, M. and Burla, N. (1961), Skip Techniques for High Speed Carry Propagation in Binary Arithmetic Units, IRE Trans., Vol. EC- 10, No.4, pp [12] Lehman, M. (1962), A Comparative Study of Propagation Speed-Up Circuits in Binary Arithmetic Units, Inform. Processing, Elsevier- North Holland, Amsterdam, pp [13] Mac Sorley, O. L. (1961), High Speed Arithmetic in Binary Computers, Proc. IRE, Vol.49, No.1, pp [14] Sklansky, J. and Lehman, M. (1963), Ultimate Speed Adders, IRE Trans., Vol. EC-12, No.2, pp [15] Bartee, T. C. (1965), Chapman, D. J., Design of an Accumulator for a General Purpose Computer, IEEE Trans., Vol. EC-14, No.4, pp [16] Majerski, S. (1967), On Determination of Optimal Distribution of Carry Skips in Adders, IEEE Trans., Vol. EC-16, No.1, pp [17] Shedletsky, J. J. (1977), Comment on the Sequential and Indeterminate Behavior of End-Round Carry Adder, IEEE Trans. Comput., Vol. C-26, No.3, pp [18] Wino grad, S. (1965), On the Time Required to Perform Addition, Journal of ACM, Vol.12, No.2, pp [19] Spira, P. M. (1973), Computation Times of Arithmetic and Boolean Functions in (d,r)circuits, IEEE Trans. Comput., Vol. C-22, No.6, pp [20] Parhami, B. Generalized signed-digit number systems: a unifying framework for redundant number representations. IEEE Transactions on Computers, vol. C-39, Jan.1990, pp [21] Nagendra, C., Owens, R. M., and Irwin, M. J. Power Delay Characteristics of CMOS Adders. IEEE Transactions on VLSI, Sept. 1994, pp [22] Srinivas, H. R., and Parhi, K. K. A fast VLSI adder architecture. IEEE Journal of Solid-State Circuits, vol. SC-27, May 1992, pp [23] Phatak, D. S., and Koren, I. Hybrid Signed Digit Number Systems: A Unified Framework for Redundant Number Representations with Bounded Carry Propagation Chains. IEEE Trans. on Computers, Special issue on Computer Arithmetic, vol. TC 43, no. 8, Aug. 1994,pp [24] Ling, "High Speed Binary Parallel Adder", IEEE Transactions on Electronic Computers, EC-15, pp , October, 1966 [25] Nagendra, C., Owens, R. M., and Irwin, M. J. Unifying Carry Sum and Signed Digit Number Representations for Low Power. In Proceedings of International Symposium on Low Power Design, Dana Point, California Apr.1995.

8 IJECSE,Volume1,Number 2 Sugandha Agarwal and Krishna Raj [26] Avizienis, A. Signed-digit number representations for fast parallel arithmetic. IRE Transactions on Electronic Computers, vol. EC-10, Sep. 1961, pp