Quartus II Software Release Notes

Transcription

1 Quartus II Software Release Notes May 2009 RN This document provides late-breaking information about the following areas of this version of the Altera Quartus II software. For information about memory, disk space, and system requirements, refer to the readme.txt file in your \altera\<version number>\quartus directory. For information about device support in this version of the Quartus II software, along with the latest information about timing and power models, refer to the Quartus II Device Support Release Notes on the Altera website at This document contains the following sections: New Features & Enhancements on page 1 EDA Interface Information on page 2 Changes to Software Behavior on page 3 Known s & s on page 7 Platform-Specific s on page 15 Device Family s on page 17 SOPC Builder s on page 30 EDA Integration s on page 35 Memory Interface s on page 38 Simulation Model Changes on page 44 Latest Known Quartus II Software s on page 45 Software s Resolved on page 45 New Features & Enhancements The Quartus II software version 9.0 includes the following new features and enhancements: The Tasks window, which provides flow-based access to processes and tools available in the Quartus II software, now offers customizable flows based on the two standard flows. The Quartus II software version 9.0 provides the SSN Analyzer for improved signal integrity and faster board design. For each input and output pin in the design, the SSN Analyzer estimates the voltage noise caused by simultaneous switching of output pins on the device. The SSN Analyzer is available for the Stratix III device family. The new Archiver now allows you to either select pre-defined file sets or create custom file sets for archiving. SOPC Builder contains enhanced display filtering features that are useful for large system visualization. Advance support for these Arria II GX devices: EP2AGX20, EP2AGX30, EP2AGX45, EP2AGX65, EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260.

2 EDA Interface Information Page 2 Advance support for these Stratix IV devices: EP4SE230, EP4SE530, and EP4SGX180. In the Quartus II software version 9.0 SP1, advance support for these Stratix IV devices: EP4SGX70, EP4SGX110, EP4SGX230, EP4SGX290, EP4SGX360, EP4SGX530. Initial support for these Stratix IV devices: EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5. EDA Interface Information The current version of the Quartus II software supports the following EDA tools. Synthesis Tools Version NativeLink Support Synopsys Synplify & Synplify Pro C Mentor Graphics Precision RTL Synthesis 2009a update 1 Mentor Graphics LeonardoSpectrum 2008b Synopsys Design Compiler SP4 Mentor Graphics DK Design Suite 5.0 SP5 Simulation Tools Version NativeLink Support Mentor Graphics ModelSim 6.4a Mentor Graphics ModelSim-Altera 6.4a Mentor Graphics ModelSim-Altera Starter Edition 6.4a Cadence NC-Sim 6.2 (Linux only) Synopsys VCS / VCS MX Y SP1 Aldec Active-HDL 8.1 (Windows only) Aldec Riviera-PRO Formal Verification Tools (Equivalence Checking) Cadence Encounter Conformal 7.2 Version NativeLink Support NativeLink Chip Level Static Timing Analysis Version Support Synopsys PrimeTime Z Board Level Static Timing Analysis Mentor Graphics TAU Version NativeLink Support Board Level Symbol/Pin-out Management Mentor Graphics I/O Designer 7.4 Version NativeLink Support

3 Changes to Software Behavior Page 3 Changes to Software Behavior This section documents instances in which the behavior and default settings of this release of the Quartus II software have been changed from earlier releases of the software. Items listed in the following table represent cases in which the behavior of the current release of the Quartus II software is different from a previous version. Description Version 9.0 The Preserve Hierarchical Boundaries logic option is removed from the Quartus II software version 9.0. As a result, the Optimization Technique and Gate-Level Register Retiming logic options do not work when set on entities, unless the entity is a partition. Changes to the TimeQuest Timing Analyzer behavior in the Quartus II software version 9.0 include the following: set_net_delay now constrains from net (output pin) to net/keeper, not individual edges. read_sdc now processes HDL-embedded constraints before reading SDC files. report_min_pulse_width now performs pulse-width checks at all nodes in the clock network. The GXB Migration Guide Reports and temporary migration flow from Arria GX and Stratix II GX to Arria II GX and Stratix IV GX for customer evaluation are no longer available. Version 8.1 The Quartus II software version 8.1 supports Mentor Graphics ModelSim 6.3g. Mentor Graphics ModelSim-Altera Edition and Web Edition are labeled as 6.3g_p1. The Quartus II software version 8.1 automatically adds a clock frequency constraint of 10 MHz for the JTAG TCK clock pin for Cyclone III devices, Stratix III devices, and newer FPGA families. Version 8.0 SP1 Exporting a Memory Initialization File (.mif or.hex) to a RAM Initialization File (.rif) format is no longer supported in Quartus II software versions 8.0 and later. Version 7.2 The Generate back-annotation data for time closure option in the Design Entry/Synthesis page under EDA Tool Settings in the Settings dialog box is no longer available. Use partitions instead of entities. Instead of using the migration flow in the software, use a manual altgx migration.

4 Changes to Software Behavior Page 4 Description Constraining cells or routing causes problems for designs ported from the Quartus II software version 7.1 or 7.1 SP1 to the Quartus II software version 7.2, because location assignments to the following block types are incompatible: IOPAD IOIBUF IOOBUF FF DDIOOUTCELL DDIOOECELL PSEUDODIFFOUT CLKCTRL (if specified as X,Y,N instead of as a user string) For the alt2gxb megafunction, when adaptive equalization is activated for a specific channel, rx_eqctrl writes to that channel do not have any effect. In the Quartus II software version 7.2, there is no support for DQSB pins in Arria GX devices, but some Quartus II version 7.2 designs require DQSB pins. The Quartus II software no longer supports Synopsys Formality software. The Quartus II software no longer supports the Synopsys PrimeTime VHDL software. The TimeQuest Timing Analyzer supports clock-as-data analysis in the Quartus II software version 7.2, while previous versions of the Quartus II software did not. This results in the TimeQuest analyzer reporting new timing paths where the start point (from node) of the path is a clock node (the target of a create_clock or a create_generated_clock command. The Classic Timing Analyzer does not support clock-as-data analysis. The functionality of the earlier TimeQuest SDC File Editor has been merged into the main Quartus II Text Editor. The Constraints menu from the earlier TimeQuest SDC File Editor is now located in the Quartus II Text Editor on the Edit menu on the Insert Constraints submenu. Starting in the Quartus II software version 7.0, when you use OC-12 with Mhz inclock, the alt2gxb megafunction generates a design with incorrect data rate. The incorrect data rate is double of what you designed. The TimeQuest Timing Analyzer now performs multicorner timing analysis by default during full compilation. This behavior can be changed in the TimeQuest Timing Analyzer page in the Settings dialog box. To prevent this incompatibility, remove the location assignments and the routing constraints. Use the PrimeTime Verilog software to perform timing analysis for your design. To generate the PrimeTime Verilog files, select Verilog in the Format for output netlist list on the Timing Analysis page under EDA Tool Settings. The behavior, which is correct, is documented in "The Quartus II TimeQuest Timing Analyzer" chapter in the Quartus II Handbook. You may need to modify your constraints to compensate for the clock-as-data analysis support if new timing violations are listed for your design, and you believe these violations are overly conservative for your design. Starting in the Quartus II software version 7.2, when you use the SONET OC-12 protocol with the input clock frequency of Mhz, refclk divider is generated by the alt2gxb megafunction in order to obtain the correct data rate. Version 7.1

5 Changes to Software Behavior Page 5 Description When using the SignalTap II Logic Analyzer, if you select a signal to be tapped that cannot be found in the netlist, the Quartus II software will give a critical warning and proceed with compilation. This is a change of behavior from version 6.1 in which compilation would stop with an error message. The altlvds_tx megafunction shows the actual phase shift of the tx_outclock generated instead of the core clock frequency. This change is only a change in the information that is displayed, and does not change the actual implementation. PLLs in Stratix II and Cyclone II devices now have a new parameter, sim_gate_lock_device_behavior, that is OFF by default. This new parameter uses a fixed, internal value of 7 to simulate the gate lock feature. If the value is set to ON, you can simulate the actual device behavior for gated lock using the parameter value gate_lock_counter, as you could in earlier versions of the Quartus II software. To remove the warnings, remove nonexistent nodes from the SignalTap II Logic Analyzer. To revert to the behavior of version 6.1 and earlier, you can promote all critical warnings to error messages in the Messages section of the Options dialog box. The Quartus II software version 7.1 Power Analyzer enhances the accuracy of the maximum static power estimate for Stratix II and Stratix II GX devices. The maximum static power drawn from the VCCPD power supply for Stratix II and Stratix II GX devices utilizing maximum power characteristics increases in the Power Analyzer power estimate by at most 15mW (depending on the device size.) The Quartus II software version 7.1 issues the error: "Error (10621): VHDL Use Clause error at <location>: more than one Use Clause imports a declaration of simple name "<name>" -- none of the declarations are directly visible." However, the Quartus II software version 7.0 and earlier did not issue the error for the same design. This changed behavior arises when a design imports overloaded subprograms with the same signature from different packages such as STD_LOGIC_UNSIGNED and STD_LOGIC_SIGNED. Both these packages define binary operations on STD_LOGIC_VECTOR arguments. Earlier versions of the software incorrectly favored the first imported declaration. Remove one of the conflicting Use Clauses. For example, use either STD_LOGIC_SIGNED or STD_LOGIC_UNSIGNED, but not both.

6 Changes to Software Behavior Page 6 Description The format for Conversion Setup Files (.cof) has changed. The element defined below (in DTD syntax) has been introduced: <!ELEMENT hex_block (hex_filename,hex_addressing, hex_offset)> <!ELEMENT hex_filename (#PCDATA)> <!ELEMENT hex_addressing (#PCDATA)> <! hex_addressing value is either relative or absolute --> <!ELEMENT hex_offset (#PCDATA)> In addition the following elements have been deprecated: <!ELEMENT bottom_boot_block (bottom_boot_filename,bottom_ addressing)> <!ELEMENT main_block (main_filename, main_addressing)> Version 6.0 The TimeQuest Timing Analyzer's QSF2SDC conversion utility cannot properly convert all Classic Timing Analyzer timing assignments. The results from the TimeQuest Timing Analyzer may also be different from the Classic Timing Analyzer due to other default behavior differences. Beginning in the 6.0 release, the Quartus II Parallel Flash Loader megafunction (altparallel_flash_loader) erases flash memory blocks before programming them. Beginning in the 6.0 release, Quartus II integrated synthesis handles bidirectional pins differently. For example if bidir1 and bidir2 are declared as inouts, the assignment bidir1 <= bidir2 creates a directional connection in which data flows from bidir2 to bidir1. In the Quartus II software version 5.1 and earlier, a bidirectional connection was created. Version 5.1 SP2 and earlier The following megafunctions have clear box models that contain assignments that are not stored in the Quartus Settings File (.qsf) and are not written out to a Verilog Quartus Mapping File (.vqm): altdqs, altdq, altddio_bidir, altddio_out, altddio_input, altlvds_rx, altlvds_tx, altufm_i2c, dcfifo, alt2gxb_reconfig The QSF2SDC conversion utility is considered a guide to help reduce the time to switch to the TimeQuest analyzer, and it is not intended to make the TimeQuest analyzer a plug-in replacement for the Quartus II Classic Timing Analyzer. You should review all converted SDC constraints for correctness and completeness. Refer to the Switching To the TimeQuest Timing Analyzer chapter in the Quartus II Handbook for more information. No action is required. If your design requires that data flow in both directions, you must directly connect the bidirectional pins together without using an assignment statement. Assignment statements always produce a unidirectional data flow. Do not save your atom netlist file as a Verilog Quartus Mapping file if you are using these megafunctions.

7 Known s & s Page 7 Known s & s General Quartus II Software s When a RAM is inferred under all the following conditions, the synthesized circuit is not guaranteed to be correct: The read from and write to the memory occur in the same always block or process. The always block or process that reads/writes to the memory array is combinational. The write assignment happens before the read. The RAM is single-port. Version 9.0 SP1 To solve this problem, either disable RAM inference or rewrite the HDL description of the RAM. RAM inference can be disabled by setting the ramstyle attribute to "logic" or by setting the auto_ram_recognition variable to Off. Alternatively, a different HDL description can be used for the RAM (refer to the "Inferring Memory Functions from HDL Code" chapter in the Quartus II Handbook). When you compile a project, and then try to open the Assignment Editor, the Quartus II software displays an internal error if the selected devices in the Migration Devices dialog box include EP4SGX290KF40C3, EP4SGX360KF40C3, and EP4SGX530KH40C3. An internal error occurs when you use Incremental SignalTap II to tap an output port that is stuck at VCC or GND. Internal Error: Sub-system: AMERGE, File: /quartus/atm/amerge/amerge_incr_tap.c pp, Line: 6076 oterm Stack Trace: 0x19F1C : amerge_mini_merge + 0x16B3C (atm_amerge) End-trace In the Device page in the Settings dialog box, click Migration Devices. In the Migration Devices dialog box, click OK to close the dialog box. In the Device page, click OK to close the page. Remove the tap node from your SignalTap II instance. In projects targetting Stratix IV GT and Arria GX devices, transceivers with ALTGX instances created in the Quartus II software version 9.0 SP1 might display an internal error in versions of the Quartus II software later than 9.0 SP1: Internal Error: Sub-system: FHSSI, File: /quartus/fitter/fhssi/fhssi_cell_grou p.cpp, Line: 1463 aux_cell!= NULL Regenerate the ALTGX instances. Version 9.0

8 Known s & s Page 8 In the Quartus II software version 9.0, the set_net_delay Tcl command is optimized by the Fitter, but in the Quartus II software version 8.1, it was not. The Quartus II software version 8.1 did not correctly synthesize case statements if the case expression is smaller than the case item expressions and contained a binary or ternary operator, for example (address << 2). The ALTGX MegaWizard allows the reset ports to be selected or deselected. But deselecting the reset ports may make the simulation output become undefined. If you use the Advanced I/O Timing feature and migrate from the Quartus II software version 8.1 or earlier, you may see decreased minimum pulse width requirements on the I/Os compared to the previous versions. This can result in increased f MAX on some paths. The change only applies only to I/O pins with board trace models that include transmission lines. In the Quartus II software versions 9.0 and later, STRATIX_II_TERMINATION assignments are ignored for Cyclone III, Stratix III, and Stratix IV. When a design targeting the Arria II GX or Stratix IV families is simulated in the Quartus II software, the rx_bistdone output signal of the altgx megafunction does not go high in PRBS high, low, or mixed frequency settings. This behavior is expected hardware behavior, and the data pattern generated is for PMA signal observation. The Quartus II software version 9.0 correctly optimizes this command in the Fitter. Re-run the Fitter on your design in the Quartus II software version 9.0. The incorrect synthesis is fixed in the Quartus II software version 9.0. To avoid the issue when compiling with the Quartus II software version 8.1, increase the size of the case expression. You can do this artificially by adding <N>'sb0 to the expression, where <N> is the size of the largest case item expression. Always keep the reset ports enabled. In the Quartus II software version 9.0, these assignments are ignored. Use the Input Termination and Output Termination logic options to make on-chip termination (OCT) assignments in Cyclone III, Stratix III, and Stratix IV device families. Check the Fitter report panels after fitting to verify which OCT value is applied to each pin. Ignore rx_bistdone and rx_bisterr in these settings. In the ALTGX MegaWizard, the GT Common Mode Voltage is 1.2V, but the MegaWizard shows 1.1V. During simulation in the Quartus II software version 9.0, the output busy signal becomes stuck in an undefined state even if any of the inputs to the altgx_reconfig block are correctly set as undefined. Designs targeting Stratix IV devices and that contain instances of the altgxb megafunction may take more than an hour in Analysis & Elaboration or Analysis & Synthesis. To use the OpenCore Plus hardware evaluation feature with unlicensed IP that supports the feature, you must first select a specific device. The Quartus II software version 9.0 and later does not support the OpenCore Plus hardware evaluation feature for Auto devices. The Quartus II software ignores the incorrect voltage. Add a reset port. On the Device page in the Settings dialog box, turn on Specific device selected in Available devices list and select a specific device in the Available devices list.

9 Known s & s Page 9 The following Internal Error in the Quartus II software version 9.0 occurs because RAMs with one word are not allowed in the Quartus II software version 9.0. Internal Error: Sub-system: ASMRAM, File: /quartus/comp/asmram/asm_ram_model_ba se.cpp When you select an item in the Data Transfer FIFO Depth list in the Scatter-Gather DMA Controller MegaWizard, the selection has no effect because the actual FIFO depth is a value calculated from a fixed formula. In the Quartus II software version 9.0, when Perform Physical Synthesis for Combinational Logic for Performance, formal verification cannot be used for 45nm and 65nm device families. When setting the formal verification tool, you may see an error. If the design uses the altgx megafunction and dynamic reconfiguration with an alternate Transmitter PLL, there is a problem when the alternate transmitter PLL logical reference index is 0. The issue could occur when placing two channels in the same quad, and each channel then starts up using different PLLs. The problem you see is the following internal error during Analysis & Synthesis: Internal Error: Sub-system: DSTR, File: /quartus/h/dstr_translator_auto.cpp, Line: 1773 The calling function has passed an illegal DEV_PART_ENUM Stack Trace: 0x9BE8 : DSTR_TRANSLATOR::get_user_string + 0x28 (DDB_DSTR) 0x1900 : dstr_get_user_string + 0x10 (DDB_DSTR) 0x36DA02 : cut_get_clock_divider_cdb_atom_tgx_hs si_clock_divider_enum_tgx_hssi_pll_ba se_data_rate_tgx_hssi_config_atom_nod es + 0x153F2 (db_cut) The following input clock frequencies are invalid for SONET OC12, but show up in the ALTGX MegaWizard: MHz MHz MHz Update the design to remove the one-word RAM. If the affected design contains DSP logic generated with DSP Builder, re-generate the DSP logic with DSP Builder version 9.0. In the Quartus II software version 9.0, keep the default and do not change the selection in the Data Transfer FIFO Depth list. Specify the base data rate on the first page of the MegaWizard. Choose only one of the following input clock frequencies: MHz MHz MHz MHz MHz

10 Known s & s Page 10 When you click Open Options dialog box - Text Editor page in the Use an External Text Editor page in the Tips & Tricks in the Quartus II software, the Printing page in the Options dialog box opens. When you use the CMU PLL, the ALTGX MegaWizard does not allow you to disable the central clock divider option. In the Quartus II software version 8.1, clock uncertainty assignments that are automatically applied by derive_pll_clocks for soft-cdr was too pessimistic for the rising edge to rising edge and falling edge to falling edge clock transfers of loaden signal for hold analysis. The ALTGX MegaWizard allows you to choose the ATX PLL for PCIe 2.0 applications; however, this configuration doesn't work properly in 230ES or 530ES silicon. Currently the MegaWizard for the Floating Point Matrix Multiplier megafunction allows you to create a multiplier of 256 or more columns in matrix AA, or rows in matrix BB. However, the actual supported column size of matrix AA or row size of matrix BB must be less than 256, or you will receive an unexpected result. If you set the value of the base data rate different from the value of the effective data rate, the pre_divide_by on the <family name>_hssi_clock_divider is incorrect. In the Category list, click Text Editor in the Options dialog box. Run the following command: qmegawiz -silent -wiz_override=use_global_clk_divider=false <design> Either run timing analysis in the Quartus II software version 9.0 or manually set the uncertainty value of rising edge to rising edge and falling edge to falling edge clock transfers of the loaden signal to 0 for hold analysis. The ATX PLL placement constraints may be more constrained for some devices, and it s recommended that the pin out is created with the ATX PLL. Once the pin placement is fixed, update the ALTGX instance and choose the CMU PLL for the PCIe 2.0 configurations. Manually update the value to the required value so that the value of base_data_ratefor pre_divide_by is the same as the value for effective_data_rate. In the Quartus II software version 8.1 and later, the Tcl project_open and set_current_revision commands no longer overwrite the compilation database when the database version is incompatible with the current version of Quartus II software. Instead, they generate an error. The Assignment Editor does not allow you to edit the location assignment of the GXB Central control unit. When LVDS transmitter is implemented using logic cells and when you select Odd deserialization factor, the MegaWizard allows you to choose between the tx_inclock and tx_coreclock port to register the tx_in port. However, it is incorrect to register tx_in using the tx_coreclock. This issue does not affect LVDS implementations using the hard SERDES or any implementation using even deserialization factors. The timing constraints auto-generated by the Quartus II software for the altlvds rx_divfwdclk output (that is, when in Soft-CDR mode) were incorrect in versions of the Quartus II software earlier than 8.1. The constraints did not correctly account for an inversion in the rx_divfwdclk clock path. Version 8.1 To avoid the error and overwrite the database, run project_open -force or set_current_revision -force. Modify the assignment manually in the Quartus II Settings File (.qsf) while the project is closed. Either preregister the tx_in using a clock with frequency of (output_data_rate/deserialization_factor), or supply a clock of this frequency to the LVDS via the tx_inclock input port and use that clock to register the tx_in inputs. This issue has been resolved in the Quartus II software version 8.1. Modify designs using a Synopsys Design Constraints File (.sdc) with rx_divfwdclk timing constraints generated by a version of the Quartus II TimeQuest Timing Analyzer earlier than 8.1 to use the correct timing constraints (as generated with the current version of the TimeQuest analyzer).

11 Known s & s Page 11 The Enable column in the Pin Planner shows only location assignments, and does not show whether other types of assignments are disabled or enabled. Use the Assignment Editor to view and disable assignments. If you compile a project in the command line, and you open the Quartus II software GUI on that project, you may experience unexpected and/or incorrect results. The Open dialog box does not display all files. Creating a new project from the TimeQuest Timing Analyzer GUI can crash the TimeQuest analyzer GUI. The following error occurs when you manually connected the seriesterminationcontrol and parallelterminationcontrol ports on an output buffer atom, but did not make a termination assignment to the corresponding I/O that uses calibrated on-chip termination: "Output buffer atom <name> has port <name> connected, but does not use calibrated on-chip termination" When you connect the dynamic termination control port on the output buffer of a dedicated output I/O, the error "Output I/O <name> has dynamic termination control connected" occurs in a design with no previous errors. An error is issued saying that an output is inverted when feeding the dynamicterminationcontrol port of an output buffer atom. If there are Dynamic Termination Control Group assignments to two different I/Os in the design that have different dynamic termination controls but are assigned to the same group, you will receive the following error: "Atoms <name> and <name> are assigned to the same dynamic termination control group, but their dynamic termination controls are not compatible" The Merged Registers and the Inverter Push-Back Through Register report panels under the Analysis & Synthesis Formal Verification report may be missing or incomplete in the Quartus II software versions 8.0 and later. Version 8.0 While compiling a project in the command line, do not open the Quartus II software GUI on that project. Restart the Quartus II software to see all the files. Because the TimeQuest analyzer GUI depends on the open project in the main Quartus II software GUI, create or change projects in the main Quartus II software GUI and not the TimeQuest analyzer GUI. Disconnect the seriesterminationcontrol and parallelterminationcontrol ports on the specified output buffer atom, or make an Input Termination or Output Termination assignment to the corresponding pin that uses a value that includes With Calibration. If the I/O was generated as part of an IP block, regenerate the IP block. If the I/O was user generated, then disconnect the dynamicterminationcontrol port, or connect it to 0 or logical ground. Remove the specified inversion. Remove all Dynamic Termination Control Group assignments from the design, because they are no longer necessary. If the assignments were created by an IP block, regenerate the block. The information is available in the following two report panels in the Analysis & Synthesis Optimization Results report under Register Statistics: Registers Removed During Synthesis (for merged registers), and Inverted Register Statistics (for inverted registers)

12 Known s & s Page 12 In the Quartus II software versions 8.0 and later, I/O primitives do not support exact pin location assignments for designs targeting Cyclone III, Stratix III, and Stratix IV devices. If your design contains I/O primitives with exact pin location assignments, you will see the following error: The location assignment on the I/O Primitive instance "inst1" specifies an exact pin location Projects created in versions of the Quartus II software earlier than version 8.0 that use Incremental Compilation will not work properly with the smart compilation feature in the Quartus II software versions 8.0 and later. A message specifying a detected change in the partition_hierarchy assignment is issued and all stages of the flow are executed. Design Space Explorer, which leverages smart compilation technology, is also affected. A new assignment check was introduced in Quartus II software version 8.0 that checks whether I/Os are fully constrained. Any I/Os that are not fully constrained appear as a line in a table in the Fitter report under I/O Assignment Analysis Warnings. The reason for the warning appears in the table. Certain conditions are warnings; others are errors. For example, an I/O with no assignments at all will have a reason of "Incomplete set of assignments" and an I/O with only an I/O standard assignment will have a reason of "Missing drive strength and slew rate". Instead of using an I/O primitive you can set an exact location using the chip_pin attribute, or through the Assignment Editor. In the Quartus II software versions 8.0 and later, open the project in the GUI and re-save the project before using the Design Space Explorer or smart compilation. Fully constrain I/Os to remove these warnings. When reading a Memory Initialization File (.mif), Quartus II software versions 7.2 and later generate uninitialized memory addresses messages, such as: Warning: 2 out of 32 addresses uninitialized. Initializing them to 0. 2 warnings found. Warning: Address 1 is not initialized. Warning: Address 3 is not initialized. Quartus II software versions earlier than version 7.2 do not have this issue. Live I/O check may produce an error if reserved pin directions are changed while live I/O check is enabled. Version 7.2 SP1 Open the affected Memory Initialization File and search for the % character. Because the Quartus II software version 7.2 supports multiline commenting beginning with a % and ending with a %, if the % character is found in the Memory Initialization File, ensure that it does not act as a multiline separator that treats the address data as a comment, or remove the % in the Memory Initialization File. Version 7.2 Turn live I/O check off and back on again to remove the error.

13 Known s & s Page 13 Using Parallel Flash Loader IP optimized for speed adversely affects the CFI device programming time when using the EthernetBlaster download cable. Use the USB Blaster or ByteBlaster II download cable instead of the EthernetBlaster Download Cable, or use the Parallel Flash Loader IP optimized for area instead of speed. On Windows, the following cores may fail to run when the PERL5LIB environment variable is set: 8B10B Encoder-Decoder POS-PHY Level 4 RapidIO SerialLite II Version 7.1 Delete the PERL5LIB environment variable: Right-click My Computer and click Properties. Click the Advanced tab, and then click Environment Variables. Delete PERL5LIB under both User variables and System variables. Restart the Quartus II software. The Quartus II software can reduce RAM by modifying control signals while maintaining functionality. For example, in many cases a read enable can be converted into a clock enable. If you open the Print dialog box or the Page Setup dialog box in the Quartus II software, and if you use an HP Business Inkjet 1200 series printer, the Quartus II software may produce an unexpected error. Altera recommends that all soft-cdr channels driven by a PLL are within a distance of 25 SERDES rows (including the unbonded SERDES) from that PLL. When you launch documentation (PDF and HTML files) from the MegaWizard Plug-In Manager, the MegaWizard uses the Web browser option in the Internet Connectivity page of the Quartus II Options dialog box. The MegaWizard will sometimes use a setting from a previous version of the Quartus II software than the present version. This can lead to errors if the web browser does not exist on your machine. If you have this printer, Altera recommends updating to the latest version of the drivers, available for free download from the HP website. Manually edit the WEB_BROWSER variable in the quartus2.ini file and remove the reference to the non-existent web browser. You may get one or more messages "Error: Can t generate programming files for project because design file "<name>" is encrypted. It does not have license file support that allows generation of programming files" from the Assembler when compiling a design that is using Altera IP with the OpenCore Plus evaluation feature when your design has VHDL source files that have the construct "use work.all;". When a design contains IP that is evaluated using the OpenCore Plus hardware evaluation feature, the Quartus II software produces a sequence of Info messages beginning with Info: Elaborated megafunction instantiation "pzdyqx:nabboc". Version 6.1 The errors are reported for IP source files that were added to your project by IP Toolbench, but which are not actually used during compilation. Remove the files listed in the error messages from your project file list and recompile the design. These messages can be safely ignored. Version 6.0 SP1

14 Known s & s Page 14 Running multiple instances of the Quartus II software using the same Quartus Project File (.qpf) may cause unpredictable results or may cause the Quartus II software to crash. Altera recommends that you not open multiple instances of the Quartus II software using the same project. In the classic Timing Analyzer, when a clock (base or derived) is assigned to an internal register, then data paths to and from the register are not analyzed for clock setup and clock hold analysis. The TimeQuest Timing Analyzer erroneously analyzes paths to the asynchronous data pins of registers (that is, the adata pin) during a recovery/removal analysis. If you change the type of a parameter setting in the Quartus II Settings File (.qsf) or a Block Design File (.bdf) and recompile your design, your change appears to have no effect. The type of a parameter is denoted by appending a prefix such as B (binary), D (decimal). For example, B represents the binary string 10101, but D represents the decimal number Path names longer than 229 characters can cause an internal error in the Quartus II software. If you make a single-point CUT=ON assignment to a node, and then override it with a point-to-point CUT=OFF assignment on a specific path, the OFF assignment will not be honored. The Classic Timing Analyzer does not recognize non-pll clock signals when using any PLL megafunction. The Quartus II software does not support design file names with more than one extension. For example, you cannot use the file name file.eda.edif. Running individual Quartus II software executables (quartus_map, quartus_fit, and so on) from within the Quartus II Tcl Console may cause the Quartus II software to crash. Do not open, change permissions, or delete the /<project directory>/db directory or any file therein while any Quartus II executable is running. Version 6.0 First, analyze the design with the clock settings assigned to the internal registers. Then remove the clock settings from the internal registers and perform a second analysis, checking only paths to and from those registers. The other resolution is to use the TimeQuest Timing Analyzer instead of the classic Timing Analyzer. Apply the set_false_path command from the asynchronous data signal s source port or register to declare these paths as false paths. Delete the <project>\db directory and recompile the design. Version 5.1 SP2 and earlier Make sure that all path names do not exceed 229 characters. This limitation applies to Windows and Linux platforms. Make clock settings assignments to all non-pll clocks. Use design file names with only one extension. Run individual executables either from within the Quartus II scripting shell (quartus_sh) or directly at a command prompt.

15 Platform-Specific s Page 15 Platform-Specific s Windows Platforms Only For Windows Vista 64-bit, when you install the update for the Quartus II software version 9.0 SP1, the software requires you to terminate the jtagserver process before you update. When Parallel Synthesis is on, the Stop button in the Quartus II software GUI may not stop all the child processes of quartus_map in Windows. The introduction of Microsoft Security Update MS prevents the proper display of Quartus II Help across a network, including displaying popups. When you install the Quartus II software version 7.2 SP1, the Nios II IDE, or any Altera-provided patches on Windows Vista with User Account Control (UAC) turned on, the Program Compatibility Assistant issues the warning: "This program might not have installed correctly." Version 9.0 SP1 Version 9.0 Version 8.0 Version 7.2 SP1 Reboot before installing the Quartus II software version 9.0 SP1, without opening the 9.0 software in between rebooting and installing. Use the Task Manager window to stop all the child processes. To properly display HTML Help files, you must access them from a local PC. If you are unable to access Help files locally, go to Microsoft Knowledge Base Article (support.microsoft.com/?kbid=896054) for more information about possible workarounds. You can safely ignore this message by selecting This program installed correctly or you can turn off UAC before installing the software. If you do not have Administrator privileges when you install the Quartus II software, certain features of the software, particularly the online Help, will not work properly, for example: Software guards (parallel and USB) Programming with JTAG server Version 5.1 SP2 and earlier Altera recommends that you have Administrator privileges when installing the Quartus II software. If the full, hierarchical name of an instance exceeds 247 characters, it may not be displayed properly in the Quartus II user interface. This problem occurs most often with EDIF netlist files generated by other EDA synthesis tools. If you install the stand-alone Quartus II Programmer and the Quartus II software, and then uninstall either one, the Programmer may report "JTAG Server -- internal error code 82 occurred" when you click the Add Hardware button in the Hardware Setup dialog box on the Edit menu. This error occurs because uninstalling the software has disabled the JTAG Server service. Limit the full, hierarchical instance name to fewer than 247 characters if possible. Manually restart the JTAG Server service by locating the jtagserver.exe program and at a command prompt for that directory, type jtagserver --install <Enter>

16 Platform-Specific s Page 16 Linux Platforms Only After you generate fan-in connections in the Chip Planner, the print preview is blank. Version 9.0 The Altera Complete Design Suite version 8.1 cannot be installed from the default DVD mount point on Red Hat Linux bit and 64-bit machines. On Linux, the MegaWizards for ALTFP_INV, ALTFP_INV_SQRT, ALTFP_EXP, and ALTFP_LOG may exit unexpectedly if you don t wait for the resource estimate display to finish updating. For wide data, this update could take several minutes. If you click Finish before the resource display is updated, the wizard results are still valid, but the MegaWizard may exit unexpectedly after it completes. Under Linux Red Hat Enterprise version 5 64-bit, opening the Text Editor during a compilation may occasionally cause the Quartus II software to crash. Under some circumstances, your web browser software may fail to launch correctly from the IP MegaStore MegaWizard Plug-In Manager. The web browser defined in the MegaWizard Plug-In Manager for the IP MegaStore inherits the environment settings from the Quartus II software. Specifically, the LD_LIBRARY_PATH environment variable may contain entries that conflict with web browsers such as FireFox, preventing them from starting correctly. While any shortcut menu is open from an undocked dockable window, if you right-click the title bar, then all activity in the title bar (left-click and drag, shortcut menu, 'X' close button) stops working. Version 8.1 To install the Altera Complete Design Suite version 8.1 on Linux 5.0: 1. Insert the DVD disc. 2. Run mount -o ro,nosuid,nodev,uid=0 /dev/<cd_device_node> /<mount_directory> If you are using CentOS 5, <cd_device_node> is hdc. 4. Run /<mount_directory>/install. It is safe to ignore this unexpected exit. Wait until the compilation completes before opening the Text Editor. Version 6.1 Edit the script that launches the web browser to make sure the Quartus II directories are the last entries in the LD_LIBRARY_PATH variable. Version 6.0 Display a shortcut menu again and perform any action except right-clicking in the title bar to restore normal operation.

17 Device Family s Page 17 Device Family s Arria II GX Arria II GX transceiver channel reconfiguration support is incomplete in the Quartus II software version 9.0. The reconfiguration Memory Initialization File (.mif) required for channel reconfiguration is not generated by the Assembler. Version 9.0 Manually change the device to a Stratix IV EP4SGX230ES device on the Device page in the Quartus II software, and compile the design to generate a Stratix IV MIF. This MIF can be used in designs targeting Arria II GX devices, because the subset of features supported by Arria II GX devices are equivalent to those in Stratix IV devices. The altgx_reconfig 'error' port is asserted due to this difference, but this error can be ignored.

18 Device Family s Page 18 Cyclone III In the Quartus II software version 8.0 and later, for designs targeting Cyclone III devices, the Fitter may introduce incorrect logic when you select Extra Effort in the PowerPlay power optimization option in the Analysis & Synthesis Settings page. Designs with M9K memory blocks that use both the clock enable and rden (read enable) signals may be affected. Version 9.0 SP1 Select Normal compilation for the PowerPlay power optimization option. Alternatively, disable Fitter power optimizations on memory blocks only by setting Optimize Power during Fitting to Normal Compilation on your memory blocks using the Assignment Editor. If you use DDR or DDR2-SDRAM memory interfaces in designs targeting Cyclone III devices, you may receive the following warning from the TimeQuest Timing Analyzer: Critical Warning: The register <name> fed by pin <DQ or CK0 pin> must be placed in adjacent LAB <name of adjacent LAB> instead of <name of current FF location> to the result. When you receive one of the following messages, there is a timing violation issue that needs to be fixed: Critical Warning: The register <name> fed by pin <DQ or CK0 pin> must be placed in adjacent LAB <name of adjacent LAB> instead of <name of current FF location> to the result Critical Warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os Info: DQ capture register <name> at <location> is not assigned to the adjacent LAB of the corresponding DQ I/O <name> at <location> Version 8.0 If the adjacent LAB is already used by DDIO input registers for other pins, you may receive this warning because no more than two global clocks (inverted clocks are counted separate from non-inverted clocks) may feed a LAB. To fix the warning, you need to move the CK0/CK0# pins to a location with a free adjacent LAB. A possible solution is to swap CK0/CK0# with CK1/CK1# or CK2/CK2#. Fix the problem to avoid violating assumptions made with the macro timing analysis used for Cyclone III devices. A possible solution is to swap CK0/CK0# with CK1/CK1# or CK2/CK2#. Stratix Designs compiled for Stratix EP1S40ES devices must be recompiled for the EP1S40 device before programming.

19 Device Family s Page 19 Stratix GX Timing simulation performed in the Quartus II software on designs that use the altgxb megafunction in Stratix GX devices is not accurate on the rx_clkout and rx_out outputs. The simulation is functionally correct, but the relative timing delays between the signals are not accurate. Stratix II GX Version 6.0 Perform your timing simulation in another tool such as ModelSim. Versions of the Quartus II software earlier than 8.1 allowed illegal GXB configurations with very high PLL input clock frequency and very lower GXB datarate. Compiling these configurations in the Quartus II software version 8.1 produces an error. The VCS flag -ntb_opts +check can produce the following error when running Synopsys VCS simulation using stratixiigx_hssi_atoms.v (alt2gxb simulation library): Error: Illegal array access. This out-of-bound/illegal array access at time 0 happens at unused channels/blocks where default parameter values and initial values of ports are not consistent. Stratix II GX post-fit compiler databases created in the Quartus II software version 7.1 are not backwards compatible with the Quartus II software version 7.2. The latency of alt2gxb megafunction simulations on Stratix II GX is not accurate in comparison to the device. This is due to approximation used in the Quartus II simulation in modeling the analog portion of the hardware. The latency on the digital portion is within the range of a few clock cycles of the device. The latency is an exact match with the hardware when input vectors are carefully made and do not contain any race conditions. Version 8.1 Version 7.2 Version 6.0 For the Quartus II software version 8.1, re-generate the design with the MegaWizard, and change to the frequency and datarate to adhere to the new limits, as necessary. Remove the +check+ option when compiling stratixiigx_hssi_atoms.v. The check is to report specifically out-of-bound or illegal array access (no other type of checking). Rerun the Fitter after importing Stratix II GX projects compiled in the Quartus II software version 7.1. The Stratix II GX Handbook has specified latency range information. The latency information from Quartus II simulations is a good approximation.

20 Device Family s Page 20 Stratix III You may see an Internal Error during timing analysis on a design targeting a Stratix III device to an I/O with a current strength setting of Minimum Current or Maximum Current. If a design that targets Stratix III devices uses LVDS RX in an I/O row, you cannot use half-rate DDR on the TX pins of the same I/O row. As a result, you cannot use DQ pins of a DDR memory interface together with LVDS RX in any Horizontal I/O row. Stratix IV Version 8.0 Version 7.1 Replace the current strength setting on the I/O with a correct current strength setting (for example, 12mA), instead of a maximum or minimum. When you use RX PMA-direct on Stratix IV devices, the timing model in the Quartus II software is incorrect. As a result, the placement algorithm may put a register too close or too far away from the high speed interface. It appears to meet timing in the Quartus II software, but when it runs on silicon, this inaccurate register placement causes timing violations. This issue does not show up in PCS mode because the phase comp FIFO in the PCS resolves this timing issue. Version 9.0 SP1 Transceiver designs using the Auxiliary Transmit (ATX) PLL might produce the following error: Error: ATX Atom "atx_pll" at location "HSSIPLL_X0_Y25_N135" requires a calibration block at location "CALIBRATIONBLOCK_X0_Y2_N135" When you instantiate an altgx megafunction in a design that targets a Stratix IV device and uses Basic (PMA Direct) protocol, ignore the Logical address of the PLL on the Reconfig page. Version 9.0 If no existing placed calibration blocks from another transceiver are placed in the corner driving the specified ATX, then one must be implicitly created with a dummy transceiver. Do this by moving or making existing transceiver channel pin assignments in the Pin Planner so that the pins are placed into transceiver blocks 0 or 1 on the same edge of the device as the ATX. You can also create a new transceiver instance of any type and assign one or more pins to the transceiver block 0 or 1 on the same edge of the device as the ATX location.

21 Device Family s Page 21 A GPLL is needed to support PMA-direct channels running at higher data rates. Most of the time, the Quartus II Fitter places the GPLL on the same side as the HSSI channel, as expected. However, sometimes the GPLL and the HSSI channel are placed on different sides. As a result, if the channels and the GPLL are placed on different sides of the device, the phase-shifts suggested in the Stratix IV Handbook no longer apply, and the design might fail timing. In the Quartus II software version 9.0, the alt_oct megafunction works in designs that target the Stratix III device family but failed to begin calibration for the Stratix IV device family. Make a location assignment to the GPLL to ensure that it is on the same side as the HSSI channel. Starting in the Quartus II software version 8.1, an altgx megafunction in a design that targets Stratix IV devices generates reconfig_togxb[3:0] input bus. Rx_analogreset is ignored and rx_pll may not work properly in Quartus II simulation if these ports are not connected appropriately. Although the ALTGX MegaWizard allows disabling the Insertion of deletion of consecutive characters or order sets option under Rate Match FIFO on the Rate match/byte order page, this option should not be disabled. When you choose a base datarate of 6500 Mbps or more and the effective datarate is 1/2 or 1/4 of the base datarate, only an input clock frequency that is 1/20 the base datarate should be allowed. However, the MegaWizard and Compiler currently allow multiple input clock frequencies. Version 8.1 You must connect reconfig_togxb with reconfiguration controller because of silicon requirements. For functional simulation or module level simulation, you can connect reconfig_togxb[3:0] = 4 b0010 if you do not have a reconfiguration controller in the same scope to connect. You must turn on the Enable insertion or deletion of consecutive characters or ordered sets option if the ALTGX configuration meets all of the following requirements: Basic protocol Double serializer block width Rate Math FIFO enabled When you choose a base datarate of 6500 Mbps or more, do not choose an effective datarate that is different from the base datarate.