Building Gigabit Interfaces in Altera Transceiver Devices

Transcription

1 Building Gigabit Interfaces in Altera Transceiver Devices Course Description In this course, you will learn how you can build high-speed, gigabit interfaces using the 28- nm embedded transceivers found in Cyclone V, Arria V and Stratix V FPGA families. You will be introduced to the transceiver architecture and how the transceivers are configured to support various high-speed protocols. You will learn how to optimize and debug both the digital and analog sections of your transceiver design. You will gain an understanding of the transceiver reconfiguration controller and how you can use it to fine tune transceiver settings and add flexibility to your transceiver design. Lastly, you will be made aware of common gotchas that occur in transceiver designs and what steps you can take to avoid them. This course also enriches digital engineers with many years of experience. Course Duration 2 days

2 Goals 1. Implement high-speed serial protocols in Altera 28-nm embedded transceivers 2. Optimize analog settings to improve behavior using Altera tools 3. Employ transceiver reconfiguration to dynamically change transceiver behavior insystem 4. Improve transceiver usage and avoid transceiver design issues by applying an understanding of device architecture to design situations Intended Users Hardware engineers who develop FPGAs and would like to build gigabit interfaces Previous Knowledge FPGA design Quartus and TimeQuest SignalTap II Note: familiarity with high-speed interfaces and transmission protocols is helpful, nut not required Course Material 1. Synthesizer and Place & Route: Quartus II (ALTERA) 2. Course book (including labs)

3 Table of Contents Day #1 Transceiver Design Creation Introduction to Altera s Transceivers o What is a transceiver? o Definition: MAC, PCS, PMA o Altera transceivers FPGAs families Transceiver Design Creation o 28-nm transceiver architecture o Transceiver locations o Transceiver layout o Non-bonded versus bonded Receiver o Receiver path definition o Receiver PMA blocks o RX PMA functional block descriptions o RX PCS architecture support functional blocks RX PCS data widths Word aligner block modes of operation Rate match FIFO block Byte ordering block o RX 10G PCS blocks RX 10G PCS functional block descriptions RX FIFO modes RX low latency PCS mode RX PMA direct mode o RX PCIe Gen3 PCS functional blocks RX PCIe Gen3 PCS functional block descriptions Transmitter o Transmitter path definition o Transmitter block diagram o TX PCS functional blocks TX PCS functional block descriptions o TX 10G functional PCS blocks TX 10G functional PCS block descriptions TX low latency PCS functional blocks TX PMA direct mode o TX PCIe Gen3 PCS functional blocks TX PCIe Gen3 PCS functional block descriptions o Transmitter PMA functional blocks

4 o Which blocks/configuration do I need? o Loopback types Transceiver Clocking o Receive clock generation o Transmit clock generation o CMU PLLs o ATX PLLs o Fractional PLLs o Transmitter local clock dividers o Central clock dividers o Input reference clock sources o Input reference clock pins o Reference clock network o RX pins Transceiver Reset Signals o Reset solutions o Example configuration: PCI-E Gen2 o Example configuration: 10GBASE-R o Device differences (Cyclone/Aria/Stratix) PHY IP Cores o Transceiver PHY IP cores o Non-protocol-specific PHY IP cores o Native PHY IP cores o Native PHY IP interfaces o Clock signals o Parallel data interfaces o Parallel data interface bit assignment o PCS/PMA control and status interface o Serial interface o Reset control and status interfaces o Native PHY IP parameter editor o Other custom protocol PHY IP cores o Protocol-specific PHY IP cores o PHY IP output files for compilation o RTL simulation o Qsys and PHY IP cores o Transceiver PHY reset controller IP core Lab #1: Configuring a Native PHY IP Core

5 Day #2 Link Bring-Up Setting Analog Parameters o RX buffer analog SI features review o CTLE o DFE o TX buffer analog SI features review o Analog Settings Link Analysis & Simulation o Transceiver link simulation o PELE o Simulation model comparison (HSPICE/IBIS-AMI/PELE) o PELE configuration o PELE simulation o Obtaining link analysis and simulation files Transceiver Toolkit o Quartus II transceiver toolkit overview o Transceiver toolkit GUI o Auto sweep o EyeQ o Design examples o Design example structure in Qsys o Design example modifications o Recommended user flow Lab #2: Using the Transceiver Toolkit Transceiver Reconfiguration o What is transceiver reconfiguration? o Transceiver reconfiguration uses o Why should I care about reconfiguration? o Reconfiguration and device support Transceiver Reconfiguration Controller o Reconfigurations modes o Reconfiguration diagram o Reconfiguration controller interfaces o Logical channel numbers o Reconfiguration controller address map o Controller offset example o Basic register-based read and write operations o Enabling transceiver reconfiguration o Controller design example scenarios

6 Example Reconfigurations o Calibration overview o Megafunction settings for calibration o Performing calibration o PMA reconfiguration o PMA register map o PMA offsets Transceiver Design Best Practices Resource Optimization o Choosing the best PLL (ATX/Channel/fPLL) o Merging TX PLLs o Why is understanding clocking important? o Transceiver clocking o Reference clocks o Reference clock pin recommendations o Internal clocking (TX clock network x1/x6/xn) o PLL feedback compensation path bonding o Transceiver channel clocks o Native PHY FPGA-transceiver interface clocks o Non-Native PHY Quartus II-selected interface clocks o Non-Native PHY optional user-selected clocks o FPGA fabric-transceiver clocks o Reducing FPGA-transceiver interface clock usage o FPGA clocking for 10G PCS channels o Channel placement guidelines o Non-bonded channel placement restrictions o Bonded channel placement restrictions o Channel merging Planning Reset Control o Reset solutions review o PHY IP core reset solutions o Which reset controller is right for me? o Using the reset controller IP o Using the embedded reset controller Planning Transceiver Reconfiguration o How many controllers should I have? o mgmt_clk_clk requirements o Connection considerations o Example valid connections o Example invalid connection o Designing reset logic with reconfiguration PHY IP Versions

7 Pin Connection Guidelines o Pin connection example (RREF pin) Lab #3: Implementing Transceiver Design Best Practices