Asynchronous Communication Mechanisms (ACMs) EECE, Newcastle University

Transcription

1 Asynchronous Communication Mechanisms (ACMs) Fei Xia EECE, Newcastle University

2 Data communication between two asynchronous processes Point to point connection writer data reader Data is a stream of items of a set type. Writer and reader are cyclic processes. Writer provides one item of data per cycle. Reader uses one item per cycle.

3 Synchronization Simple approach writer reader a t b

4 ACMs An ACM divides temporal domains writer ACM reader writer timing domain reader timing domain temporal divide

5 ACM model writer data ACM Control variables Shared memory reader data The shared memory is organized as a set of n cells A cell is a memory location that can store one data item Each process has its own set of control variables Each process updates its own control variables A process can only read the value of a control variable of another process Concurrent processes executing on different timing domains 1-bit control variables Does not require any synchronization primitives Order of execution does not interfere on the correctness of the result

6 History Atomic register [Lamport 86] The problem of asynchronous communication can be solved using shared registers Complex registers are built from simple ones ACMs [Simpson 87-03] Defined a fully ACM that preserves data-coherence with 4 slots Classification of ACMs Systematic synthesis of ACMs [Yakovlev Group 96-08] ACMs are modelled using MATLAB for use in higher level systems Automatic synthesis of ACMs [Gorgônio, Xia 05-08] State space generation (BFS based) Petri net synthesis using theory of regions Modular approach using Petri nets modules as building blocks Modelling and verification using CPN

7 ACM classification No overwriting Overwriting No re-readingreading BB OWBB Re-reading RRBB OWRRBB Overwriting enables the writer to be fully asynchronous Rereading enables the reader to be fully asynchronous BB stands for bounded buffer

8 ACMs with buffering Writer ACM Reader Control variables data enough memory to contain an arbitrary number of items Shared memory data

9 Buffering C 0 C n-1 C 1 C 2 n cells in a ring

10 Implementation example RRBB with three cells from an interleaving specification s0 wr2 s1 wr0 (wr wait) wr2 wr0 wr1 (wr wait) wr0 wr1 wr2 (wr wait) wr1 wr2 s0 rereading waiting s1 cyclic

11 RRBB Adding silent actions s0 s1 µ11 µ01 wr2 wr2 µ11 µ01 λ 20 λ 20 wr0 wr0 λ: writer silent actions; µ: reader silent actions µ12 wr0 µ12 λ 01 wr1 prepare to reread µ22 wr0 µ22 λ 01 wr1 µ20 wr1 µ20 λ 12 wr2 µ00 µ00 wr1 λ 12 wr2 s0 s1

12 µ11 RRBB synthesis µ01 s0 wr2 µ11 µ01 s1 λ 20 λ 20 wr2 20 µ12 wr0 wr0 wr0 µ12 λ 01 wr1 var w: 0..n-1; r: 0..n-1; initialized sensibly (say r=w-1) and initialize data items in the cells. writer wr: write cell w; ww: wait until r w+1; reader r0: if (r+1 mod n) w then r:=(r+1 mod n); w0: w:=(w+1 mod n); rd: read cell r; µ22 µ22 wr0 λ 01 wr1 µ20 wr1 µ20 λ 12 wr2 µ00 µ00 wr1 λ 12 wr2 s0 s1

13 RRBB modular design Writer ACM cell i w and r Reader data advance Writer cell memory ACM cell i+1 w and r data advance Reader data cell memory data

14 Modular design algorithm var w: 0..1; r: 0..1; initialized sensibly (one cell has w=1 and another has r=1, all others being 0) and initialize data in the cells. Writer Reader wr: write; r0: if wnext=0 then w0: w:=0; wnext:=1; begin r:=0; rnext:=1; ww: wait until rnext=0; wa: advance to next; advance to next end rd: read;

15 Overwriting Needs more than one slot per cell This will allow the writer to overtake the reader if overwriting the oldest item in the buffer Item to be overwritten can be Oldest in the buffer Newest in the buffer Some other item (does not make as much sense as the previous choices) Also has to do with if the ACM is organized as a FIFO, a stack or a random bag

16 3-Cell OWRRBB µ0001 w11 µ 0001 λ 1100 w00 λ 0011 λ 1100 w11 µ 0101 r0 01 w11 µ0101 µ r0 01 λ 1100 r0 01 w00 r0 01 r0 01 λ 1100 λ 0011 w11 r0 01 µ0111 w00 µ0111 λ 0010 µ0100 w11 µ0100 λ 1101 µ1111 r11 µ1111 r11 w00 λ 0010 µ0000 r00 w11 µ0000 r00 λ 1101

17 3-cell OWRRBB writer Control variables slot 0 cell 0 cell 1 cell 2 x 00 x 10 x 20 data reader slot 1 x 01 One-hot enconding (1-bit variable) Control variables

18 Modular OWRRBB algorithm var w: 0..1; r: 0..1; over: 0..1 (this cell is overwritten); release: 0..1 (writer releases cell for reader); Writer Reader w0: overnext:=0; r0: if over=1 then if w r then over:=1; w=(not)r; wr: write slot w; begin over:=0; advance to next end r:=w; wa: release:=1; rd: read slot r; releasenext:=0; advance to next; ra: if releasenext=1 then advance to next

19 Automatic synthesis

20 Acknowledgements Alex Yakovlev Hugo Simpson Ian Clark Eric Campbell Jordi Cortadella Kyller Gorgonio