2D Recognition and Tracking

Transcription

1 2D Recognition and Tracking 1 Theme: 2 Subject: List of Abbreviations AR Augmented Reality 6 DoF Six Degrees of Freedom 3 Background When you think of AR, one of the key elements to consider is 2D recognition and tracking technology. This term refers to an ability to identify the 2D images and their position in space caught by the device s camera. AR is the enhancement of the view of the real world with CG overlays such as graphics, text, videos or sounds, and across all AR applications. Most of these apps use 2D images to trigger pre-defined 3D visualization, animation, video, or soundtrack. In other words, they use 2D recognition and tracking to determine what relevant information should be added to the real world. It means that 2D recognition and tracking plays an essential role in the field of augmented reality. 4 Scope 2D Recognition and Tracking When the target image appears in the camera, the image can be recognized and its pose (6 DoF) can be known. After recognition, the image can be tracked and its pose (6 DoF) can be updated during the image moving. 1 / 4

2 5 Expected Outcome and Deliverables The source code of 2D recognition and tracking software, and it can be used on the Huawei mobile phone; The source code of 2D image preprocess software (if it is needed), and it can be used on the Huawei mobile phone and PC; The document of the software s API, and the Demo, based on the Huawei mobile phone, is needed; The copyright of source codes in 2D recognition and tracking software and 2D image preprocess software should belong to Huawei. 6 Acceptance Criteria 1) On-device 2D recognition and tracking result should be stable, and the recognition time should below 1 second; 2) Recognition accuracy is at 90%; 3) Recognition works up to 5% of screen area; 4) Positional error as good as 0,25% of image size; 5) Angle at which target image can be tracked is 150 (± 75 ); 6) Sideways (constant linear) movement for tracking is 0.38 m/s; 7) Rotation (constant) movement for tracking is 180 /s. 8) When using FullHD (1080p) camera image to recognize and track, the usage of the CPU (Kirin 970) should be below 15%. In the processing, only the recognizing and tracking is tested not including the rendering. The specific device will be Mate 10 (CPU: 4*Cortex-A GHz + 4*Cortex-A53 1.8GHz, RAM: 6GB). 2 / 4

3 7 Phased Project Plan HIRP OPEN 2018 T is denoted as the starting time of the project. Phase1 (from T to T + 3 month): Finish basic 2D recognition and tracking function software; Deliverables are the source code of 2D recognition and tracking software, the source code of 2D image preprocess software, the document of the software s API and the Demo. Phase2 (from T + 3 month to T + 5 month): Optimize the performance of 2D recognition and tracking software; Deliverables are the new version of 2D recognition and tracking software, the source code of 2D image preprocess software, the document of the software s API and the Demo; Optimization should reach the 6 Acceptance Criteria from 1) to 7). Phase3 (from T + 5 month to T + 6 month): Optimize the CPU usage of the 2D recognition and tracking software; Deliverables are the final version of 2D recognition and tracking software, the source code of 2D image preprocess software, the document of the software s API and the Demo; Optimization should reach the 6 Acceptance Criteria in 8). 3 / 4

4 Copyright Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 4 / 4

5 Project name: Architecture and/or Compiler for Deep Learning 1 Theme: 2 Subject: Computer Architecture List of Abbreviations NPU Neural Processing Unit CNN Convolutional Neural Network ASIC Application Specific Integrated Circuit FPGA Field Programmable Gate Array GPU Graphic Processing Unit EDA Electronic Design Automation 3 Background Deep learning has become ubiquitous and indispensable. To fulfill the high computation demand in deep learning, specialized architectures are proposed, such as the DianNao series and MIT Eyeriss accelerators. An example of this innovation in industry is the NPU in Huawei Kirin 970 processor. The design of deep learning architecture requires multi-objective optimization maximizing accuracy, speed, reliability, energy efficiency and also the software tool-chain support, flexibility in application. 1 / 4

6 Furthermore, there is a rising need for compiler technology for deep learning systems, to compile the front-end framework workloads directly to hardware backends, for supporting the custom processor, or various hardware backends e.g. GPU. Generally speaking, both architecture research and compiler research proposals for deep learning are welcomed. 4 Scope Deep learning architecture Investigate the architecture for deep learning acceleration (e.g. CNN, neuromorphic). The realization platform and style are not restricted. It can be specialized datapath, many-core processor, etc. in ASIC, FPGA or EDA simulation. Compiler for deep learning systems Deploying front-end deep learning framework workloads (e.g. Caffe, Tensorflow) to the hardware back-end, e.g. scheduling the deep learning accelerator and do optimization of the instructions. 5 Expected Outcome and Deliverables Technical reports for deep learning architecture and/or compiler for deep learning systems; Source codes, scripts, other design files and descriptions; Discussions including Face-to-face and/or online conference calls; 1 Invention/patents depending on the characteristic of the detailed research topic; 2 / 4

7 6 Acceptance Criteria HIRP OPEN 2018 Realization of the design in accepted language or format (e.g. C++/Python/Verilog/layout etc.) and demonstration of the idea in computer simulation. 7 Phased Project Plan Phase1 (~3 months): Survey the state of the art, and provide the technical plan of the research work. Phase2 (~6 months): Technical research / development / test of the design. Provide the technical report. Phase3 (~3 months): To apply for the patent and summarize the research work. To provide all the technical materials. 3 / 4

8 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 4 / 4

9 Conversion of Artificial Neural Networks to Spiking Neural Networks 1. Theme: 2. Subject: Brain-Inspired Computing List of Abbreviations: ANN Artificial Neural Networks DNN Deep Neural Networks CNN Convolutional Neural Networks SNN Spiking Neural Networks 3. Background In recent years, spiking deep neural networks have become an increasingly active field of research. This has been driven both by the interest to build more biologically realistic neural network models, and by recent improvements and the availability of larger-scale neuromorphic computing platforms, which are optimized for emulating brain-like spike-based computation in dedicated analog or digital hardware. Neuromorphic platforms can be orders of magnitude more efficient in terms of power consumption compared to conventional CPUs or GPUs for running spiking networks, and often permit distributed and asynchronous event-based computation, thereby improving scalability and reducing latencies. Furthermore, event-driven

10 neuromorphic systems focus their computational effort on currently active parts of the network, effectively saving power on the rest of the network. Training of spiking deep networks typically does not use spike-based learning rules, but instead starts from a conventional ANN, fully trained with backpropagation, followed by a conversion of the rate-based model into a model consisting of simple spiking neurons. Theory has shown that SNNs are at least as computationally powerful as their analog counterparts, but practically it has proven difficult to come up with equivalent solutions. One approach used by O Connor(2013) for example is to train spiking DBNs by using the Siegert mean-firing-rate approximation of leaky integrate-and-fire (LIF) neurons to approximate probabilities during training. Another approach used by Perez- Carrasco(2013) requires tuning of parameters such as leak and refractory period in the spiking network. In both cases, the spiking network suffers from considerable losses in classification accuracy, when compared to a non-spiking network of similar architecture. Therefore, we look for a new method which could convert any ANN to a SNN architecture, so that on the one hand it can maintain the accuracy and on the other hand computationally much more efficient than ANN. 4. Scope 1) Research on methodology: Investigate the state-of-the-art research on conversion from ANN to SNN; propose a novel method which has high accuracy and low energy-consuming. 2) Research on application: Investigate the scenarios which the aforementioned SNN architecture could show outstanding advantages. Do the experiments on simulation platform or on real scenarios. 5. Expected Outcome and Deliverables

11 At least one novel conversion algorithm is proposed and tested. 1-2 published papers in the top-tier (CCF-A, B) journals and conferences. 1-2 patents, need to pass Huawei s review. Regular meeting and notes (once per month). 6. Phased Project Plan Phase1 (~T+3 months): investigate the state-of-the-art conversion from ANN to SNN. Phase2 (~T+9 months): propose the new method and algorithm, do experiments based on real applications, show competitive performance in MNIST or CIFAR-10 (higher accuracy and lower energy consuming) Phase 3 (~T +12 months): experiments on deep network (e.g. Resnet18-SSD), show competitive performance. Experiments on SNN chips

12 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects

13 Distributed parallel modelling of the simulation model based on C/C++ 1 Theme: 2 Subject: Simulation Model 3 Background Even with today s high speed processors, it is common for simulation jobs to take hours, days, even weeks, to complete. To overcome the speed limitation of the processors, parallel or distributed computation over multiple servers is required. That is, the simulation model is divided into several parts, and each part is simulated on one of the servers. In this way, a speedup proportional to the number of servers can be achieved. 4 Expected Outcome and Deliverables 1. An accurate, reliable distributed parallel framework which encapsulates the task of distributing a simulation model over several partitions (servers), and handles messaging between these partitions (servers). The framework provides a speedup proportional to the number of servers used. 2. The source codes and the algorithms for the partition, communications and synchronization between different servers. 3. Technical report which gives a full description of the above distributed parallel framework; 5 Acceptance Criteria An accurate, reliable distributed parallel framework which encapsulates the task of distributing a simulation model over several partitions (servers), and handles messaging between these partitions (servers). The framework provides a speedup proportional to the number of servers used. The distributed parallel framework needs to be tested and 1 / 3

14 approved by the expert team 6 Phased Project Plan Phase1 (T~T+2 months): The analysis of technology status. Phase2 (T+3~T+7 months): Provide the corresponding technical analysis report and detailed design proposal. Phase3 (T+8~T+12 months): The simulation and results verification. 2 / 3

15 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 3 / 3

16 Improving Utilization Rate of GPUs Cores for Multi-stages Task Applications 1 Theme: 2 Subject: Heterogeneous Computing List of Abbreviations NA 3 Background GPUs are now widely used in applications driven by deep learning technology, such as video & image processing. GPUs play the role of the workhorse of modern AI. However, GPUs are not fully utilized and the utilization rate usually are lower than 60% in most cases. The low utilization rate of GPUs are mainly caused by two aspects: one is due to the limitation of hardware structure of Nvidia, releasing few controllability to programmers; the other factor is the characteristic of tasks itself, such as task granularity, data dependence and etc., which stall multi-stages task or multi-tasks to concurrently execute on GPU efficiently. Bo Wu[1] proposed and developed FLEP, a software system that enables flexible kernel preemption and kernel scheduling on commodity GPUs. A versatile programming framework for pipelined computing on GPU was developed by Jidong Zhai etc[2],. Their works are aiming to impose more controllability on GPU kernel execution, and improve utilization of GPU cores and resources. However, how to bypass the hardware limitations of Nvidia GPU and alleviate the task granularity and data dependence burden on task concurrent execution to improve GPUs utilization, is still a novel and tough research topic in the fields of accelerating applications, such as video analyzing and image retrieval. 1 / 4

17 4 Scope 1) Research on GPU resource management on CPU+GPU heterogeneous programming model: investigate efficiency GPU memory management methods on heterogeneous programming model; 2)Research on GPU Task schedule management on CPU+GPU heterogeneous programming model: investigate how to schedule GPU kernels to execute concurrently and reduce waiting time caused by implicit synchronize, task granularity and data dependence, to achieve higher utilization; 3)Research on efficiency solution design: based on 1) and 2), design one or more efficiency solutions to resolve the low utilization of GPU for most applications on heterogeneous programming model, especially for kernelized correlation filters(kcf) algorithm for object tracking in video analyzing application. 5 Expected Outcome and Deliverables Technical reports of efficiency GPU memory management methods on heterogeneous programming model; Technical reports of scheduling GPU kernels to execute concurrently, such as persistent threads programming model,gpu preemption model and GPU pipeline programming model and etc., including theoretical optimal system parameters analysis; Efficiency solutions for GPU utilization with source codes and description; 1~2 Invention/patents; 6 Acceptance Criteria Project proposal is accepted by the evaluation team, Huawei. Project deliverables are accepted by the evaluation team, Huawei. 2 / 4

18 GPU utilization rate > 95% for KCF algorithms. 7 Phased Project Plan Phase1 (~3 months): Survey the state of the art of GPU memory management methods, as well as GPU kernels concurrent scheduling methods. Analyze and provide the related technical reports. Phase2 (~5 months): Research on solution design based on 1) and 2), provide the state of the art solution to achieve higher GPU utilization rate in kinds of typical scenarios and provide the related technical report. Phase3 (~4 months): Evaluation on solutions with real scenario provided by Huawei, provide related algorithms, code, simulation results and patents. Reference: [1] Wu B, Liu X, Zhou X, et al. FLEP: Enabling flexible and efficient preemption on GPUs[C]//Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, 2017: [2] Zheng Z, Oh C, Zhai J, et al. Versapipe: a versatile programming framework for pipelined computing on GPU[C]//Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture. ACM, 2017: / 4

19 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 4 / 4

20 Key Technical Progresses and Challenges of Topological Quantum Computing 1. Theme: 2. Subject: Topological Quantum Computing 3. Background Quantum Computing is the art of controlling and exploiting the time evolution of highly complex, entangled quantum states of physical hardware registers for the purpose of computing and simulation. It has already been shown that difficult problems such as factorization of numbers can be efficiently solved using a quantum computer. Topological quantum computing is a potential for Quantum Computers in future. A topological quantum computer is a theoretical quantum computer that employs two-dimensional quasiparticles called anyons, whose world lines pass around one another to form braids in a three-dimensional space time (i.e., one temporal plus two spatial dimensions). These braids form the logic gates that make up the computer. The advantage of a quantum computer based on quantum braids over using trapped quantum particles is that the former is much more stable. Small, cumulative perturbations can cause quantum states to decohere and introduce errors in the computing, but such small perturbations do not change the braids' topological properties. While the elements of a topological quantum computer originate in a purely mathematical realm, experiments in fractional quantum Hall systems indicate these elements may be created in the real world using semiconductors made of gallium arsenide at a temperature of near absolute zero and subjected to strong magnetic fields. This project will be dedicated to acquiring knowledge and opinions on the state-of-the-art of topological quantum computing, especially, the 华为保密信息, 未经授权禁止扩散第 1 页, 共 3 页

21 experimental feasibility of some up-to-date theoretical and technical proposals. 4. Scope The project involves analyzing and integrating information about topological quantum computing in areas including, but not limited to, the following: the basic theory of topological quantum computing, the up-to-date progress, the partner s research results, the breakthrough technologies and future trend. 5. Expected Outcome and Deliverables Survey reports about up-to-date progress of topological quantum computing; Survey reports of state of the art of technical proposal and experimental feasibility analysis Reports of partner s research results and future trend analyzation At least 6 seminar courses on the field of topological quantum computing, and a workshop 6. Acceptance Criteria Tutorial courses/survey reports/conference paper to be reviewed and accepted by assigned acceptance team. 7. Phased Project Plan Phase1 (~6 months): Integrate the theory of topological quantum computing, and give 6 seminar courses. Survey the state of the art of proposals, including the physical materials, experimental methods, etc. Phase2 (~4 months): Report the partner s research results on the field of topological quantum computing. Phase3 (~2 months): Hold a workshop on the field of topological quantum computing. Survey the state of the art of technical development and future trend. Analyze experiment feasibilities of theoretic and technical proposals 华为保密信息, 未经授权禁止扩散第 2 页, 共 3 页

22 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects 华为保密信息, 未经授权禁止扩散第 3 页, 共 3 页

23 Location technology research for Underground Parking 1 Theme: 2 Subject: Indoor location system List of Abbreviations RSSI Received Signal Strength Indication UWB Ultra-wideband RFID Radio Frequency Identification Slam Simultaneous location and mapping 3 Background Location technology is an important research point for autonomous driving. Accurate location algorithm can provide a robust and reliable location for path planning & control algorithms. The indoor location technology, combined with high-definition maps in the scenarios of park or basement park lots, solves the problems of Where I am and Where to go. At present, indoor location technology is divided into two aspects. One is independent of infrastructure, based on vehicle s sensors for location, such as laser Slam, visual Slam, inertial odometer, etc.; the other is relying on infrastructure, using RSSI or fingerprint and other information for location, such as RFID, ultra-wideband technology (UWB), Wi-Fi and Bluetooth, etc. The former is less robust to dynamic environments or related to environment such as lighting. For an underground parking lot with less characteristics it is difficult to build the feature maps; the latter is depending on the 1 / 4

24 deployment of the infrastructure, whose location accuracy is higher and the robustness is stronger. However, it s difficult to deploy the infrastructure widely caused by the high cost. One hand, driverless cars are equipped with sensors such as cameras, ultrasonic sensors, millimeter-wave radars and laser radar. It is easy to get rich environmental information for indoor location. On the other hand, infrastructure costs, proper deployment and algorithms have greatly improved for indoor location accuracy and robustness. Therefore, it is the time to start the application research of the indoor location technology for autonomous driving. 4 Scope Vehicle-based location scheme Investigate the advantages and disadvantages of various indoor location solutions based on in-vehicle sensors, such as laser radar location, visual location, and ultrasonic location; Investigate location schemes based on V2I, such as UWB, RFID, and other location solutions. Evaluate the advantages and disadvantages of the above solutions; Compare multiple location schemes, and determine the project's location scheme accordingly. Indoor location implementation Based on the above location scheme, on the condition of that vehicle sensors and infrastructure are installed, algorithm development is carried out to achieve basic vehicle location accuracy. 5 Expected Outcome and Deliverables Investigation report of Vehicle-based indoor location; Indoor location algorithm design instructions; Indoor location demonstration with source code; 1~2 inventions. 2 / 4

25 6 Acceptance Criteria HIRP OPEN 2018 The algorithm accuracy and robustness of indoor location algorithm meets centimeter-level or decimeter-level, and should be enough for path planning. 7 Phased Project Plan Phase1 (~3 months): Complete investigation work on relevant location solutions and finish basic design instructions manual. Phase2 (~6 months): Simulate basic program of algorithm, and output basic simulation instruction description; finish the basic hardware deployment solution with experimental reports; Phase3 (~3 months): Implement the location algorithm on Huawei s vehicle on the scenarios of underground parking lots. 3 / 4

26 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 4 / 4

27 Methodology and Framework for Automated Dependable Software Design and Implementation in Edge Computing and Embedded Systems 1 Theme: 2 Subject: Methodology and Framework List of Abbreviations MEC Multi-access Edge Computing 3 Background Nowadays, edge computing and modern embedded computing systems become more and more relevant when IoT and 5G/MEC connect physical world and digital world together. And emergent applications in IoT and 5G/MEC become more and more complex and expand to a much larger scale. In these applications, unpredictable events may occur in real-time and must be reacted upon in real-time too. In addition, the interactions between these systems/ applications and the physical world are more intricate. These changes make the correctness of these applications much more difficult to assure than before, since their complexities grow exponentially with the scale of the system. Traditional verification/validation methods/programming paradigms seem to produce high development cost. So, the foremost common question of these applications is how to assure their correctness to meet criticality requirement of certain levels with minimum cost. We believe that automating the building process of a trustworthy system is a promising direction. 4 Scope We are seeking proposals to a methodology and corresponding software framework for this automated building process of a trustworthy system problem in Edge Computing and next 1 / 4

28 generation Embedded Computing systems. The methodology and framework should confront following issues: 1. Flexible customization and composable service in edge/embedded computing 2. Automated end-to-end application lifecycle management in edge/embedded computing 3. Automated Software Optimization in edge/embedded computing 4. Dependability and Safety in edge/embedded computing 5 Expected Outcome and Deliverables We expect the outcome and deliverables as following: 1. Methodology, Theoretical Model and Framework: we need a methodology, theoretical model and corresponding software framework that could be used in IoT, 5G/MEC, video surveillance and other edge computing scenarios in which the openness of embedded system is one of the major concerns. The framework should support Huawei hardware/software platforms; 2. Embedded Domain Knowledge Base/Expertise System: a) Framework/toolsets to build embedded domain knowledge base/expertise system b) Auto-optimization technologies for embedded software 3. Transparent application deployment: technologies to enable transparent application deployment disregarding whether it is deployed on edge or in cloud 6 Acceptance Criteria 1. Methodology, Theoretical Model and Framework: a) A well-defined methodology and theoretical models that could pass Huawei review b) A framework that could be run a demo on an environment agreed by both parties and pass Huawei review 2 / 4

29 2. Embedded Domain Knowledge Base/Expertise System: a) A framework/toolsets that could be run a demo on an environment agreed by both parties and pass Huawei review b) Auto-optimization technologies for embedded software should show its advantages in a demo run on an environment agreed by both parties and pass Huawei review 3. Transparent application deployment: should show its advantages in a demo run on an environment agreed by both parties and pass Huawei review 7 Phased Project Plan Phase No. Phase description Time( months) Main task content Output Standard that should achieve 1 Design and review of proposal. 2~4 Proposal is accepted and approved by Huawei. Investigation Report Design documents of proposal. 2 Implementation and Delivery 6 or more Document preparation, software implementation and delivery Documents, implementations that could meet above acceptance criteria 3 / 4

30 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 4 / 4

31 Performance optimization method for quantum circuit simulator 1 Theme: 2 Subject: Quantum Computing List of Abbreviations N/A 3 Background Before we have mature and easy-to-access quantum computing chips, quantum circuit simulator is very quantum computer research, for quantum software, algorithm, hardware and architecture development and verification. It also could be useful for classical computer simulation of material / chemical / drug quantum system. It is also the foundation of quantum algorithm and quantum software research. The main challenge for quantum circuit simulation is that memory resources and communication overhead are increasing exponentially with the number of qubits. This is also the original motivation for quantum computer. This project is to develop optimization techniques of quantum simulator in the case of maximum entanglement, and supports the simulation of 50 qubits circuit system and algorithms based on high performance server cluster. 4 Scope Distributed shared memory technology Distributed shared memory technology and algorithm for large scale matrix vector multiplication in quantum circuit simulation. The memory overhead is reduced by more than 5 times while the communication overhead is not significantly larger, or more than 5 times faster. Distributed communication technology 1 / 4

32 Distributed communication optimization technology for large scale matrix vector multiplication in quantum circuit simulation: The communication efficiency is increased by more than 3 times on the premise that the memory cost is not significantly increased. Physical qubit simulation Support physical qubits, noise and error correction protocol simulation. Other Optimization methods such as qubits scheduling and mapping. 5 Expected Outcome and Deliverables Investigation and performance analysis report on Simulator. Document and source code on distributed shared memory and communication optimization technology for quantum circuit simulation. Design document and code supporting noise and error correction protocol simulation. 1-2 papers. 1-2 patents 6 Acceptance Criteria The report and design document pass Huawei review; The paper is submitted to conference or periodical review. The patent idea pass huawei review. Improvement of existing method should be better than the known one, new method should have some innovative features. Methods should be verified on some simulator or theoretically proved. 7 Phased Project Plan Phase1 (~T+3 months): A survey on the quantum circuit simulators and perform a bottleneck analysis. 2 / 4

33 Phase1 (~T+6 months): The design document on distributed shared memory and communication algorithms supporting 50 qubits. The design document on physical qubits (simulator for noise and error correction protocol) simulator. One patent pass review. Phase2 (~T+9 months): Implementation of distributed simulator, the first version of the physical qubit simulator. Phase 3 (~T +12 months): Optimize algorithms and final version of code, submitting 1 papers (CCF B or mainstream quantum related conference), one more patents. 3 / 4

34 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 4 / 4

35 Quantum Error Correction Method Research 1 Theme: 2 Subject: Quantum Computing List of Abbreviations N/A 3 Background & Scope Recently, big progress has been made in quantum computing chip. 100+qubits chips are on the way. But the quantum volume of such quantum computer is heavily restricted by noisy and gate error. Quantum error correction is key to universal fault tolerant quantum computer. Quantum error correction is an important research topic from the beginning of quantum information processing research. And many new codes, techniques, methodologies have been developed. The goal of this project is to support innovative research on quantum error correction, with considering the hardware progress, noisy intermediate-scale quantum computer in near future and fault-tolerant large scale quantum computer and algorithms. 4 Expected Outcome and Deliverables Survey report and trend analysis on quantum error correction research. Design document and source code on new quantum error correction code. 1-2 papers. 1-2 patents. 5 Acceptance Criteria The report and design document pass Huawei review; The paper is submitted to conference or periodical review. The patent idea pass huawei review. 1 / 3

36 Improvement of existing method should be better than known method, new method should have some innovative features. Method should be verified on some simulator or real quantum computer platform, or theoretically proved. 6 Phased Project Plan Phase1 (~T+3 months): Survey and analysis of quantum error correction research and development. Phase1 (~T+6 months): One new quantum error correction method and one patent idea. Phase2 (~T+9 months): Quantum error correction source code and test report, one paper draft. Phase 3 (~T +12 months): Final design and test report, source code. One more patent idea. 2 / 3

37 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 3 / 3

38 Quantum logic circuit optimization techniques 1 Theme: 2 Subject: Quantum Computing List of Abbreviations N/A 3 Background The quantum volume of current and near future quantum computer hardware are very limited by both qubits number and noise; how to make full use of quantum hardware resource as much as possible, to achieve efficient and large scale quantum algorithms, is an important and challenge research topic. Quantum algorithm and program is compiled into quantum logic circuit (Assembly instruction sequence), then logic circuit is implemented on physical chip. For the same quantum algorithm, there may be several different equivalent logic circuits. Intermediate representation algorithms are important to reduce the number of gate operations in logic circuit. 4 Scope Develop efficient quantum circuit optimization methods and improving related compiler optimizer. The goal is to reduce the quantum logic gates number by 50% on average. We recommend to implement the optimization method in open source quantum programming framework ProjectQ. 5 Expected Outcome and Deliverables Technical reports of optimizing quantum logic circuit. The algorithm design document and the implementation code (Based on ProjectQ), compared with the existing quantum compiler, the performance is raised by more than 50%. 1 / 3

39 1-2 papers. 1-2 patents. 6 Acceptance Criteria The report and design document pass Huawei review. The methods and related source code pass testing and meets the performance and functional requirements. The paper is submitted to the conference or periodical review. The patent idea pass Huawei review. 7 Phased Project Plan Phase1 (~T+3 months): Investigates techniques for the automated optimization of quantum logic circuit. Phase1 (~T+6 months): Implement an existing method for optimizing quantum logic circuit. A new idea of quantum logic circuit optimization. Phase2 (~T+9 months): Code and test report for optimizing quantum logic circuit, submit a paper. Phase 3 (~T +12 months): The design document and the final version of the code, submit one paper (CCF B or the mainstream quantum related conference), and one patent. 2 / 3

40 Copyright(C)Huawei Technologies Co., Ltd All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of Huawei Technologies Co., Ltd. Trademarks and Permissions and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd. All other trademarks and trade names mentioned in this document are the property of their respective holders. Confidentiality All information in this document (including, but not limited to interface protocols, parameters, flowchart and formula) is the confidential information of Huawei Technologies Co., Ltd and its affiliates. Any and all recipient shall keep this document in confidence with the same degree of care as used for its own confidential information and shall not publish or disclose wholly or in part to any other party without Huawei Technologies Co., Ltd s prior written consent. Notice Unless otherwise agreed by Huawei Technologies Co., Ltd, all the information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute the warranty of any kind, express or implied. Distribution Without the written consent of Huawei Technologies Co., Ltd, this document cannot be distributed except for the purpose of Huawei Innovation R&D Projects and within those who have participated in Huawei Innovation R&D Projects. 3 / 3

41 Quantum machine learning algorithms 1 Theme: 2 Subject: Quantum Computing List of Abbreviations N/A 3 Background & Scope Quantum computer is in fast research progress. Many important progresses in quantum hardware have been made in recent years. Machine learning are one of the potential killer application for future quantum computer. We need machine learning quantum algorithms for such applications. Some progresses have been made in quantum machine learning algorithms development. But it is still far from practically useful quantum machine learning algorithms that can run one real quantum computer and produce practical results. The main goal of this project is to make innovative progress on some quantum machine learning algorithms. 4 Expected Outcome and Deliverables 2 innovative quantum algorithms for machine learning applications, source code implemented in opensource quantum simulator or public quantum cloud, algorithm design and description document; Survey report on quantum machine learning algorithms; 1~2 papers; 1~2 patents. 5 Acceptance Criteria The report and design document pass Huawei review; 1 / 3