Digital system (SoC) design for lowcomplexity. Hyun Kim
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1 Digital system (SoC) design for lowcomplexity multimedia processing Hyun Kim
2 SoC Design for Multimedia Systems Goal : Reducing computational complexity & power consumption of state-ofthe-art technologies based on multimedia and big-data Method : Speed-up and Low-power through HW acceleration & optimization Two ways for acceleration : GPU porting / Digital circuit design GPU porting Highly optimized for parallel data processing and matrix operations Various development frameworks for DNN Size & Cost & Power consumption problem! Digital Circuit (SoC) Design Implementation is more difficult than GPU but, Fast & Small & Cheap & Low power Comparison between GPU porting & FPGA design GPU (Tesla K40) Caffe + CuDNN FPGA (Virtex 7 485T) Microsoft Catapult project 2015 Power 235W ~25W FPGA design consumes about one tenth of power compared to GPU porting High flexibility to apply various optimization techniques More than x100 speed-up can be achieved by various schemes Digital circuit design is the best option for acceleration and optimization!
3 Platform Multimedia Processing System on Chip (SoC) Platform All researches were performed on this platform and related to low-power HW acceleration & optimization Low-Power Video Recording System Battery-operated & Video Codec Embedded compression Preprocessing Video Coding Standard Contribution 1: HW-based low-power video recording system with multiple video coding modules Contribution 2: Optimal combination of power scaling algorithms in HW-based video coding Contribution 3: Optimized selection of SRAM size for power reduction in HW-based video coding Contribution 4: Optimized HW implementation of DWT+SPIHT and its video quality optimization Contribution 5: Low-power HW-based video surveillance with early BG subtraction and adaptive FMC Contribution 6: HW design of real-time naturalness image enhancement based on Retinex
4 Low-Power Video Recording System Goal : Implement and optimize a HW-based low-power video recording system considering the trade-off between the performance and power consumption HW implementation Only for meaningful video data Always operating that will be stored for a long time Optimal operation scheme Camera input LWC Encoder Temp Mode LWC Decoder DRAM Perm Mode H.264 NAND FLASH Trade-off between performance & power consumption Front-end verification on FPGA board Contribution 1) HW Implementation for low-power VRS which achieves power saving up to 72.5% 2) Optimized power solution based on trade-off between power & performance Published in IEEE Transactions on Multimedia
5 Platform Multimedia Processing System on Chip Platform All researches were performed on this platform and related to low-power HW acceleration & optimization Preprocessing Video Coding Standard Contribution 1: HW-based low-power video recording system with multiple video coding modules Contribution 2: Optimal combination of power scaling algorithms in HW-based video coding Contribution 3: Optimized selection of SRAM size for power reduction in HW-based video coding Contribution 4: Optimized HW implementation of DWT+SPIHT and its video quality optimization Contribution 5: Low-power HW-based video surveillance with early BG subtraction and adaptive FMC Contribution 6: HW design of real-time naturalness image enhancement based on Retinex
6 Power-Scaling for Video Compression Goal : Find the optimal combination of low-power algorithms achieving best performance in the HW-based video encoder Flowchart Formulation for power estimation Trade-off between power consumption & performance Optimal Combination Selected Combination Power Saving(%) Power-level table for real-time application Candidate Combination Machine Learning Methodology Experimental results Contribution 1) Optimizing video coding standards based on trade-off between power & performance 2) HW Implementation of low-power video codec More than 2dB enhancement at 40% power saving Published in IEEE Transactions on VLSI
7 Optimized SRAM Size for Video Codec Goal : Decide optimal SRAM sizes for achieving best performance in HW-based video codec Flowchart Various SRAMs in video codec and their different sensitivities to error Formulation Optimal size Optimization Experimental results Contribution 1) Optimized SRAM size solution of HW-based video codec for minimizing the performance degradation considering trade-off between HW resource & performance Published in IEEE Journal on Emerging and Selected Topics in Circuits and Systems
8 Platform Multimedia Processing System on Chip Platform All researches were performed on this platform and related to low-power HW acceleration & optimization Embedded compression Preprocessing Contribution 1: HW-based low-power video recording system with multiple video coding modules Contribution 2: Optimal combination of power scaling algorithms in HW-based video coding Contribution 3: Optimized selection of SRAM size for power reduction in HW-based video coding Contribution 4: Optimized HW implementation of DWT+SPIHT and its video quality optimization Contribution 5: Low-power HW-based video surveillance with early BG subtraction and adaptive FMC Contribution 6: HW design of real-time naturalness image enhancement based on Retinex
9 Low-cost Hardware Design of 1D SPIHT Goal : Implement a low-cost HW-based embedded compression module (1-D DWT+SPIHT) Block diagram Experimental results Implementation schemes Partitioned SPIHT Bit-allocation Contribution 1) A low-cost HW design of a 1D DWT+SPIHT with partitioned SPIHT and bit allocation 2) Optimization considering the trade-off between HW resource and performance -Reduce HW gate count and memory by 59% and 75% with only a slight PSNR degradation Published in IEEE Transactions on Consumer Electronics
10 Optimized DWT and SPIHT Goal : Optimize the R-D performance of HW-based DWT+SPIHT modules Structure of1-d DWT and SPIHT Correlation analysis between DWT coeff. & loss Machine Learning Methodology Formulation and Optimization Optimal solution of compression ratio for each coding block Experimental Results Contribution Examples before/after applying the scheme 1) Optimizing the performance of DWT and SPIHT 2) Applying the proposed scheme to HW DWT+SPIHT Accepted in IEEE Transactions on Multimedia
11 Platform Multimedia Processing System on Chip Platform All researches were performed on this platform and related to low-power HW acceleration & optimization Preprocessing Contribution 1: HW-based low-power video recording system with multiple video coding modules Contribution 2: Optimal combination of power scaling algorithms in HW-based video coding Contribution 3: Optimized selection of SRAM size for power reduction in HW-based video coding Contribution 4: Optimized HW implementation of DWT+SPIHT and its video quality optimization Contribution 5: Low-power HW-based video surveillance with early BG subtraction and adaptive FMC Contribution 6: HW design of real-time naturalness image enhancement based on Retinex
12 Low-Power Video Surveillance System Goal : Implement low-power HW-based video surveillance with the highest power saving Inserting BG sub. into HW-based pipeline structure Flowchart of HW-based BG sub. using only the information generated during video compression Operation of coding standard in low-power video surveillance (MK C, MK P ) Classification MB CURR coding option IME option for MB NCO-LO (FG, FG) Strong FG Regular (FME & IP) Regular SR & BM (FG,BG) Object Boundary Only IP Regular SR & BM (BG,FG) Uncovered BG Only IP Regular SR & BM (BG,BG) Strong BG SKIP mode Small SR & BM BG sub. results Experimental results Contribution 1) Performing BG sub. w/o additional resources considering HW structure of video codec 2) Achieving best power savings with negligible PSNR degradation in video surveillance Published in IEEE Transactions on Consumer Electronics
13 Real-time HW Design for Retinex Goal : Implement Low-power/Real-time HW IP of Retinex algorithm Retinex algorithm - Pre-processing for improving the brightness of the image in the dark part of the input image - Emphasize reflection components by separating illumination component and reflection component - Require a large amount of computations Dark part : image compression efficiency and recognition accuracy are very low it is very important to improve the brightness of the image Block diagram Examples before/after applying Retinex FPGA implementation results -Implemented on ZC706 FPGA board -Achieving real-time operation (FHD 60fps) -20% LUT reduction and 53% FF reduction compared to previous design -No frame memory Low-power & Fast CES2018 demo Contribution 1) Real-time HW implementation of Retinex and resource optimization for HW design Exhibited at 2018 CES Submitted in IEEE Transactions on Consumer Electronics
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