Fast Fourier Transform Architectures: A Survey and State of the Art

Transcription

1 Fast Fourier Transform Architectures: A Survey and State of the Art 1 Anwar Bhasha Pattan, 2 Dr. M. Madhavi Latha 1 Research Scholar, Dept. of ECE, JNTUH, Hyderabad, India 2 Professor, Dept. of ECE, JNTUH, Hyderabad, India Abstract Fast Fourier Transform (FFT) algorithm is widely used in many signal processing and communication systems. Due to its intensive computational requirements, it occupies large area and consumes high power if implemented in hardware. Efficient algorithms are developed to improve its architecture. In this paper, a variety of available FFT algorithms are presented and then different architectures are outlined by exploring the techniques and algorithms involved in each of the architectures. The widely adopted architectures and trends in architectural modification to reduce power consumption and area and to achieve high throughput are discussed. Keywords Fast Fourier Transform (FFT), Architecture, Optimization, Throughput. I. Introduction Fast Fourier Transform (FFT) is an efficient method for computing Discrete Fourier Transform (DFT). The DFT of a signal time domain signal x(n) is given in equation (1). Where is called twiddle factor and it is a complex value. Direct computation of an N point DFT requires O(N 2 ) operations where as the FFT brings down the operations into O((N/2)log 2 N) [1]. FFT uses divide and conquer approach to reduce the computations. The idea of divide and conquer is to map the original problem into sub problems with the following relation: Cost (sub problems) + Cost (mapping) < Cost (original problem) [3] Depending on the way the full DFT is mapped into sub problems, the FFT algorithms are classified into two families: Cooley-Tukey and Prime Factor Algorithms (PFA). Cooley-Tukey mapping is the simplest mapping suitable for any number N if mixed radix method is employed, but the PFA is not suitable for any number because of the restriction that all the factors of N should be co-prime. So, PFA is used as the special FFT algorithm for numbers with coprime factors. Each type of algorithm is further classified based on other characteristics as it operates in-place or uses extra scratch memory, whether it uses decimation-in-time or decimation- infrequency, etc. In Cooley-Tukey radix-2 algorithm, the N point DFT is subdivided into two (N/2) point DFTs and then (N/2) point DFT is recursively divided into smaller DFTs until a two point DFT, whose butterfly is just an addition and a subtraction of input complex numbers. It is the best suitable algorithm for a number N, which is a power of 2. Higher radix algorithms such as radix-4, radix-8, etc can be 94 International Journal of Electronics & Communication Technology (1) employed to reduce the complex multiplications but the butterfly structure becomes complex with the multiple input complex adders. So, a new algorithm called split radix algorithm [2] is adopted to get the benefits of both radix-2 and radix-4 algorithms to achieve minimum complex multiplications by maintaining the simple butterfly structure. Prime Factor Algorithms use Good s mapping and Chinese Remainder Theorem for decomposing the N point DFT into smaller DFTs which are the factors of N and are mutually prime [3]. With this mapping the twiddle factor multiplications are avoided at a cost of increased number of additions and irregular structure, which is difficult to implement in hardware. A modification of PFA is Winograd fast Fourier Transform Algorithm (WFTA), which is the only method of finding DFT from convolution. It is capable of achieving minimum complex multiplications but the number of additions is increased. Other drawback of WFTA is that it does not allow in-place computations. So, auxiliary storage is required and its access which is comparable to arithmetic operations makes it less suitable for hardware implementation. Rest of the paper is organized as follows: In Section II, basic FFT architectures and comparison between the various pipelined architectures and also between memory based and SDF architectures are presented. The trends in architectural modifications for better optimization and state of the art FFT architectures are addressed in Section III followed by conclusion in Section IV. II. FFT Architectures There are four basic types of FFT architectures in the literature: 1. Memory based architectures 2. Cache memory architectures 3. Array architectures 4. Pipelined architectures 1. Memory Based Architectures FFT algorithms are mostly operated in stages where in each stage data read and write operations are performed by accessing memory [5]. The memory based architectures are classified into single memory architecture and dual memory architecture. In single memory architecture, the processing element is connected to a single memory unit of at least N words by a bidirectional bus as shown in fig. 1. Data exchanges are taken place between the processor (Proc) and memory at each stage using this bidirectional data bus. Fig. 2 shows the dual memory architecture, where two memories of size N each are connected to the processing element with two separate bidirectional data buses. Data inputs from one memory are passed through the processing element to another memory and vice versa till the transform is completed. Fig. 1: Single Memory Architecture

2 ISSN : (Online) ISSN : (Print) Fig. 2: Dual Memory Architecture Input data rate may not be equal to the FFT processor frequency, so the data inputs should go through three phases: input buffering, computation and output reordering. Data to be transformed is first stored in the input buffer till the N samples are collected. Then this memory is used as the computational memory, which is accessed by the processor. At the same time another memory block becomes the input buffer to store another set of input data. The processor takes some time to complete the computations and stores the intermediate data in computational memory. When the transform is completed, the computational memory serves as the output buffer. Memory based architectures for computing an N point radix-r FFT require ((N/r) log r N) memory accesses where r words are read from and written to memory at each access. The clock frequency should be log r (N/r) times the frequency of data inputs because only one processing element is handling the computations. 2. Cache Memory Architectures The cache memory architecture [5] shown in fig. 3 has a data cache at the processor to increase the speed of the memory access and the energy efficiency. It is similar to that of single memory architecture except the cache between the processor and main memory due to which data pre-fetching is possible. This kind of architecture is not widely adopted due to controller complexity and extra hardware. IJECT Vo l. 5, Is s u e 4, Oc t - De c Pipelined FFT Architectures Pipelined FFT architectures are fast and high throughput architectures with parallelism and pipelining [6, 10]. Even though the hardware complexity is high and less flexible compared to other architectures, they offer high throughput and energy efficient implementations. Here we present some commonly used pipelined architectures such as Multi-path Delay Commutator (MDC) and Single-path Delay Feedback (SDF). A. Multi-Path Delay Commutator In this kind of architectures, input sequence is first divided into multiple parallel data streams by commutator and then, butterfly operation followed by twiddle factor multiplication is performed with proper delays to each data stream. In radix-2 MDC (R2MDC), input data stream is divided into two parallel paths as shown in fig. 5 for N equal to 16. Totally, (log 2 N 1) complex multipliers, log 2 N butterfly units and (3N/2 2) delay buffers are required. All the butterfly units and multipliers can be utilized at 100% with proper input buffering. Fig. 6 shows the radix-4 MDC (R4MDC) architecture, in which four parallel streams are processed at once. A total of (3log 4 N 1) complex multipliers, log 4 N radix-4 butterfly units and (5N/2 4) words of memory is required. B. Single-Path Delay Feedback In single path delay feedback architectures, a single data stream goes through multiplier in every stage. The delay units are more efficiently utilized by sharing the same storage between the inputs and outputs of the butterfly. Radix-2 and Radix-4 SDF architectures are shown in fig. 7 and fig. 8 respectively. By careful observation of these architectures, it is evident that the utilization of multipliers and butterfly units are at 50% because they are bypassed for half of the time. Fig. 3: Cache Memory Architecture 3. Array Architectures In array architectures [8], a number of processing elements with local buffers are interconnected in a network fashion as shown in fig. 4 to carry out the FFT computations. These structures are also not widely adopted due to huge area requirements and other reasons. Fig. 5: Radix-2 Multipath Delay Commutator FFT Architecture Fig. 6: Radix-4 Multipath Delay Commutator FFT Architecture Fig. 4: Array Architecture Fig. 7: Radix-2 Single Path Delay Feedback FFT Architecture International Journal of Electronics & Communication Technology 95

3 access, random addressing is necessary. Memory based architecture needs to drive its clock log r (N/r) times the processor frequency to achieve the same performance as pipelined SDF architecture. So, pipelined architectures are preferred when performance and power are the main concern than the complexity. On the other hand memory based architectures are good choice where complexity is of main concern. Fig. 8: Radix-4 Single Path Delay Feedback FFT Architecture Table 1 shows the comparison of hardware requirements for the above pipelined architectures. SDF architectures have the minimum memory requirements due to efficient use of delay buffers. Higher Radix MDC architectures are not preferred because of their huge requirement of scheduling buffers whereas the higher radix SDF architectures are preferred because the number of complex multipliers is reduced, hardware utilization is enhanced and needs less memory. A careful implementation of higher radix processing elements is required because the complexity of adders may increase if not implemented by several cascaded radix-2 butterfly units. Table 1: Comparison of Pipelined FFT Architectures Table 2: Comparison Between Memory Based and Pipelined SDF FFT Architectures Among these architectures, memory based architectures and Pipelined architectures are widely adopted. Table 2 shows the comparison between pipelined SDF architecture and memory based architecture for radix-r N point FFT implementation. Both the architectures have almost the same storage requirements where in memory based architecture, main memory is partitioned into r banks for simultaneous access and in pipelined SDF, memory is distributed into log 2 N banks. Power consumption can be reduced in pipelined SDF architecture with efficient implementations of sequential buffers because of its sequential access whereas in memory based architecture, to achieve a conflict free memory 96 International Journal of Electronics & Communication Technology III. Trends and State of the Art Any single FFT algorithm itself is not the best suitable for all kinds of hardware platforms. So, for better optimization, a best suitable algorithm should be selected for given hardware. Low power consumption, less area, regularity in structure and high performance are the main concerns of FFT optimizations. In the literature, different FFT algorithms are adopted in different FFT architectures for achieving required goals in specific applications. Here, we present the current trends in FFT architectural optimization and state of the art. By employing in-place FFT algorithms and shared memory buffers, the memory usage in memory based architectures can be greatly reduced. In [7], a mixed radix algorithm is used with in-place computation strategy for conflict free memory access. In addition, the architecture consists of only one butterfly unit capable of performing a radix-4 operation or two radix-2 operations. With this architecture, the area, computational clock frequency and power consumptions are reduced. Recently, in the architecture presented in [9], the same in-place computation strategy is employed and a modified radix-2 algorithm to avoid redundant operations is adopted for real valued signals. This design uses two processing elements to achieve a very less computational clock frequency for FFT computations of 512 points and above. In [11], a pipelined R2SDF architecture is proposed with Static Random Access Memory (SRAM) replacing the shift registers for achieving low power and area. To achieve high performance, four parallel data paths are employed in the radix-2 4 SDF architecture designed for MIMO-OFDM systems [12]. The architecture presented in [13] for OFDM systems adopted the SDF style and different multipliers that forms an FFT structure without Read Only Memory (ROM) to achieve low power consumption compared to other architectures. A variable length pipelined MDC for MIMO- OFDM systems is proposed in [14]. In this design, the memory utilization rate is improved by simple memory scheduling for reordering the input and output bits for area reduction. In [15], an efficient modification for feed forward pipelined FFT architecture is proposed. The input data sequence is rearranged into two half word streams and the data commutator is modified to achieve half the number of adders. For normal order output streams a sequence converter is integrated in the last stage commutator to achieve the minimum overall buffer size. A novel pipelined FFT architecture capable of performing real valued FFT is proposed in [16]. This generic architecture is designed for processing four samples simultaneously and also it requires less memory. It is suitable for real time applications due to its high throughput. A radix-2k feed forward pipelined architecture, which is suitable for transforming any number N (a power of 2), for parallel processing of data samples is presented in [17]. These parallel samples can be arbitrarily selected depending on the required throughput. In [18], a new pipelined architecture for radix-2 3 and radix-2 4 algorithms for real valued FFT is proposed. This design uses folding methodology for datapath optimization and offers less complexity in terms of adders and delays. A 64 point radix-4 3 algorithm based pipelined FFT architecture for WLAN is proposed

4 ISSN : (Online) ISSN : (Print) in [19]. In this architecture, 4 input samples are taken in parallel and one of the four output samples are selectively produced. It has more hardware complexity than the traditional SDF and MDC architectures but reduces the computational clock frequency by 25% and hence the power consumption is reduced. Researchers have proposed different modifications to baseline architectures for optimizing the processing elements and delay buffers to achieve low power and high throughput. In memory based architectures, dual port SRAMs are used for increasing the speed and reducing the power consumption. To achieve high throughput and reduce the multiplication complexities in pipelined architectures, FFT algorithms with higher radices are adopted based on radix-2 k. With this approach the regularity of structure is maintained without increased complexity. IV. Conclusion Basic architectures for FFT implementations are explored and a comparison between the widely adopted architectures in terms of hardware complexity and scope of optimization is discussed. The trends in architectural optimization and various modifications to baseline architectures proposed in the literature are reviewed and the algorithms adopted for the state of the art architectures are also discussed. V. Acknowledgement We would like to thank Dr. M. B. Srinivas, Dean Admissions and Mr. Syed Ershad, Research Scholar, BITS Pilani, Hyderabad Campus, for their help and valuable suggestions. References [1] J. W. Cooley, J. Tukey, An algorithm for machine calculation of complex Fourier series, Math. Comput., vol. 19, pp , Apr [2] P. Duhamel, H. Hollmann, Split radix FFT algorithm, Electron. Lett., Vol. 20, No. 1, pp , Jan [3] P. Duhamel, M. Vetterli, Fast Fourier transforms: a tutorial review and a state of the art, Signal Process, Vol. 19, No. 4, pp , [4] Keshab K. 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Grajal, M. A. Sánchez, Oscar Gustafsson, Pipelined Radix-2k Feed forward FFT Architectures, IEEE Trans on VLSI systems, Vol. 21, No. 1, Jan 2013, pp [18] Manohar Ayinala, Keshab K. Parhi, FFT Architectures for Real-Valued Signals Based on Radix-23 and Radix-24 Algorithms, IEEE Trans. Circuits Syst. I, Vol. 60, No. 9, Sep 2013, pp [19] Kala S, Nalesh S, S K Nandy, Ranjani Narayan, Design of a Low Power 64 Point FFT Architecture for WLAN Applications, 2013 IEEE. Anwar Bhasha Pattan received his B.Tech degree in Electronics and Communication Engineering from Madina Engineering College, Kadapa, Andhra Pradesh, India, in 2004, the M.Tech degree in VLSI System Design from Annamacharya Institute of Technology and Sciences, Rajampet, Andhra Pradesh, India, in 2008, and pursuing Ph.D. degree in Low Power VLSI Design from Jawaharlal Nehru Technological University Hyderabad, Telangana, India from He was a Lecturer in department of ECE in QCET, Venkatachalam and MeRITS, Udayagiri, Andhra Pradesh, India in and respectively and Assistant Professor in Annamacharya Institute of Technology and Sciences, Rajampet in His research interests include Low Power VLSI Design, VLSI Arithmetic Circuits and VLSI Architectures. At present, He is engaged in Fast Fourier Transform Architectural Optimization. International Journal of Electronics & Communication Technology 97

5 Dr. M. Madhavi Latha obtained B. E (NU) in 1986, M. Tech (JNTU) in 1993 and the first internal Ph. D (JNTU) in She has more than 3 years of teaching experience in C. R. Polytechnic College, 4 years of Industrial experience in ECIL, Power Electronics, Midfield Steels Ltd., 19+ years of teaching experience in JNTUH, Hyderabad, India since 1994, where she is currently working as Professor of ECE and Director of Innovative Technologies. She established the first Digital Signal Processing Laboratory under AICTE- TAPTEC Project & also in support of Texas Instruments, Austin, USA and Analog Devices, USA. She has good rapport with Ni2 Designs, Cadence Design systems, Mentor Graphics, Synopsys Intl., Xilinx, Trident Tech Labs, VEDA IIT, AMD industries and NRSA, CDAC, DLRL and RCI organizations. She established the first Center for Excellence in VLSI & Embedded Systems Design (CVED) in ECE department and is the coordinator of CVED. Her research interests include Digital Image and Signal Processing, VLSI, Wavelet applications, Biomedical Signal Processing and CMOS Analog and Mixed Signal Design. 98 International Journal of Electronics & Communication Technology