FPGA Implementation of FFT Processor in Xilinx

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1 Volume-6, Issue-2, March-April 2016 International Journal of Engineering and Management Research Page Number: FPGA Implementation of FFT Processor in Xilinx Anup Tiwari 1, Dr. Samir Pandey 2 1 Research Scholar, Department of Electronics & Communication Engineering, Jharkhand Rai University, Ranchi, INDIA 2 Professor, Department of Mathematics, Jharkhand Rai University,Ranchi INDIA ABSTRACT Fast Fourier Transform is an essential data processing technique in communication systems and DSP systems. In this brief, we propose high speed and area efficient 64 point FFT processor using Vedic algorithm. To reduce computational complexity and area, we develop FFT architecture by devising a radix-4 algorithm and optimizing the realization by Vedic algorithm. Furthermore, it can be used in decimation in frequency (DIF) and decimation in time (DIT) decompositions. Moreover, the design can achieve very high speed, which makes them suitable for the most demanding applications of FFT. Indeed, the proposed radix-4 Vedic algorithm based architecture requires fewer hardware resources. The synthesis results are same as that of theoretical analysis and it is observed that more than 15% reduction can be achieved in terms of slices count. In addition, the dynamic power consumption can be reduced and speed can be increased by as much as 16% using Vedic algorithm. Keywords - FFT, Vedic algorithm, DSP, radix-4 I. INTRODUCTION With the advancement of VLSI, Fast Fourier Transform (FFT) is applied to wide field of digital signal processing (DSP) and communication system applications [10]. Now days, one of the important application of FFT is the orthogonal frequency division multiplexing (OFDM). It is mainly used in wireless local area network (WLAN), digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). Due to such diverse application of FFT, it is desirable to develop efficient FFT to meet the requirement of various OFDM communication standards. The FFT is a faster version of the Discrete Fourier Transform (DFT) and calculates Discrete Fourier Transform efficiently by reducing the computational complexity. FFT architectures have been comprehensively studied these days [1-4]. At the architectural level, various FFT architectures such as memory-based and pipeline architecture have been adopted. Memory-based architecture is widely adopted to design an FFT processor. It consists of butterfly processing element and memory units. It has low power consumption but long latency and low throughput. To improve the efficiency of memory based FFT architecture, radix-4 butterfly processing units along with dual port memory is adopted in our work. Moreover, the butterfly processing unit decides cost and characteristic of FFT processor. A butterfly unit is composed of complex adders and multipliers [15]. The multiplier is usually the speed bottleneck in the design of the FFT processor. If these complex multiplications are implemented using shift and add operation, it results in higher hardware cost and also, limits the performance of FFT. To improve the performance of such complex computation Vedic algorithm is adopted. The benefits of Vedic algorithm for efficient implementation of complex multiplier have been largely unexplored. A systematic design methodology that incorporates Vedic algorithm, better radix utilization and memory parameters for FFTs has not been thoroughly investigated. In recent years, several designs of FFT using Vedic algorithm have been proposed [5-7]. But all these designs explore limited set of parameters. We contribute with insights on how to use Vedic algorithm structure for highly area-efficient FFT implementation. To further improve area and speed, we adopt efficient radix-4 architecture. Single radix-4 architecture is recursively utilized to compute 64-point FFT. Our proposed architecture includes Vedic based CORDIC algorithm to generate various values of twiddle factor instead of using ROM s to store twiddle factors, which is suited for the power-of-4 radix style of FFT. The remainder of this brief is structured as follows. Detailed analysis radix -4 FFT algorithm is illustrated in Section II. In Section III, the proposed FFT design is discussed. Result and comparison are presented in Section IV. Section V concludes the paper. 134 Copyright Vandana Publications. All Rights Reserved. II. FFT ALGORITHM

2 The DFT of the sequence of N complex of numbers x 0,,x N-1 is defined by: radix-4 uses 48 complex multiplications and 48 complex additions. This is huge reduction in computation complexity. III. PROPOSED DESIGN W = e j (2π / N ) indicates the value of coefficients of the FFT and are often referred as twiddle factors, x (n) is a time sequence and X[k] is a frequency sequence. Direct implementation of (1) yields in large hardware and high complexity. Therefore, to minimize its computational complexity and reduce the hardware cost the fast Fourier transform (FFT) was developed [8]. Using symmetry and periodic property of the complex sequence, W, the Fast Fourier Transform (FFT) is able to effectively decompose and compute a DFT. These properties are defined in (2) and (3). In order to improve performance, we propose a radix-4 FFT processor architecture that operates on data length of 64-points with minimum area consumption. Fig. 3 depicts the block diagram of proposed FFT. The proposed FFT processor is comprised of radix-4 butterfly calculation units implemented using Vedic algorithm, an address generator, memory unit, twiddle factor generator and commutator. Our primary concern is improving the performance of the inefficient computational block of the FFT processor by eliminating the complex critical path components and by using Vedic Algorithm. The detailed functions of each module appeared in Fig. 3 are described in the following subsections. Thus, this reduces the complex number multiplication and addition from N 2 to N/2log 2 N and Nlog 2 N respectively [20]. Generally, FFT operates on an input signal sequence by decomposing it into smaller stages. This decomposition can be performed using decimation-in-frequency (DIF) or decimation-in-time (DIT) decomposition to construct an efficiently computational [4] signal-flow graph (SFG). Here, our work adopts DIF decomposition. The N-point FFT can be decomposed to repeat micro operations called butterfly operations. When the dimension of the butterfly is r, the FFT operation is called a radix-r FFT. For FFT hardware realization, if only one butterfly structure is enforced in the chip, this butterfly unit will execute all the calculations recursively. If parallel and pipeline processing techniques are used, an N point radix- r FFT can be executed by (N/r) log r N clock cycles [18]. This indicates that a radix-4 FFT can be four times faster than a radix-2 FFT. The total number of complex multiplication is (3N/4) and the number of required complex additions is (3N/4). Thus, radix-4 algorithm reduces number complex multiplier. Also, the numbers of stages required are also reduced by half. Fig. 2 depicts SFG for radix-4 butterfly. For computing 64-point FFT A. Address Generation Unit (AGU) The address generator performs memory addressing. The address generation unit controls the address bus going to memory [21]. The FFT processor reads and writes from and to the 8 twin port memory banks concurrently. There are 8 read address buses, and 8 write address buses. They have two signals, Start and Busy. The first one enables the processor to process the data and the second one indicates processing of data inputs. The incoming data samples are partitioned into even and odd samples. After the assertion of the Start signal 64 input samples are clocked into the memory bank. A 6-bit counter controls the serial input of the data in the memory bank. Once all the data inputs are stored in memory bank, a signal Busy is asserted to process the data. AGU also controls the operation of selector unit by generating appropriate signals at a time. Initially, memory has the first 135 Copyright Vandana Publications. All Rights Reserved.

3 64 complex time samples. The butterfly unit selects four samples simultaneously and processes them and outputs the results in the same memory location. The butterfly unit is then given four more samples from memory banks. This process is repeated 16 times (for a 64-point FFT) until all the inputs in memory banks are depleted. At this instant, the first of the three stages has been processed. This pingpong of processed data continues for all three stages. The appropriate four samples must be selected from memory banks for butterfly operation. Also, the appropriate twiddle factors are generated by rotating angle generator. Moreover, to resolve data conflict, conflict free memory addressing scheme is required. One such scheme is discussed in [18]. B. Radix-4 Butterfly Unit using Vedic Algorithm To perform 64-point FFT a single 4-point FFT unit is recursively used. This 4-point FFT is designed using high speed radix-4 algorithm. Moreover, the performance of FFT is limited by arithmetic operation such as complex multiplication. Complex multiplication of two numbers requires 4 multipliers, 2 adders and 1 subtractor or 3 multiplier and 5 adders. This large number of multipliers degrades the performance of FFT. Vedic algorithm is an ancient and well known technique for arithmetic operation. The method which is used for multiplications is Urdhva-tiryagbhyam which means vertical and crosswise. Fig. 4 shows the example based on Vedic algorithm. The very first step is to vertically multiply LSB s of two numbers. Carry bit generated due to this is transferred to the next step and the result bit goes to the final result. In second step, it performs crosswise multiplication with adjacent number. Again, the previous carry bit is added here to yield final result and carry bit is propagated to next step. In third step, the algorithm executes vertical and crosswise multiplication and previous carry is added to give final product. In this way, this algorithm performs multiplication of two given numbers in vertical and crosswise manner until left with only MSB bits. The proposed FFT utilizes Urdhva-tiryagbhyam method of Vedic algorithm to perform complex twiddle factor multiplications. C. Twiddle Factor Generator The twiddle factors are generated using Vedic algorithm based Coordinate Rotation Digital Computer algorithm (CORDIC). CORDIC is a popular technique for computing trigonometric and exponential functions. It performs rotation of a vector through some angle, specified by its coordinates [15-16]. To eliminate the need of ROM to store twiddle factor, proposed FFT uses CORDIC to generate various values of twiddle factor. It uses two mode, rotation mode and vectoring mode. In rotation mode, the rotation by -45 degrees and the other by -135 degrees is obtained. Now, when the original vector is on the X axis, we can rotate it by -45 degrees and then negate the x component to get the vector we would have got had we rotated by -135 degrees [17]. Taking advantage of this fact, we do not pass on -45 degrees or -135 degrees to this module. The module always performs a -45 degrees rotation on the input real valued vector. Y component is negated to get the rotation by -135 degrees. These rotations can be defined by following equations: Here, i represents the iteration, X r (i) and X i (i) are the real and imaginary coordinates of the vector at iteration i, Z(i) is the angle at iteration i and d(i) defines the direction of each rotation. The implementation of above equations requires only shift and add operations. But, these operations consume lot of area and also yield low throughput. To overcome these problems, and to take high speed and low area advantage of Vedic algorithm. Vedic based multipliers are implemented. Setting the y component of input vector to zero (8) and (9) are reduced to [19]: Equation (11-12) that represents twiddle factor can be implemented using Vedic multiplier as shown in fig. 5. Fig. 4. Urdhva-tiryagbyham method of multiplication. D. RAM A memory unit is composed of 8 dual-port memory banks which facilitate 8-way parallel data access. 136 Copyright Vandana Publications. All Rights Reserved.

4 Each memory bank is 8-bit wide. From memory perceptive, in-place memory scheme is adopted so as to minimize the hardware resources and speed up the memory access time. For radix-r FFT, r banks of memory are needed to store data, and each memory bank could be dual-port memory. With "in-place" strategy, the r outputs of the butterfly can be written back to the same memory locations of the r inputs, and replace the old data. Table I shows allocation of data into respective memory banks. FPGA, proposed architecture consumes around five percent occupying 373 slices. The number of lookup tables (LUTs) available is 28,800 and the FFT uses four percent available resources. Dynamic power consumption is only 10 mw. Table III shows performance comparison of proposed FFT design with other existing designs. The result shows that the number of LUTs and slices has been reduced significantly in the proposed design. The operating clock frequency is MHz. E. Commutator The Commutator is one type of a switch that ensures efficient data routing mechanism. It consists of 8- to-1 MUXs. It performs following functions. Commutator 1 routes the butterfly outputs to appropriate memory banks. These memory bank outputs are routed to proper 4- point butterfly inputs according to the control signals obtained from address generation unit. Commutator 2 is responsible for routing the input data to proper memory bank during FFT input period [22]. It is also responsible for routing the memory output data to proper output destinations. IV. RESULT AND DISCUSSION The proposed architecture of FFT processor was modeled using VHDL language. The entire architecture was synthesized and implemented using Xilinx ISE v13.1. The device used for testing the design was Virtex-5 FPGA. The functionality was tested by creating test bench waveform and used in behavioral and post layout simulations. Fig. 6 depicts simulation result of the proposed design. A signal inputbusy is asserted high as soon as all inputs are stored into RAM. This signal is used to start the FFT calculation and to read RAMs, which contain 12 bits wide data input values. When signal inputbusy goes low the next stage of FFT is enabled. The invert signal specify FFT/IFFT mode. Here, we have used FFT mode of operation by setting invert signal to low logic. The output values are 14 bits wide with 3 bits representing the fractional part. A signal outdataen represents valid output. When it is asserted high, this indicates presence of valid output. A signal reset is active high and used to reset the system. Table II shows synthesis result for proposed design. Of the 7200 available slices on the Xilinx Virtex-5 V. CONCLUSION In this work, a new radix-4 FFT processor suitable for OFDM system has been proposed. The proposed architecture achieves high operation speed by employing several performance-enhancement techniques, including a recursive use of radix-4 algorithm realized with multiple memory banks, a conflict-free memory addressing scheme, and a new Vedic multiplier based twiddle factor multiplier structure. Also, area minimization is obtained by devising an efficient Vedic algorithm based butterfly processing structure, while the novel twiddle factor multiplier has low power consumption and hardware complexity. Synthesis results show that the proposed FFT processor can provide up to MHz speed and slices count is 373. The proposed FFT architecture can also be 137 Copyright Vandana Publications. All Rights Reserved.

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