155 Mb/s Optical Line Interface

Transcription

1 155 Mb/s Optical Line Interface Agilent Technologies Broadband Series Test System Product Features Cell based implementation Operates in both cell mode and SONET/SDH frame mode Provides access to ATM cells via parallel data ports in byte serial fashion Provides physical layer measurements as well as error generation Internal traffic generator has 1 foreground channel and up to 100 background channels The Agilent Technologies 155 Mb/s Optical Line Interface generates and analyses ATM cell streams contained within a SONET or SDH framing format. It is a single-slot VXI module that provides test capability at the physical and ATM cell layers for the Agilent E4200/E4210 Broadband Series Test System. The is capable of operating in both a cell mode and in a SONET/SDH frame mode. This allows the user to not only examine ATM cells mapped into a SONET/SDH frame but also all of the SONET/SDH frame data. Line interface modules not only connect the device or system under test to your Broadband Series Test System, but also provide physical, convergence, and ATM cell testing capabilities. Transmission test functionality includes: Traffic generation Cell error, loss & delay measurements Traffic capture & playback

2 Technical Specifications Traffic Generation Modes Three Tx/Rx modes are available. In Terminal mode, full signal generation and analysis functions are available. In Repeater mode, the received signal is re-transmitted (physical layer loop back). In Local Loopback mode, the transmit signal is electrically looped to the receiver. ATM Cell Generation The transmitted cell stream can contain ATM cells generated internally by the, and ATM cells generated by an optional E4209 Cell Protocol Processor module. ATM cells generated on-board can consist of one foreground channel to stimulate the channel under test, and up to one hundred background channels for loading purposes. Fill cells are used to occupy unused bandwidth. Total Bandwidth Mb/s Modes User-Network Interface (UNI) or Network-Node Interface (NNI) HEC Automatic generation Fill Cells Idle or unassigned Channel Priority Order Foreground, background, CPP (highest to lowest priority) Channel Control VCI VPI GFC Payload Type Cell Loss Priority SAR-PDU Support AAL-0 AAL-1 Foreground Channel Bandwidth From 100 b/s to Mb/s in 10 b/s increments Accuracy +/ ppm Background Channels Number of Channels Up to 100 Bandwidth 3000 b/s to Mb/s in increments of 3000 b/s Accuracy +/- 21 ppm Distribution Off Periodic Channel Density Bandwidth and cell distribution for each background channel is individually assignable up to maximum bandwidth Channel Depth 16 cells Cell Payload Single cell PRBS Data pattern Byte access Cell Payloads Payloads Time stamp (32-bit departure time stamp value with 100 nanosecond resolution) Cross cell PRBS-9 PRBS-15 (inverted and not inverted) PRBS-23 Single cell PRBS-9 Data pattern or byte access Data Patterns User byte AA55h or FF00h Incrementing (value of each successive byte is incremented by 1) Byte Access Payload of all cells in the selected channel can be edited by the user in an active channel environment, or off-line as a sequence of PDUs AAL-1 automatically inserts first payload byte containing SN/SNP values and CSI bit Distribution Off Single burst Periodic (according to the specified bandwidth) Channel Depth 1500 cells (variable) Cell Payload Timestamp Single cell PRBS Cross cell PRBS Data pattern Byte access 4

3 Erroring Control Error conditions can be introduced to simulate alarm signals and signal stressing. Error stressing is used to generate incorrect bytes in a test signal. Error Stressing Control Off SONET/SDH Stressing On ATM & SONET/SDH Measurements Pulse On (error condition is normally off; pulses on) Pulse off (normally on; pulses off) Sequence On (normally off; alternates on/off/on) Sequence Off (normally on; alternates off/on/off) ATM Error Injection Cell header or payload bytes with bit error masking Cell Loss Sequence Number in the SAR-PDU is skipped and a fill cell is inserted PRBS Error Add Single bit error add to the PRBS pattern in the cell payload SONET/SDH Stressing SPE pointer errors can be introduced once or at a user defined sequence Data errors can be introduced singly or at a rate of 1.0E-9 to 1.0E-3 on to the Section/RS BIP, Line/MS BIP,Path BIP, Line/MS FEBE and Path FEBE Loss of signal for either a single frame, or continuous Measurements are sampled every 100 milliseconds and accumulated over the user-specified measurement period. Results from the most recent complete measurement period are retained Measurement Period Range 1 second to 3 days in resolutions of 1 second Result Types Cumulative or latched (based on most recent measurement period) Result Formats Count Ratio Seconds Virtual Channel Errors AAL-1 SN/SNP errors Cell loss PRBS errors PRBS sync loss alarm seconds SONET/SDH Measurements Traffic Capture & Playback Out of frame errors Loss of frame alignment errors Loss of pointer errors Loss of cell synchronization error Loss of signal errors Line AIS Line FERF Path AIS Path FERF Path yellow Section BIP Line BIP Path BIP Path FEBE Line FEBE Uncorrected HEC error ATM Capture Provides capture of 1500 cells from the selected ATM cell stream. Capture is manual or event triggered. Manual triggering captures 1500 cells after the trigger. Event triggering captures 750 cells pre-trigger, and 750 cells post-trigger. Manual Triggered on user request ATM Cell Triggers Cell loss Header error PRBS error SN/SNP byte error SONET/SDH Capture When in SONET/SDH frame mode, the E1697 line interface captures and displays TOH data, POH data, and path trace messages. ATM Cell Measurements HEC errors Corrected headers Cell count Cell bandwidth Select Cell Not Received (SCNR) alarm seconds Cell Delay Measurements Cell delay Inter-arrival time Cell delay variation 5

4 Parallel Data Port The line interface has two parallel data ports, one to transmit and one to receive ATM cells in byte serial mode. The parallel ports includes byte-wide cell data, a cell synchronization pulse, and a variable rate clock input and output. Cells may be optionally scrambled and descrambled. Connector D1 is the receive data port interface; connector D2 is the transmit data port interface. The receive data port provides automatic cell delineation using the HEC method as per ITU-T Recommendation I.432. Input cell synchronization is not required. Data Port Specifications Clock source Mb/s using internal clock source; 20 Mb/s to 156 Mb/s using external clock Clock rate MHz using internal clock source; 2.5 MHz to 19.5 Mhz using external clock Line format Non Return to Zero (NRZ) Input and output levels TTL Input impedance >1000 ohms Source impedance 50 ohms (typical) Required load impedance Greater than 500 ohms; less than 15 picofarad Recommended cable Less than 1 meter of 3M type 3600/26 shielded twisted pair Timing Timing relationships between the clock and data for the transmit and receive data ports are shown in figures below. Parallel Port Pinouts The D1 and D2 data ports use high-density 26 pin slim line female D connectors. Signal Connector Adaptor Cable Data Data Data Data Data Data Data Data Sync Clock 1 1 Ground 13,14,19,23,25,26 13,14,19,25 6

5 Front Panel Connectors & Indicators OC-3 Input FC-PC adapter Rx sensitivity of -24 dbm for 10E-10 residual BER Input overload greater than -7 dbm 1310 nm OC-3 Output FC-PC adapter Class 1 laser 1310 nm Exceeds Intermediate Reach (IR) specifications Reference Clock Input SMB connector 1 V p-p input Nominal 50 ohm impedance MHz with better than a 55/45% duty cycle Rx/Tx Trigger Outputs SMB connectors TTL outputs Nominal 50 ohm impedance Tx Clock/Data Trigger Outputs SMB connectors ECL levels Clock: Mhz with better than a 55/45% duty cycle Data: Mb/s serial stream Timing, propagation delay of 2.5 to 5.0 nanosecond w.r.t. rising clock edge 50 ohms, terminated to -2 V Applicable Standards ATM Cells ITU-T Recommendation I B-ISDN ATM layer specification Telcordia TA-NWT Asynchronous Transfer Mode and ATM Adaptation Layer (AAL) Protocols Generic Requirements SONET/SDH SDH as per ITU-T G.708 and I.361 for BSTS CD-ROM software releases prior to version A.10; SDH as per ITU-T G.707 (draft) COM E, July 1995 "Draft revised ITU-T recommendation G.707 network node interface for the synchronous digital hierarchy (SDH)" for A.10 and later releases SONET as per Telcordia TA-NWT for BSTS CD-ROM software releases prior to version A.10; SONET as specified by Telcordia GR-253-CORE "Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria" for releases A.10 and later PRBS Patterns PRBS-9 as per ITU-T O PRBS-23 as per ITU-T O EMC CISPR11, Class A Rx Clock/Data Trigger Inputs SMB connectors ECL levels Clock: Mhz with better than a 55/45% duty cycle Data: Mb/s serial stream NRZ timing, setup and hold within 400 picosecond w.r.t. rising edge 50 ohms, terminated to -2V LED Indicators Failed Error Access Ref Clk Gating Signal BIP Size, Weight & Power Dissipation Size 1 slot C-size VXI card Weight 1.3 kg (2.9 lb) nominal Power Dissipation 36 Watts (max) 7