PRODUCT SUMMARY. SARA-Lite SAR for AAL Type 0/5 with UBR Traffic, Frame Relay and LANE Support INTRODUCTION

Transcription

1 SARA-Lite SAR for AAL Type 0/5 with UBR Traffic, Frame Relay and LANE Support INTRODUCTION PRODUCT SUMMARY SARA-Lite ATM AAL0/5 Segmentation and Reassembly Product TheTranSwitchSARA-Lite product provides ultra high-performance ATM Segmentation and Reassembly (SAR) processing with programmable flexibility. It consists of separate hardware and software parts, namely the SARA-2 ATM Cell Processing Integrated Circuit (IC) Device and SARA-Lite Microcode. This microcode is loaded into the instruction memory of the SARA-2 s integral RISC processor and enables it to perform the specific AAL Type 0/5 SAR functions of SARA-Lite with CBR, VBR and UBR traffic, as well as providing support for the implementation of frame relay and LAN emulation services via software. Product documentation and applications support is available for OEMs who wish to undertake the design of systems incorporating SARA-Lite. The SARA-2 ATM Cell Processing IC includes an integrated RISC engine and OC-3 SONET/SDH framer. It contains several functional blocks that provide optimal cell processing at rates up to 155 Mbit/s via a careful mix of hardwired logic and programmable microcode. One subsystem, the SARA-2 ATM Communications Processor (ACP), is a RISC processor with additional specialized instructions for cell processing. This engine, along with powerful on-chip DMA and memory controllers, a hardware hash table lookup mechanism, and high-performance cell/line interface functions, enables the SARA-Lite to support various data networking applications. Furthermore, other SAR functions may be added in the future via microcode changes as standards and system requirements evolve. This document describes the operation of the SARA-Lite ATM AAL0/5 Segmentation and Reassembly solution in the following sections: Page 1.0 SARA-Lite System Overview Segmentation and Reassembly of Packets into/from ATM Cells SARA-Lite Traffic Scheduling and Hash Mechanisms AAL0 or Raw Cells Support Frame Relay Service/ATM Interworking LAN Emulation (LANE) Service Related Documents...33 Please refer to the two TranSwitch documents listed in Section 7.1, which complete the description of the SARA-Lite product. Copyright 1998 TranSwitch Corporation TranSwitch, TXC and SARA are registered trademarks of TranSwitch Corporation SARA-Lite is a trademark of TranSwitch Corporation. Microsoft, Windows and Windows NT are either trademarks or registered trademarks of Microsoft Corporation. Other brand, product and company names mentioned herein may be the property of their respective owners. Document Number: TXC SCDA-PS1 TranSwitch Corporation 3 Enterprise Drive Shelton, CT USA Tel: Fax:

2 1.0 SARA-Lite SYSTEM OVERVIEW SARA-Lite combines the versatility of a programmable RISC architecture with an optimized hardware platform to perform ATM SAR functions. The SARA-2 ATM Cell Processing IC Device is the core hardware platform used in conjunction with RISC microcode to implement the SAR functionality. Figure 1 graphically depicts the concept of the SARA-2 programmable architecture together with SARA-Lite microcode to implement the following functions: 1. Implementation of the Common Part Convergence Sublayer (CPCS) for AAL Type 5, which includes: Support for message mode: fixed or variable length (0-65,535 bytes) CPCS-SDU support Non-assured operation: in the event of corrupted CPCS-SDU, re-transmission is not supported Preservation of sequence integrity per connection Preservation of U-U information (1 byte) 48-byte alignment to the CPCS-PDU trailer Insertion of PAD bytes in the CPCS-PDU Insertion of the length field in the trailer CRC-32 field calculation in the trailer 2. Implementation of the SAR Sublayer for AAL Type 5 including: Segmentation of variable length CPCS-PDUs into 48-byte SAR PDUs Reassembly of 48-byte SAR PDUs into variable length CPCS PDUs Creation of 53-byte ATM cells by adding a header to the SAR PDU Exception conditions include: Error in cell syntax: bad header CRC, bad payload CRC Error in received packet: end-of-frame not received before beginning of a new packet DMA error conditions PCI error conditions SARA-2 ATM Cell Processing IC Part Number TXC ACBG SARA-Lite Microcode Part Number TXC SCDA + = SARA-Lite Product AAL0/5 SAR CBR, VBR and UBR Traffic Frame Relay Support LAN Emulation Support Figure 1. SARA-Lite Product Overview -2 - TXC SCDA-PS1

3 3. AAL0 or Raw Cells support 64-byte or 48-byte AAL0 can be supported When 64-byte mode is selected, a complete 64-byte cell buffer is copied into/from the external host buffer, rather than the 48-byte cell payload 4. Frame Relay Service (FRS) support Interworking Function support Discard Eligibility (DE) to CLP mapping FECN to EFCI mapping 5. LAN Emulation (LANE) support LECID receive filtering 1.1 DATA STRUCTURES IN THE SARA-Lite The SARA-Lite requires several data structures for its operation, which control the data flow, packet transfers from/to host memory, traffic management, and maintenance functions. The specific contents of each of the data structures will be covered in the following sections. However, an overview of each of the intervening structures will be given in this section. Figure 2 shows the typical environment in which the SARA-Lite operates with three distinct interfaces: (i) PCI connection to a host processor, (ii) local control memory, and (iii) cell interface. The control of the SARA-Lite is performed via the PCI interface from a host processor, which typically will be part of a PC station with a number of PCI slots. However, it is possible to implement the PCI bus in a single PCB. The control memory is used by SARA-Lite to store data for control and for temporary buffering of incoming and/or outgoing cells.the cell interface transmits and receives ATM cells either via UTOPIA or via a SONET/SDH framer. Regarding the data structures, the actual usage by the SARA-Lite is context sensitive. The meaning of the information in these data structures and its interaction with the host controller will be understood when the specific operation of the SARA-Lite is addressed later in this document. At this time, a summary of the data structures is provided, with a brief explanation of their function in the overall operation. More detailed information is provided in the Data Sheet for the SARA-2 ATM Cell Processing IC Device, document number TXC MB. RISC Controller Structures The SARA-Lite RISC core requires various stacks and stack pointers, some local variables, configuration information, and the dynamic memory allocation heap. These are automatically initialized in the external RAM by the RISC core upon power-up. Reassembly Hash Table The Reassembly Hash Table consists of a linear array of 24-bit pointers to chains of Reassembly VC structures. The hash table logic performs a hash on the VPI/VCI fields of each received ATM cell header to derive a table index to an entry in the Reassembly Hash Table. The hash index computation is controlled by a set of three registers which provide two 16-bit masks and a 4-bit shift value. By programming different binary patterns into the mask registers and using different shift values, different hash functions may be generated TXC SCDA-PS1

4 PCI Bus SARA-Lite Host Buffers Reg. Reassembly, Hashing CPU IR PCI BUS I/F DMAI DMAO Service Q RISC LinkI Queue Segmentation, Traffic shaping LinkI LinkO Free Cell Buffer pointer queue Cell FIFO Rx Tx UTOPIA/ Framer Cell Interface RR Memory Controller Control Memory Indicate MSG Pool MSG Pool Reassembly Buffer Pool Free Cell Buffer Pool Segmentation VC structures Allocated Cell Buffer Rate Control Table (RCT) UBR... BD BD BD BD Reassembly Hash Table BD BD Reassembly VC structures Figure 2. SARA-Lite Operating Environment Rate Control Table (RCT) SARA-Lite uses the Rate Control Table to provide precise control over the granularity of rates requested per virtual circuit and also to provide flexibility in the multiplexing of different virtual circuits. It is also used to determine the burst size and sustainable cell rate (SCR) allocated to each virtual circuit. The traffic shaping hardware in the device traverses the Rate Control Table to schedule cell transmissions. The Rate Control Table is a linear array of 32-bit entries. Each entry points to a segmentation VC structure entry. During segmentation, the Rate Control Table is traversed sequentially and each entry is provided service according to the control bits. Each entry in the table corresponds to a CBR or VBR virtual circuit. When an entry in the Rate Control Table is serviced, one or more ATM cells (based on the burst size in the Segmentation VC structure) can be sent from that virtual circuit. A Rate Control Table entry may also specify a null entry (an idle cell is sent) or a skip entry (that entry is skipped). A UBR virtual circuit is serviced when the CBR or VBR virtual circuit pointed to by the Rate Control Table does not have a cell to send, or when the Rate Control Table entry specifies a null cell. All UBR virtual circuits are maintained in a circular linked list, resulting in round-robin servicing of the UBR virtual circuits TXC SCDA-PS1

5 Virtual Circuit Structures Data structures associated with both Segmentation and Reassembly are referred to as Segmentation VC structures and Reassembly VC structures, respectively. These structures are used by the SARA-Lite to control the segmentation and reassembly of cells into the appropriate VCs. The segmentation VC structure contains information relating to each virtual connection set up for segmentation. A separate VC structure is present for each virtual circuit, whether it is CBR/VBR or UBR. When a virtual connection is established, the contents of the entry corresponding to the virtual circuit are initialized by software. A VC structure indicates the AAL type associated with the virtual circuit and contains other control and status information specific to the virtual circuit. An additional field in the VC structure provides a pointer to active Buffer Descriptors. The reassembly VC structure contains information relating to each virtual circuit set up for reassembly. When a virtual circuit is established, the contents of the VC structure corresponding to the virtual circuit are initialized by software. A VC structure indicates the AAL type associated with the virtual circuit and contains various control and status information related to the virtual circuit. An additional field in the entry provides a pointer to active Buffer Descriptors. Buffer Descriptors (BD) SARA-Lite segments and reassembles packets using the host buffer memory. The Buffer Descriptors are a set of 16-byte structures that describe the parameters of blocks of data or free buffers. Each entry contains parameters for segmenting packets and the location of the buffer in the packet memory. When a packet is set up for segmentation, an available Buffer Descriptor is initialized with the packet parameters. Similarly, free Buffer Descriptors are used to reassemble cells into packets. Buffer descriptors are chained together in a linked list to support sophisticated scatter and gather algorithms and to support efficient packet memory management. Host Request and Indicate Ring Structures The host software interacts with the SARA-2 via a service interface consisting of request and indicate message rings (RR and IR) in host memory. Both high and low priority rings are maintained for RR and IR. All waiting messages with high priority will be served before a message of low priority. The host sends a request message, such as connection set-up or packet segmentation, to the SARA-2 via the request rings. The SARA-2 sends a response or notification indicate message, such as packet reassembly completion or OAM cell receive notification, to the host via the indicate rings. SARA-Lite host interface logic implements associated request ring / indicate ring logic which facilitates the exchange of messages between the host software (e.g., device drivers) and the on-chip RISC microcode with very low overhead in either an interrupt-driven or polled manner. The message rings have hardware support for minimizing message interrupt overhead and also for setting bounds on interrupt overhead. The request and indicate message structure is similar to the Buffer Descriptor (i.e., 16-byte entries). Message Pool The Message Pool is a linked list of free 16-byte message descriptors. The messages from the request rings in host memory are transferred into these descriptors. If the message is a packet for segmentation, this descriptor is then linked to the associated segmentation VC structure. If it is a host buffer allocated for packet reassembly, it is linked either to the Reassembly Buffer Pool, or to a specific Reassembly VC structure. Reassembly Buffer Pool The Reassembly Buffer Pool is a linked list of free host buffer descriptors. It is used by the SARA-2 to queue the Buffer Descriptors for host buffers that are available for packet reassembly. When the SARA-2 receives the first cell of a packet, it fetches a descriptor from this queue and starts reassembly in the host buffer pointed to by the descriptor. Indicate MSG Pool The Indicate Message Pool is used by the SARA-2 to queue the response or notification messages to the host before these messages are forwarded to the indicate rings TXC SCDA-PS1

6 Cell Buffers (CB) The cell buffers are 64-byte memory segments in local control memory used for temporary storage of cells for segmentation and reassembly. These buffers allow lossless reassembly even under large PCI latency restrictions. 1.2 INITIALIZATION PROCEDURES These procedures perform the following functions: Initialize the registers of the SARA-2, such as control registers. Set up service interface rings (indicate and request rings). Download and run microcode. Set up host buffers for transmit and receive data operations TXC SCDA-PS1

7 2.0 SEGMENTATION AND REASSEMBLY OF PACKETS INTO/FROM ATM CELLS 2.1 ATM ADAPTATION LAYER SARA-Lite has been designed to support the segmentation and reassembly functions required to achieve packet transmission across an ATM network (or an SMDS network). In this and the following section, these functions, as defined in the ANSI draft standards for B-ISDN, are briefly reviewed. Figure 3 illustrates the protocol model for the variable bit rate (i.e., packet based) ATM Adaptation Layer (AAL) Type 5 as defined in the ANSI draft standards 1,2. The AAL is split into three sublayers. The service specific convergence sublayer (SSCS) is used to add additional service features such as assured transfer (error correction by retransmission). It may be a null sublayer for unassured transfer (error detection but no correction). The Common Part Convergence Sublayer (CPCS) performs error detection and control functions at the frame level. The Segmentation and Reassembly Sublayer (SAR) performs the functions necessary to segment frames into ATM cells and reassemble a multiplexed stream of ATM cells back into their original frames. SARA-Lite supports the functions of the CPCS and the SAR sublayers for AAL5 common part, and some functions of the ATM layer. User Layer Service-Specific Convergence Sublayer (SSCS) ATM Adaptation Layer (AAL) AAL5 Common Part Common Part Convergence Sublayer (CPCS) Segmentation and Reassembly Sublayer (SAR) ATM Layer Physical Layer Figure 3. Protocol Model for Variable Bit Rate AAL Type AAL Type 5 The structure of the CPCS-PDU for AAL Type 5 is shown in Figure 4. The CPCS payload is a variable length field containing 0-65,535 bytes of CPCS-user information. The PAD field is used to align the CPCS-PDU to a 48-byte boundary. The PAD field is octet-aligned and can range from 0 to 47 bytes. The CPCS-UU field contains one byte of user-user information and can take on any value. The CPI field is reserved for supporting future functions. The length field indicates the length in bytes of the payload field. 1. T1S1.5/92-003R2 Broadband ISDN ATM Adaptation Layer 3/4 Common Part Functionality and Specification May T1S1.5/ Broadband ISDN ATM Adaptation Layer 5 Common Part Functionality and Specification May TXC SCDA-PS1

8 The CRC-32 field contains the result of the CRC-32 calculation performed over the entire CPCS-PDU as specified in the ANSI standard. CPCS-PDU CPCS Payload PAD CPCS-UU CPI Length CRC-32 Bytes: Figure 4. Structure of the AAL Type 5 CPCS-PDU 1 The segmentation process for AAL5 is illustrated in Figure 5. CPCS Trailer CPCS-User_PDU Common part convergence sublayer CPCS Payload PAD Trailer CPCS-PDU Segmentation and Reassembly Sublayer SAR Payload SAR Payload SAR Payload SAR_PDU ATM Layer Cell Payload Cell Payload Cell Payload ATM cell header with user-to-user indication = 0 ATM cell header with user-to-user indication = 1 Figure 5. Segmentation Process for AAL Type 5 The CPCS-PDU is segmented into 48-byte segments, with each segment forming a SAR_PDU. No SAR_PDUs are partially filled, since the CPCS-PDU is aligned to a 48 byte boundary. There is no SAR header or trailer on the SAR_PDU. Each SAR_PDU forms the 48-byte payload of an ATM cell. Each ATM cell has a five-byte cell header. An ATM-user-to-user indication is available in the payload type field of the ATM cell header. AAL5 uses an ATM user-to-user indication of 1 to indicate the last SAR_PDU of a CPCS-PDU. All other SAR_PDUs are carried in ATM cells with an ATM user-to-user indication of T1S1.5/ Broadband ISDN ATM Adaptation Layer 5 Common Part Functionality and Specification May TXC SCDA-PS1

9 2.1.2 SARA-2 AAL5 Service In the transmit direction, the CPCS-PDU for AAL5 is as illustrated in Figure 6, with the specific fields calculated and inserted. The SARA-2 supports: 1. Calculation of the PAD size and insertion of the PAD 2. Insertion of the CPCS trailer provided by the host via the Service Interface request primitive Send Segment End. 3. Calculation and insertion of the CRC-32 field. CPCS-PDU CPCS trailer Payload PAD CPCS-UU CPI Length CRC-32 Bytes Provided by host and inserted by SARA-2 Calculated and inserted by SARA-2 Figure 6. Construction of CPCS-PDU for AAL5 in Transmit Direction In the reassembly direction, the received CPCS-PDU for AAL5 is as illustrated in Figure 7. The SARA-2 delivers the whole CPCS-PDU to the host and supports: 1. Reassembly of the full CPCS-PDU into host memory 2. Notification of the CPCS-UU, CPI and Length fields to the host via the Service Interface primitive "RcvSDUcomplete" 3. CRC-32 checking. CPCS-PDU CPCS trailer Payload PAD CPCS-UU CPI Length CRC-32 Bytes Provided to the host via the Service Interface Figure 7. Disposition of CPCS-PDU for AAL5 in Reassembly Direction -9 - TXC SCDA-PS1

10 2.2 THE ATM LAYER The format of the ATM cell at the user network interface (UNI) of an ATM network, as defined by the CCITT for broadband ISDN 1, is shown in Figure 8. The generic flow control (GFC) field is used to ensure fair and efficient access between multiple devices sharing a single UNI. A label space of 24 bits is provided, divided into two fields: an eight-bit virtual path identifier (VPI), and a 16-bit virtual channel identifier (VCI) 2. The VPI allows a group of virtual connections, called a virtual path, to be identified and the VCI identifies the individual virtual connections within each virtual path. The payload type (PT) field is used to distinguish user information and network information. For user information cells, the payload type field carries a single bit ATM user-to-user identification. The cell loss priority (CLP) bit permits two priorities of cell to be defined so that the network may discard low priority cells under congestion conditions. The header error check (HEC) field provides an eight-bit cyclic redundancy check on the contents of the cell header. ATM Cell Header GFC VPI VCI PT CLP HEC Payload Bits Figure 8. Structure of an ATM Cell at the User Network Interface 48 bytes 2.3 ATM SEGMENTATION IN THE SARA-Lite The segmentation of packets performed by the SARA-Lite requires a series of steps, as shown in Figure 9. In order to properly set up the connection and initiate the segmentation of the packets, there must be interaction between the host processor and the SARA-Lite via the PCI bus. A service interface defines the low-level control of the operation of the SARA-Lite via messages that are passed between the host memory and the SARA-Lite hardware. Allocate Host Buffer for Data Packet Link Host Buffer to VC structure (See Figure 11) Packet Segmentation (See Figure 12) Recycle Host Buffer (See Figure 14) Figure 9. Steps for Segmentation of an AAL5 Packet 1. CCITT Recommendations I.150, I.361 (Geneva, June 1992). Note that the CCITT has since been re-named to ITU-T. 2. Within the telecommunications industry, the terms virtual connection, virtual channel, and virtual circuit tend to be used as synonyms. In this document the more general term virtual circuit has been adopted TXC SCDA-PS1

11 In order to segment a packet into ATM cells several steps must be fulfilled which are shown in Figure 9. Several simplifications have been applied in this flowchart. First it is assumed that structures in the SARA- Lite have been properly initialized and the appropriate parameters for each VC programmed into Control Memory. Some of these parameters include the bandwidth allocation for each VBR/CBR circuit, and setup of the number of VCs. Host buffers OS 1 Request/ Indicate Rings CPU Host Memory PCI BUS Interface Serial EPROM Interface D M A 5 7 Segmentation Traffic Shaping RISC Reassembly Hashing Memory Controller 6 8 Output Cell Control & FIFO UTOPIA Interface SONET/ SDH Framer Interface SARA-Lite 3 Cell Buffers Buffer Descriptors Segmentation VC structures Rate Control Table 4 Control Memory Figure 10. Segmentation Flow in SARA-Lite The following numbered list describes the individual arcs shown in Figure 10 for Segmentation Flow. 1. The host CPU writes packets (CPCS-PDU payloads) that are to be segmented to buffers in host memory. A CPCS-PDU may be scattered among several host buffers. 2. As host buffers are filled with data, the host software generates a series of service interface request messages (one per host buffer). Each request message specifies the VC, buffer size and host memory address. The message also specifies the AAL type and whether the host buffer is associated with the last fragment of a CPCS-PDU. 3. The SARA-2 processes the request messages and adds the resulting buffer descriptors to a linked list pointed to by the segmentation VC structure. This linked list enables multiple host buffers on the same VC to be set up for segmentation. 4. When the traffic scheduler services the Rate Control Table (RCT), the Segmentation VC structures are retrieved. If the CURR_BUFF_DESCR in a Segmentation VC structure is NULL, then no data exists for the VC. Otherwise, if there are host buffers active for segmentation, the CURR_BUFF_DESCR provides a pointer to the linked list of buffer descriptors. Each buffer descriptor provides the address to access data in host memory. 5. The DMA controller makes a request on the PCI bus. Once the request is granted, the SARA-2 becomes a master on the PCI bus. The DMA controller also fetches a free cell buffer from the free cell buffer pool in SARA-2 control memory. The DMA controller fills the free cell buffer with data from the PCI memory, decrementing the size and incrementing the address fields of the buffer descriptor. If the data belongs to the last cell of a PDU, the DMA controller writes the specified number of padding bytes into the cell buffer and then copies the CPCS-PDU trailer TXC SCDA-PS1

12 6. The segmentation processing logic processes the AAL Specific Fields of the Segmentation VC structure and flags from the buffer descriptor to generate the AAL SAR-PDU header and trailer fields. The SARA-2 writes back to control memory the partial CRC, data address and data size fields, and updates the flags and cell count. 7. When the output cell FIFO can accept a cell, the output control logic retrieves the cell from the cell buffer to prepare it for transmission. The cell buffer is released to the free cell buffer pool. 8. In the UTOPIA mode, if the external interface is ready to accept a cell, the cell is sent out. If in the framer mode, the cell is mapped into the payload of the SONET/SDH frame and the framer adds the SONET/SDH overhead bytes. 9. When a CPCS-PDU is completely segmented, the SARA-2 sends a service interface indicate message, with or without an interrupt, releasing the buffers associated with the CPCS-PDU for re-use by the host Link Host Buffer to VC Structure The linking of a packet to the corresponding VC structure starts when the host writes a message into the Request Ring, as shown in Figure 11. The format of the message is specified in the SARA-Lite Service Interface Technical Manual (document number TXC TM1) and it is repeated in Table 1 for the reader s convenience. The message written by the host is a 16-byte message containing information on the VC number to link the packet as well as other parameters such as the type of connection (VBR, CBR, or UBR) and the request to send the packet. A detailed explanation on the message format, meaning, and usage can be found in the same Technical Manual. Host * Write MSG to Request Ring (RR), one MSG for one host buffer * Update the RR Tail registers in SARA-2 SARA-Lite * RR queue is not empty: Read MSG from RR; process Mtype & Mflags; copy MSG to Free MSG buffer (h/w) * Update RR head register (h/w) * Update head pointer of Free MSG Buffer queue MSG Format: Mtype Mflags Word1 Word2 Word3 VCID SARA-Lite * Load the pointer (physical address of MSG buffer) with proper request code to service queue (h/w) TypeCode(4) ReqCode(4) BDptr(24) SARA-Lite * RISC processes TypeCode and ReqCode: RISC links this MSG buffer to VC structure if MSG buffer contains information of a packet for segmentation. The VC structure and Buffer Descriptor (BD) are updated. Figure 11. Host Buffer Linking to VC Structure in SARA-Lite TXC SCDA-PS1

13 Mtype Mflags VCID Word 1 Word 2 Word 3 Table 1: 16-Byte Structure for Request Ring Messages After writing a message into the Request Ring, the host updates the Request Ring tail pointers. This action will prompt the SARA-Lite to read the message in the Request Ring and start the process to link the packet into the VC structure. All these actions are performed internally to the SARA-2 and are transparent to the user. The Request Ring head and tail registers are part of the Communications Registers in the SARA-2 IC. The host will have to write to the tail register in order to add an additional message to the queue which will be serviced by the SARA-2 RISC. It is important to notice that the minimum number of Service Interface messages that the host needs to write to the Request Ring to transmit a CPCS-PDU is two. The first message is used to "Send Segment" over the PCI interface to the SARA-Lite control memory, and the second is used to "Send Segment End" to signal that no more buffers need to be linked to that particular VC for that CPCS-PDU Packet Segmentation The segmentation of a packet will take place if two conditions are fulfilled, namely that there is data to be transferred for a particular VC and that VC is a candidate for transmission. The first condition is met as soon as the linkage of the packet is finalized. The second condition is required to be met in order to fulfill the negotiated rate for that VC which is determined by the programming of the Rate Control Table. Also, it is important to distinguish between different types of traffic such as CBR/VBR and UBR. CBR and VBR traffic are managed by means of a Rate Control Table mechanism. The Rate Control Table is traversed and VCs that are candidates are examined to determine if data on that VC is ready to be transferred. The Rate Control Table is a linear array of 32-bit long descriptors that have to be appropriately programmed to allocate bandwidth to each of the connections. Figure 12 shows the flowchart of events required in the segmentation of a packet for AAL5. Two rate control tables are displayed: (i) one for CBR/VBR VCs, and (ii) one for UBR VCs TXC SCDA-PS1

14 * RCT Traversal Unit sequentially scans through the RCT; UBR Traversal Unit looks for segmentation candidate * Send CBR/VBR cells, UBR cells or idle cells * DMAO obtains a free cell buffer pointer from free cell buffer pointer queue RCT traverse (CBR/VBR) RCT VC structure BD BD * DMAO writes ATM header (read from VC structure) into cell buffer; copies 48 bytes from host buffer to cell buffer * Calculates CRC-32; updates VC table and BD table CBR/VBR traffic UBR traverse VC structure BD BD * DMAO forwards cell buffer pointer to DMAO-LinkO queue * Link controller outgoing channel reads data from cell buffers; forms 52-byte ATM cell into cell FIFO * Link controller writes cell buffer pointer to the free cell buffer pointer queue UBR traffic Figure 12. Packet Segmentation in SARA-Lite For CBR/VBR circuits, once data is available and that particular VC is a candidate to send cells, the SARA-Lite will transfer the cells from the host memory into the Control memory. The cells will be forwarded from the Control memory to either the UTOPIA or SONET/SDH Framer cell interface for transmission onto the physical link. In the absence of CBR/VBR VC candidates, or in the absence of CBR/VBR data to transfer, the SARA-Lite will look for UBR VC candidates to transfer data TXC SCDA-PS1

15 2.3.3 Host Buffer Recycling After segmentation, it is necessary to recycle some of the data structures used in the process. Some of the structures are automatically recycled by SARA-Lite transparently to the user. However, the host needs to recycle the buffers allocated in host memory for the packet. The host can start recovering these packet buffers as soon as SARA-Lite notifies the host that the information in the buffers has been transferred to SARA-Lite Control memory. Figure 13 describes the processing of a Buffer Descriptor by SARA-2. If the NOTIFY bit of Descriptor Mode in BD is set to 1, RISC will forward the message contained in the BD to the host via indicate rings. last cell of BD? Yes No Continue Segmentation * RISC processes Buffer Descriptor after the packet is segmented. Notify=1? No Yes * RISC releases BD back to MSG Pool. * Update the head pointer of MSG pool. * RISC links BD to indicate MSG pool. * Update the tail pointer of Indicate MSG pool. * DMAI copies the Indicate MSG to Indicate Ring. * DMAI updates the head pointer of indicate MSG pool. * DMAI releases the BD to MSG pool by updating the head pointer of MSG pool. Figure 13. SARA-2 Segmentation Processing of Buffer Descriptor TXC SCDA-PS1

16 A summary of the host buffer recycling is shown in Figure 14. The path begins by the host allocating the buffers in memory and notifying SARA-Lite of the existence of a packet waiting for segmentation. Internally SARA-Lite will allocate a Buffer Descriptor for each of the memory segments required by the packet awaiting segmentation. Host SARA-Lite MSG Pool Buffer Descriptor Request Ring Indicate Ring OR RISC Indicate Logic Indicate MSG Pool Figure 14. Host Buffer Recycling in SARA-Lite Once the packets are transferred to the Control memory, an entry to an internal service queue is added. With every Buffer Descriptor being used, SARA-Lite will recycle the buffer for re-utilization. At the last Buffer Descriptor of the packet, SARA-Lite notifies the host via the indicating logic by placing a message in the Indicate Ring. The message written to the Indicate Ring is similar to the one shown in Table REASSEMBLY OF AAL5 PACKETS Cells can be received either via UTOPIA or via SONET/SDH frames. In either case, the cells received are forwarded to the link queue block which in turn will be managing the transfer to cell buffers in control memory and finally to packet memory in the host memory TXC SCDA-PS1

17 The reassembly steps are shown in Figure 15 and the flow is detailed in Figure 16. Three main blocks are represented in Figure 16: (i) SARA-Lite with the internal structures, (ii) Control Memory used by SARA-Lite to store data structures, and (iii) Host Memory for both packet memory and service interface messages. Receive Cell at the Cell Control Block Perform Hashing on the incoming VP/VC Search VC Connection and find the pointer to the VC Reassembly Structure Write Cell to Free Cell Buffer Connection Not Supported Cell Discarded Notify Host Transfer Cell to Host Memory Packets Figure 15. Steps for Reassembly of an AAL5 Packet 1 Host buffers Request/ Indicate Rings 6 8 PCI BUS Interface D M A Segmentation Traffic Shaping RISC Reassembly Output Cell Control & FIFO UTOPIA Interface SONET/ SDH Framer Interface 1 Serial EPROM Interface Hashing Memory Controller SARA-Lite OS CPU Host Memory Cell Buffers Buffer Descriptors Reassembly VC structures Hash Table Reassembly Buffer Descriptor Pool Control Memory Figure 16. Reassembly Flow in the SARA-Lite TXC SCDA-PS1

18 The cell coming from either the SONET/SDH framer or the UTOPIA interface has to be processed and reassembled into the host memory. Before the actual reassembly occurs, several intermediate steps must be fulfilled. A flow chart detailing these steps is shown in Figure 15. The ATM header of the cell that arrives at the SONET/SDH framer or UTOPIA interface is used to perform the hashing algorithm and determine it is a valid connection or not. A pointer is obtained from the hashing and a search for the appropriate connection is performed. If the cell corresponds to a valid connection it is transferred to a cell buffer in the Control memory where it will wait for the final transfer to the appropriate host memory buffer. After the cell has been transferred, some of the intervening data structures need to be recycled. AAL5 CPCS-PDU Reassembly The following numbered list describes the individual arcs shown in Figure If the internal framer mode is used, the SARA-2 delineates cells after framing to the transmission format. If the UTOPIA mode is used, the SARA-2 receives complete 53-byte ATM cells. 2. The hash control logic processes the ATM cell header of the received cell to provide a hash table index. The hash table entry provides a pointer to the Reassembly VC structure corresponding to the ATM cell. 3. The SARA-2 fetches a free cell buffer and writes the cell to the control memory. This allows adequate system throughput even under delayed access to the PCI bus (due to usage of the PCI bus by other devices). 4. The Reassembly VC structure fields are read to determine the AAL type and obtain reassembly flags. The CLP and PT fields of the incoming cell are also processed. AAL-specific functions are performed and the reassembly structure fields are updated. 5. The DMA controller gets a buffer descriptor pointer. If the reassembly VC has host buffers allocated to it, the VC structure points to an available buffer descriptor, and that BD is used. Otherwise, the SARA-2 fetches a new buffer descriptor from the reassembly buffer pool. If this is not the first cell of a CPCS-PDU, the SARA-2 reads the partial CRC information from the Reassembly VC structure as well. 6. The PCI bus interface makes a request to the PCI bus. When the bus request is granted, the DMA controller transfers the 48-byte AAL5 payload from the cell buffer to the host buffer, computing AAL5 CRC as the data is transferred. If the host buffer is filled, the current descriptor is appended to the end of the linked list of descriptors already used for this CPCS-PDU. The SARA-2 fetches a new descriptor from the reassembly buffer pool and continues with the transfer. The partial CRC is then written to the Reassembly VC structure. The cell buffer is then released to the free cell buffer pool. 7. When a cell has been transferred, the size and host buffer address in the buffer descriptor are updated. When the last cell of a CPCS-PDU is transferred, the AAL5 CRC and length fields are verified and errors, if any, flagged. 8. When the reassembly of a CPCS-PDU is complete, the SARA-2 sends an indicate message for each used buffer, with or without an interrupt, releasing the buffer(s) associated with the CPCS- PDU. The used buffer descriptors are copied to the indicate ring for host processing. The buffer descriptors are released for reuse TXC SCDA-PS1

19 2.4.1 Host Buffering Recycling in Reassembly Process Host buffers must be available to SARA-Lite in order to reassemble the received cells into packets. The request to the host for the free buffers is made via the Service Interface. Figure 17 shows the processing of the Buffer Descriptor by SARA-2 after the host buffer is filled. * RISC processes the Buffer Descriptor after the host buffer is filled. * SARA-2 moves filled BD to Indicate MSG pool. * Update Indicate MSG tail pointer. * DMAI copies contents of Indicate MSG Descriptor to Indicate Ring (IR). * Update Indicate MSG pool head pointer. * Update IR tail register. * Release Indicate MSG descriptor to MSG pool; update head register of MSG pool. * Host processes message at IR. * Update IR head register. * Host assigns message buffer to Reassembly buffer pool from MSG pool. * Update the head of Reassembly buffer pool. * Update the head of MSG pool. Figure 17. SARA-2 Reassembly Processing of Buffer Descriptor TXC SCDA-PS1

20 The host provides free buffers to the SARA-Lite buffer pool, which are used to send the cells into the host memory. After the cells are reassembled in host memory, SARA-Lite notifies the host (via the indicate ring) that those buffers are not needed for reassembly and the data can now be manipulated in any form required. Figure 18 shows a summary of the host buffer recycling process. Reassembly Buffer Pool Buffer Descriptor Request Ring MSG Pool RISC Indicate MSG Pool Indicate Ring Figure 18. Host Buffer Recycling in SARA-Lite TXC SCDA-PS1

21 3.0 SARA-Lite TRAFFIC SCHEDULING AND HASH MECHANISMS 3.1 TRAFFIC SCHEDULING SARA-2 incorporates a traffic scheduler which schedules the transmission of CBR, VBR and UBR cell streams on a per-virtual-circuit basis. SARA-Lite uses a table-based scheduler to provide precise control over the granularity of rates requested per CBR/VBR virtual circuit. The table-based approach provides adequate flexibility in the multiplexing of different virtual circuits while achieving desired burst size and sustainable cell rate allocated to each virtual circuit. The traffic shaping hardware in the device traverses the Rate Control Table to schedule cell transmissions. The Rate Control Table is a linear array of 32-bit entries, as illustrated in Figure 19. Each entry points to either a segmentation VC structure entry or a NULL entry. During segmentation, the Rate Control Table is traversed sequentially and each entry is provided service according to the control bits. Each entry in the table corresponds to a CBR or VBR virtual circuit. When an entry in the Rate Control Table is serviced, one or more ATM cells (based on the burst size in the Segmentation VC structure) can be sent from that virtual circuit. A single virtual circuit can occupy from zero to all the table s slots. When more than one entry in the Rate Control Table may point to the same Segmentation VC structure entry, multiple bursts of cells can be sent for that virtual circuit in a single traversal of the Rate Control Table. The hardware cycles through the Rate Control Table entries endlessly, one slot per one or more cell times, transmitting one or more cells for the virtual circuit named in the slot. The 3-bit control field of the RCT entry determines the action to be taken, which can be one of the following: a) send one (or more) cells from a particular virtual circuit (identified in bits 0-23 of the RCT entry) b) jump to another location in the RCT c) transmit a null cell Command Reserved Pointer to Segmentation VC structure Entry 1 Pointer to Segmentation VC structure Entry 6 Pointer to Segmentation VC structure Entry n NULL 000 Jump to Beginning of Table Figure 19. SARA-Lite Rate Control Table Circular Linked List of CBR/VBR Virtual Circuits SARA-Lite maintains a separate doubly-linked list of active UBR virtual circuits as shown in Figure 20. The traffic scheduler traverses the Rate Control Table and the UBR circular list in order to select the candidate virtual circuits for segmentation. The Rate Control Table is used to schedule CBR and VBR traffic, while the UBR circular list is used to schedule UBR traffic. Note that the UBR circular list is a simple linked list of active UBR VCs that may have cells to transmit TXC SCDA-PS1

22 UBR Linked List VC1 VC2 VCn Figure 20. Circular Linked List of UBR Virtual Circuits During segmentation, the RCT is traversed sequentially. At each cell slot time the RCT is accessed and the operation identified in the RCT entry (that the scheduler is pointing at, at that time) is performed. At the next cell slot time the contents of the next RCT entry are investigated. Note that jump operations do not require a cell slot time to complete, and can be considered to take place instantly. Since the RCT is traversed in a cyclic fashion, the granularity of each virtual circuit in the RCT is equal to the total line rate (say 155 Mbit/s) divided by the total number of cells (including burst size) allocated to all entries in the table (NCELLTOT). Note that the number of entries in the RCT is programmable and can have a maximum of 64,000 (thereby yielding a per VC granularity of approximately 2 kbit/s, or less if VBR VCs are present). By the same token, the amount of bandwidth allocated to a specific VC is equal to the total line rate divided by NCELLTOT, and then multiplied by the number of entries and associated burst sizes in the RCT that have been assigned to that VC. Hence, for the case of CBR connections, the number of VC entries and the size of the RCT are shaped according to the PCR traffic parameter. The "gap" between the RCT entries allocated to a certain VC with PCR = 1/T is made to be equal to T. It is a bit more complex for the VBR case. Here the PCR, SCR and MBS should be taken into consideration. The entries in the RCT are allocated according to the MBS, and they are spaced by a gap equal to T, i.e. if the MBS = 3 then 3 VC entries are filled in the RCT, and the gap between the entries is T (where PCR = 1/T). Also the bursts have to be separated by leaving a gap of Ts, where SCR = 1/Ts. Note also, that for the case of bursty traffic, there exists a field specified in the Segmentation VC structure called "Burst Size" that allows a certain number of cells to be transmitted back to back. This avoids allocating separate entries in the RCT to reproduce bursts, thereby simplifying the RCT set-up. A UBR virtual circuit is serviced when the CBR or VBR virtual circuit pointed to by the Rate Control Table does not have cells to send. A UBR virtual circuit may also be served if a NULL entry is encountered in the Rate Control Table. The hardware traffic scheduler continuously scans the UBR linked list of virtual circuits to identify a UBR virtual circuit that has data ready for segmentation TXC SCDA-PS1

23 3.2 HASH MECHANISM The hashing algorithm is used to locate the VC state information required for reassembly of received cells. It does this by indexing the entries of the Reassembly Hash Table in the control memory. Such entries contain pointers to chains of Reassembly VC structure entries. Figure 21 shows the Reassembly Hash Table. Pointer to first Reassembly VC Structure Entry in Hash Bucket Chain # 1 Pointer to first Reassembly VC Structure Entry in Hash Bucket Chain # 2 Pointer to first Reassembly VC Structure Entry in Hash Bucket Chain # 3 Pointer to first Reassembly VC Structure Entry in Hash Bucket Chain # (n-1) Pointer to first Reassembly VC Structure Entry in Hash Bucket Chain # n Figure 21. Reassembly Hash Table Consider the easier case, whereby every entry in the Hash Control Table points to a single Reassembly VC structure entry. A Reassembly VC structure contains all information relevant to a particular VC; such information is needed whenever a new cell is received, in order to perform the appropriate AAL functions, to place the cell in the appropriate host memory location, etc. As soon as a new ATM cell is received its header is isolated and is passed through the Hash Computation Logic. Here the VP and VC fields are examined in order to determine the index of the Hash Control Table which contains the pointer to the VC structure associated with that cell. However, several Reassembly VC structures can be "grouped" and linked in a (hash bucket) chain, so that they can be accessed by a single entry in the Hash Control Table. This mechanism enables memory space vs. search time trade-off. The hashing computation logic can be customized to implement this feature, by modification of the HLMASK1 and HLMASK2 fields. The index generated by the hashing logic is used to read the Hash Control Table entry, which points to a chain of Reassembly VC structure entries. This chain is traversed until a match is found between the VP/VC field of the received ATM cell and that contained in the Reassembly VC structure entry. Figure 22 describes the Hash Index computation logic TXC SCDA-PS1

24 23 VPI(7:0) HLCSR VCI(15:0) shift 15 0 VCI(15:0) & 15 0 HLMASK2 & 15 0 HLMASK1 Exclusive-OR gates & 15 0 HLIMASK 15 0 Hash Index Note: "&" indicates 16 two-input AND gates operating on the corresponding bits of the registers or gates immediately above and below it, with the 16-bit result passed downwards. Figure 22. Hash Index Computation Logic TXC SCDA-PS1

25 4.0 AAL0 OR RAW CELLS SUPPORT The SARA-2 supports both 48-byte and 64-byte mode for AAL0 traffic. On the transmitting side: If the traffic is AAL0, and the bit FCT in the segmentation VC structure is set, then the entire cell buffer is copied "as is" from the host buffer space. If the bit FCT is "0", the 48-byte cell payload is copied in from the external host buffer. The cell buffer format is shown in Figure Reserved (32 bits) Unused (32 bits) Unused (32 bits) ATM header (32 bits) Payload bytes 0-3 Payload bytes Payload bytes Figure 23. Cell Buffer Format On the receiving side: The complete 64-byte cell buffer is transferred to the host memory buffer if the bit FCT in the reassembly VC structure is set. Otherwise, the 48-byte cell payload is transferred to the host buffer TXC SCDA-PS1

26 5.0 FRAME RELAY SERVICE/ATM INTERWORKING Frame Relay Service (FRS) is now in widespread use as a technology for virtual networking. However, most of the backbone network is migrating towards an ATM-based transport structure operating at 155 Mbit/s or higher over SONET/SDH systems. ATM is a cell-based technology with a fixed length of 53-bytes per cell which permits use of an optimized switch architecture. This optimization allows switching cells at a much higher speed than variable length packet switching schemes. Also, ATM provides the possibility for mixing different types of traffic such as voice, data, and video into a single network. However, due to the presently installed base of Frame Relay networks, it is possible to take advantage of that infrastructure by providing interworking solutions between Frame Relay networks and ATM networks. Network A Network B FR-CPE IWF IWF FR-CPE FR UNI B-ISDN FR UNI FR-CPE Frame Relay Network IWF ATM Network ATM Network IWF Frame Relay Network FR-CPE FR UNI FR UNI B-CPE B-ISDN UNI B-ISDN UNI B-CPE Figure 24. Frame Relay/ATM Interworking Configurations The Frame Relay Forum FRF.5 specifies the interworking scenario between FR and ATM. Figure 24 depicts a generic diagram for the various scenarios connecting FR networks and B-ISDN/CPE via B-ISDN networks. ITU-Recommendation I.555 specifies two distinct scenarios: 1. Connection of two FR networks/cpe using B-ISDN 2. Connection of an FR network/cpe with a B-ISDN/CPE using B-ISDN. In these scenarios, the interworking function (IWF) between Frame Relay and ATM clouds will use a SAR device to segment and reassemble frames to/from cells TXC SCDA-PS1

27 5.1 NETWORK INTERWORKING FUNCTIONS The Frame Relay Service is a connection-oriented data transport service that provides for the bidirectional transfer of variable length packets for LAN interconnection and terminal-host applications. The Frame Relay Service requires the initial establishment of end-to-end connections, either through provisioning or call setup procedures. An interworking function (IWF) is required when FR packets need to traverse the ATM network. Please refer to the ATM Forum B-ICI document for different network interworking scenarios and the functionality of the IWF. This section discusses the functional mapping between FR functions and ATM functions. IWF IWF FR ATM FR user user upper layers Q.922 core Q.922 core FR-SSCS CPCS SAR ATM ATM FR-SSCS CPCS SAR ATM Q.922 core upper layers Q.922 core PHY PHY PHY PHY PHY PHY PHY Figure 25. Mapping between Two FR networks Using an ATM Network As shown in Figure 25, part of the IWF function is to map the FR service specific convergence layer PDU into ATM cells. The IWF features to be supported are: 1. Variable length PDU formatting and delimiting 2. Error detection 3. Connection multiplexing 4. Loss priority indication 5. Congestion indication (forward and backward) 6. PVC status management TXC SCDA-PS1