A PROGRAMMABLE COMMUNICATIONS PROCESSOR FOR THIRD GENERATION WIRELESS COMMUNICATION SYSTEMS

Transcription

1 A PROGRAMMABLE COMMUNICATIONS PROCESSOR FOR THIRD GENERATION WIRELESS COMMUNICATION SYSTEMS Sridhar Rajagopal and Joseph R. Cavallaro Rice University Center for Multimedia Communication Department of Electrical and Computer Engineering Houston, TX Abstract This paper presents the architecture requirements for a programmable communications processor for baseband signal processing in 3G wireless communication systems. Third generation communication systems are being designed to provide extremely high data rates such as up to 2 Mbps for wireless cellular systems and up to 100 Mbps for wireless LAN systems. Along with these data rates, the standards also specify support for enhanced features such as multiple rates, quality-of-service, multimedia support and flexibility in the algorithms and parameters used in the communication systems. Though these high data rate requirements may be met by application-specific VLSI architectures, the flexibility requirements for 3G systems motivate the need for more programmable solutions. In this work, we show the reasons that current generation programmable processors are inadequate to meet the needs of 3G communication systems. We specify the nature of the workloads and the processing requirements for baseband signal processing for 3G communication systems and present the features that need to be present in a programmable architecture. As an example, we show how bit-level extensions for operations in typical algorithms for estimation and detection in CDMA-based cellular systems can provide significant speedup in data rates. This work was supported in part by Nokia Corporation, Texas Instruments Inc., the Texas Advanced Technology Program under grant , and by NSF under grant ANI

2 I. Need for a programmable communications processor Third generation (3G) wireless communication systems [1] are being designed to provide extremely high data rates such as up to 2 Mbps for wireless cellular systems [2] and up to 100 Mbps for wireless LAN systems [3]. Along with these data rates, the standards also specify support for enhanced features such as multiple rates, quality-of-service and multimedia support. Currently existing standards such as IS-95 narrowband Code Division Multiple Access (CDMA) standard for cellular communications provide only data rates up to 19.2 Kbps. These real-time data rate requirements are generally met by a general purpose processor (GPP) or a digital signal processor (DSP) based solution with co-processor support for algorithms with high computational complexity. Also, the future communication systems have more sophisticated and advanced algorithms [4] requiring greater computational support from the processor along with the 3-4 orders-of-magnitude increase in data rates and low power consumption at the same time. This huge demand on the processor requirements clearly motivates us to seek alternate solutions for future systems. This directly motivates the need for a baseband communications processor. The data rates supported in 3G systems are also dependent on several factors such as the mobility of the users, the congestion in the network, the signal to noise ratio in the channel, etc. A cellular network based on Wideband CDMA [5], for example, provides support for varying data rates from 32 Kbps to 2 Mbps. The operations in the physical layer (baseband) process the information coming from or going to the higher layers. This layer performs the operations of coding and modulation of the information during transmission and the demodulation, detection and decoding during reception. The modulation and coding schemes for the system may need to be changed on a packet-by-packet basis. This means the algorithms implemented for detecting and decoding of the data also need to be flexible in their parameters. For example, a convolutional encoder and its corresponding Viterbi-based decoder may need to change its constraint length (parameter) from 3 to 7, depending on the channel conditions or the modulation scheme may need to be varied from 16-QAM (Quadrature Amplitude Modulation) to 64-QAM to increase the data rates which means a different detection scheme may need to be used. Thus, application specific VLSI architectures, which could potentially meet real-time requirements [6], are not feasible due to the high degree of flexibility needed in 2

3 Wireless Mobile device (Laptop/PDA/Cell phone) Baseband Programmable Communications Processor A/D D/A RF Unit Higher Layers (MAC/Network/Application) Add-on PCMCIA Network Interface Card Figure 1: A programmable communications processor. the algorithms used in the wireless communication system. This motivates the need for a programmable 1 communications processor. Since different wireless communication systems such as cellular and LAN systems co-exist, it is conceivable in the future to think of wireless devices that switch between different communication standards [7], depending on the location of the mobile device. This further motivates a programmable communications processor solution as the right approach for implementing future communication systems. A block diagram of a wireless communication system with programmable communications processor is as shown in Figure 1. The baseband signal processing (physical layer) is done in the communications processor and the higher layers such as the MAC layer, network layer, IP and the application layer is done on the host device which may be a laptop, a PDA, a cell phone or any such mobile wireless device. It is assumed that the mobile wireless device contains software capable of programming the baseband communications processor. This software is resident on the host. This software will use the information from the higher layers to program the communications processor with the required parameters. II. Nature of communication workloads Having motivated the need for a programmable communications processor, we now discuss the features needed in the architecture of the processor to provide real-time support for wireless communication algorithms. Based on a study of typical and advanced algorithms used and proposed for communication systems, we now present what we believe is a good description of the workload and architecture requirements Here, programmable refers only to flexibility and encompasses reconfigurable architectures as long as they can be reprogrammed without having to break the communication link. 3

4 for wireless communication algorithms. 1. Low but variable precision support Low fixed-point precision is sufficient for most operations in the communications processor. Modulation using BPSK (Binary Phase Shift Keying with 1 communication bit per symbol), for e.g, used in the IS-95 standard, transmits bits which can be represented as +1 or -1 (or re-encoded as 0 and 1 and needing just a single bit precision). Advanced modulation schemes can be encoded to use around 2-6 bit precision to represent the data. The input precision available is also restricted by the use of A/D and D/A converters between the communications processor and the RF unit. A floating point unit is not be required as a fixed-point implementation [6] of the algorithms can attain floating point precision and a floating point unit has significantly higher area and power requirements. However, depending on the modulation scheme and the algorithms used, the precision requirements change at different parts of the computations. But, the maximum precision needed does not typically increase beyond 16 bits. The communications processor should be able to re-configure its hardware to perform efficiently with limited and variable precision [8]. 2. Matrix based computation support Since most of the estimation, detection and decoding schemes involve searching for the transmitted sequence, the solutions for the algorithms at the receiver typically are matrix/vector-based. Though this coarse-grained parallelism can be exploited with parallel hardware units, the challenge is to perform parallel operations efficiently for all algorithms with low overhead. Matrix operations are also memory-intensive. The memory should be insensitive to the strides of the data access, especially if matrix transpositions need to be calculated as accessing memory in column major order could potentially mean hits to the same bank. Hence, a multiple functional unit processor with a stride insensitive memory system [9] and a large memory bandwidth is needed. 3. Complex valued arithmetic support Operations on complex-valued arithmetic is common in most wireless communication algorithms. This needs to be well supported by the communications processor. There have been DSP and GPP instructions for aligning and shuffling the real and imaginary parts [10] in computations such as the 4

5 FFT. However, typically the support for complex arithmetic is done in software and the real and imaginary parts are computed in parallel in hardware. 4. High I/O bandwidth The high data rate requirements in 3G communication systems implies that a high I/O bandwidth is needed between the communication processor and the RF and between the communication processor and the host. 5. Special instructions for critical operations The receiver complexity is much higher than the transmitter for wireless communication systems. The data transmitted over the wireless channel suffers from the effects of the wireless channel such as path loss, fading due the mobility of the user, multipath reflections and interference from other users. Hence, the receiver needs to estimate, detect and decode the data transmitted over the wireless channel. Special instructions or functional units that can accelerate the critical and computationintensive operations of estimation, detection and decoding need to be investigated and provided in the communications processor. 6. Power down modes Power is a major consideration in the design of such a communications processor. The power consumption of the digital processing in current generation communication systems is almost equal to the power consumed by the RF units. The communications processor should not only be able to process data in Mbps but also should be power efficient. If any of the functional units in the processor are idle, there should be support for power down modes. The processor should also save power during idle periods when there is no wireless transmission or reception. III. Example: Support for bit-level operations We now present an example to show how support for bit-level operations could be useful for estimation and detection algorithms for BPSK modulation based on the IS-95 CDMA standard. Let us consider a typical Sun UltraSPARC or Intel-based GPP such as the IA-64 providing support for multimedia extensions [11, 12]. The instruction set extension for performing integer-bit multiplications is as shown in Figure 2. 5

6 64-bit Register D[i][j] 64-bit Register r[j] +/- 8 +/- 8 8-bit Control Register b[i] 8 64-bit Register D[i][j] Figure 2: 8 Integer - Bit Multiplications in Parallel Integer - bit multiplications are common in operations such as cross-correlation and multi-user detection for BPSK systems. This can be illustrated with the help of an example for cross-correlation. Consider where and are short integers(8 bits) and is bit-wide (+1 or -1 represented as 1 or 0). If the single bit is replicated and stored in the special purpose 8-bit register, 8 operations can be performed in parallel in a single cycle, based on the sign of the bit. This is in contrast to current DSP or GPP architectures without this extensions, where this operation would be a branch for addition or subtraction based on the value of the bit. This limits exploiting the available parallelism. Note that the operation has been made more general to accommodate for multiplications such as!, and hence the single bit has been replicated in this example. Thus, the branching can be avoided and 8 operations can be performed in parallel in a single cycle. This also helps in removing overheads involved in packing and unpacking of bits in the operation, as can be seen for the "# case, where the bits can be utilized directly. Thus, the multiplication by bit vector is done without any additional cycles as opposed to processors with conventional SIMD extensions. Since there are 64 multiplications and 64 additions in the above equation for cross-correlation, there are effectively 16 multiplication operations and 8 addition operations, as 4 multiplications and 8 additions 6

7 can be done in parallel. This gives the cycle count as cycles (assuming 3 cycles for multiplication and a single cycle addition) on a usual SIMD machine. However, this requires only 8*1 = 8 cycles using the proposed instruction as the bit multiplications can be avoided. This implies speedup of around 7X. However, note that this may translate to a higher number when the effect of memory and caches are also factored in or in a lower number if a superscalar architecture is considered. This modification is a realistic and feasible extension of the ADD operations with multimedia extensions as ADD/SUB operations. Though we showed the bit-level extensions as an example for the IS-95 standard, similar low-cost extensions based on [8] can be envisioned for the communications processor. IV. Conclusions In this paper, we have motivated a need for a programmable communications processor for 3G wireless communication systems. We qualitatively describe the nature of the workloads involved for communication algorithms and the features that need to be present in an architecture for such a programmable communications processor. Finally, we present support for bit-level operations in GPP with multimedia extensions as an example to show how such features in a communications processor can greatly improve its performance for wireless communications algorithms. V. Related and Future Work In this paper, we have outlined the needs for a programmable communications processor for 3G communication systems. This work builds on the concept of Software Defined Radios [1, 13] where the goal has been to increasingly shift the processing from the analog RF domain to the digital domain in order to provide greater flexibility. Our work attempts to specify the architecture features needed in the digital hardware that accelerates the implementation of the communication algorithms while retaining the needed flexibility. The paradigm of extensions and co-processor support for current GPPs and DSPs may not be able to extend to the processing requirements of 3G communication systems due to the orders-of-magnitude improvement in performance needed. Though architectures for media and image processing [14] such as the Imagine architecture [15] address similar problems for media and image processing, there has been little or no work in developing the same for wireless communication systems. Reconfigurable architectures such as GARP [16], PipeRench [17], Chameleon [18] etc. have also recently generated a lot of attention for media 7

8 and communication processing. In the final paper, we will explore these different existing programmable architectures and the modifications that can be made to these architectures to enhance their suitability for 3G wireless communication systems. References [1] Q. Bi, G. I. Zysman, and H. Menkes, Wireless Mobile Communications at the Start of the 21st Century, IEEE Communications Magazine, vol. 39, no. 1, pp , January [2] M. Zeng, A. Annamalai, and V. K. Bhargava, Recent advances in cellular wireless communications, IEEE Communications Magazine, vol. 37, no. 9, pp , September [3] N. Weste and D. J. Skellerm, VLSI for OFDM, IEEE Communications Magazine, vol. 36, no. 10, pp , October [4] S. Das, S. Rajagopal, C. Sengupta, and J. R. Cavallaro, Arithmetic acceleration techniques for wireless communication receivers, in Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, October 1999, pp [5] Third Generation Partnership Project, [6] S. Rajagopal, S. Bhashyam, J. R. Cavallaro, and B. Aazhang, Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers, Accepted to IEEE Journal in Selected Areas in Communications (JSAC), [7] RENE: Seamless Multitier Wireless Networks for Multimedia Applications, Rice University, [8] S. Balakrishnan and S. K. Nandy, Arbitrary precision arithmetic-simd style, in 11th International Conference on VLSI Design, Chennai, India, January 1998, pp [9] G. S. Sohi, High-Bandwidth Interleaved Memory for Vector Processors - A Simulation Study, IEEE Transactions on Computers, vol. 42, no. 1, pp , January [10] C. Hansen, MicroUnity s MediaProcessor Architecture, IEEE Micro, pp , August [11] M. Trembley, J. M. O Connor, V. Narayan, and L. He, VIS Speeds New Media Processing, IEEE Micro, pp , August [12] A. Peleg and U. Weiser, MMX Technology Extension to the Intel Architecture, IEEE Micro, pp , August [13] J. Mitola, The Software Radio Architecture, IEEE Communications Magazine, vol. 33, no. 5, pp , May [14] P. Ranganathan, S. Adve, and N. P. Jouppi, Performance of image and video processing with generalpurpose processors and media ISA extensions, in 26th International Symposium on Computer Architecture, Atlanta, GA, May 1999, pp [15] S. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. Lopez-Lagunas, P. R. Mattson, and J.D. Owens, A bandwidth-efficient architecture for media processing, in 31st Annual ACM/IEEE International Symposium on Microarchitecture (Micro-31), Dallas, TX, December 1998, pp [16] T. C. Callahan, J. R. Hauser, and J. Wawrzynek, The GARP Architecture and C Compiler, IEEE Computer, pp , April [17] S. C. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, and R.R. Taylor, PipeRench: a reconfigurable architecture and compiler, IEEE Computer, vol. 33, no. 4, pp , April [18] B. Salefski and L. Caglar, Re-configurable computing in wireless, in Design Automation Conference, Las Vegas, NV, June 2001, pp