High-Speed Network Processors. EZchip Presentation - 1

Transcription

1 High-Speed Network Processors EZchip Presentation - 1

2 NP-1c Interfaces Switch Fabric 10GE / N x1ge or Switch Fabric or Lookup Tables Counters SDRAM/FCRAM 64 x166/175mhz SRAM DDR NBT CSIX c XGMII HiGig 10GE MAC PCI 32 x 66MHz Host CPU 36 x190mhz 16 channels SPI GE MAC HiGig XGMII or 10GE / N x1ge 10GE / N x1ge OC192 / 4xOC48 / 16xOC12 EZchip Presentation - 2

3 TOPcore - Super-scalar Architecture Line Switch fabric Control CPU Lookup tables External lookup tables memory TOP modify TOP search TOP resolve TOP search TOP parse NP-1 memories Frame memories Line Switch fabric Control CPU packet flow Four types of TOPs Task Optimized Processors Each tailored for specific tasks EZchip Presentation - 3

4 NP-1 1 Programming Model Single-image programming model Number of TOPs in each pipeline stage is transparent Four independent programs to write No multi-threading H/W auto sync and control of the TOPs Dynamic allocation of packets to TOPs Message and packet pointer passing between TOPs Access arbitration to frame and lookup memories Optimized instruction set 1 TOP instruction ~ 10 RISC instructions Special commands for deep packet processing Auto frame ordering Simple shorter time to market EZchip Presentation - 4

5 Available Sample Applications L2 Switching MPLS LER & LSR VPLS & Draft Martini IPv4 & IPv6 Routing NAT ACL URL Load Balancing More under development... EZchip Presentation - 5

6 Bandwidth to Memory Key performance factor NP-1 integrates multiple embedded memory cores 500 Gbps aggregate bandwidth Lookup tables of all types 4 embedded cores; 256 bit wide each; 1.6M bytes 256 Mbytes additional via external 4 DRAM chips Frame buffers 2 embedded cores; 512 bit wide each; 2M bytes Up to 768 Mbytes additional via QX-1 Traffic Manager Memory cores accessed simultaneously by the TOPs Arbitration transparent to user EZchip Presentation - 6

7 NP-1 1 Classification Perform lookups for diverse applications, e.g. VLAN/L2/MPLS/IPv4/IPv6 switching and routing ACL and policy L5-7 web switching/firewalls/storage gateways Enabled through Unique integrated TOPsearch engines Patented search algorithms High-bandwidth embedded DRAM Large external DRAM EZchip Presentation - 7

8 NP-1 1 Classification (cont.) 4 DRAM chips provide 256M byte available for lookup tables Direct, Hash, Tree Millions of entries per table Flexible, Long keys and results (associated info) Reduce system chip-count,power dissipation, cost by ~80% Also reduce board size, complexity, power supplies, cooling Increase system Time IN Market Large memory headroom available e.g. IPv6 router, 512K routes and 512K flows: 85% headroom No hardware changes to support new applications Simply download new software EZchip Presentation - 8

9 Hash Lookups Fixed length keys e.g. VLAN+DA, MPLS, 5/7 tuple IPv4/IPv6 flows Programmable keys per table, up to 38 Bytes Programmable result (associated info.) per table, up to 96 Bytes, more via concatenation Multiple hash tables per NP-1 With up to ~50K total entries in embedded memory With 2M (or more) entries per table in external memory Deterministic lookup performance (patented) Exactly 2 memory accesses to complete search Regardless of table size 10G wire-rate lookups No need to rebuild table after updates (unlike CAM) Always available, no maintenance overhead EZchip Presentation - 9

10 Tree Lookups Support Binary and ASCII based trees Best match e.g. Longest Prefix Match or First match e.g. ACL Variable length keys e.g. LPM IPv4/IPv6 addr. Long text-based keys e.g. URL, cookie, CGI, SCSI commands Flexible wildcards in keys in prefix, suffix, random Programmable entry keys per table, up to frame length Programmable result (associated info.) per table, up to 96 Bytes, more via concatenation EZchip Presentation - 10

11 Tree Lookups Multiple trees per NP-1 With up to ~50K total entries in embedded memory With 2M (or more) entries per tree in external memory Per tree: find Best Match e.g. LPM or First Match e.g. ACL One third the memory accesses vs. Patricia trees (patented) Pipelined searches in both embedded and external memories 10G wire-rate lookups EZchip Presentation - 11

12 Lookup Result / Associated Info. Program any bits/bytes with match result Up to 96 Bytes per entry Can be concatenated for more For any actions, e.g. Forward Filter Police Tag and Modify Report Update table, counters, state Trigger another lookup Retrieve info (addresses, index pointers, etc.) Other EZchip Presentation - 12

13 Stateful Classification NP-1 is a bi-directional 10G device and can generate packets, get replies and maintain state Sees both ingress and egress traffic e.g. syn / syn-ack / ack (TCP 3-way handshake) Uses same 4 DRAM chips for all classification & lookups Lots of headroom for table storage to keep track of sessions and flows Maintains and updates millions of sessions with state Off-loading Host for intensive applications, e.g. NAT, firewall, VPN, load balance, storage, traffic analysis EZchip Presentation - 13

14 Stateful Classification Operation Sessions learned and states updated in session hash table Updates done by TOPs w/o requiring host Up to 5.8M state updates per second Session aging in H/W e.g. idle timeout, or S/W e.g. RST bit on in a TCP session State updates are in order and sequential Packets of same session guaranteed to update state in correct order Packets of same session guaranteed to be matched with an already updated state Dynamically activated only for relevant packets within a flow through microcode EZchip Presentation - 14

15 Stateful Classification Applications NAT: Generate and assign unique port numbers on the fly TCP session set-up & tear-down 3-way handshakes with no host intervention Use L5-7 info. to support applications that Dynamically create multiple sessions e.g. FTP, RPC Dynamically change port numbers e.g. RTSP, H.323 RTP/RTCP Keep IP Addresses in payload e.g. HTTP Detect events, issue alerts and log parameters Sequence numbers out of allowed range High rate of new sessions being opened EZchip Presentation - 15

16 Counters & Dynamic Allocation Up to 2Mx36bit counters, implemented in SRAM Addressing for up to 8M counters 36 / 54 / 72 bit counters Can be updated by any TOP For per-flow statistics, SRTCM/TRTCM token buckets etc. Allocating & Recycling counters In H/W, wire-speed, w/o requiring micro-code or host Auto allocation & association with newly learned flows Auto recycling upon aging of flows Read/modify/write in a single instruction Add/subtract any 16 bit value Dynamic allocation and recycling of indices E.g. for NAT TCP port allocation In H/W, wire-speed, w/o requiring micro-code or host Auto allocation & association with newly learned flows EZchip Presentation - 16

17 Text String Processing No limitation to how deep the packet can be looked into Special SCAN block for string parsing any character can be specified as a delimiter up to 16 delimiters can be defined list of valid delimiters specified for each scan scanning be done forwards and backwards 8-character key text CAM with wildcards and selective case sensitivity EZchip Presentation - 17

18 Per-flow Rate Control NP-1 1 Integrated QoS Features Rate counters implement token bucket SRTCM/TRTCM To Switch Fabric: Virtual Output Queues: Prevent head of line blocking across switch fabric 1024 unicast queues; 8 multicast queues 8 priorities x 128 switch-fabric dest. (e.g. line-cards) or 4 x 256 To Links: 8 queues per 10GE port 64 queues per SPI4.2 port (e.g. 16 x 1GE ports, 4 priorities each) Strict priority Weighted Round Robin (WRR) RED, WRED, tail drop EZchip Presentation - 18

19 Implementation with TeraChip SF Example: 160Gbps solution Line Card Switch Fabric Card 10x1GE VSC 7321 SPI4.2 EZchip NP-1c CSIX TeraChip TCI1x TeraChip TCF16x10 TeraChip TCF16x10 10GE VSC 7321 SPI4.2 EZchip NP-1c CSIX TeraChip TCI1x2 Line Card EZchip Presentation - 19

20 Example: Advanced Services Card 12x1GE BCM Line Card Switch Fabric Card 12x1GE 5690 BCM 5690 XAUI BCM BCM BCM 5670 EZchip NP-1c XGMII HiGig BCM 8011 Services Card EZchip Presentation - 20

21 Example: Stand-alone alone (pizza) Solution 10x1GE PM 3388 SPI4.2 EZchip NP-1c XGMII HiGig BCM 5671 XAUI 10GE EZchip Presentation - 21

22 EZdesign Software Toolset Simulator Clock accurate NP-1 target simulation Assembler + Preprocessor Support extensive macro language C compiler Debugger Break points, step, memory viewers Performance charts, board and NP-1 viewer Frame Generator Layers 2-7 Random, fixed values, erroneous frames Structure Generator Direct tables, hash, trees Enables structure creation based on frame stream EZchip Presentation - 22

23 EZdriver Control Processor API Enhanced API SW development abstraction layer NP-1 initialization Configuration Loading TOPs microcode & lookup structures Host frame handling, send & receive Lookup tables updates Statistics retrieval Runs under VxWorks, Linux, NT/2000 EZchip Presentation - 23

24 EZdesign Development Environment Single Board Computer Host apps EZdriver VxWorks Simulator Compiler Debugger Generator PCI Evaluation Board Loopback 2 x Eval Boards To Switch Fabric NP-1c 10 x 1GE 10GE EZchip Presentation - 24