The Switcherland Distributed Computing System
|
|
- Kathryn McLaughlin
- 6 years ago
- Views:
Transcription
1 4th GI/ITG-Fachtagung Arbeitsplatz-Rechensysteme, Koblenz, ay 21-22, 1997, pp The witcherland Distributed Computing ystem ichaela Blott, Hans Eberle, Erwin Oertli, eter Ryser wiss Federal Institute of Technology Institute of Computer ystems CH-8092 Zurich, witzerland {michaela.blott, eberle, oertli, ryser}@inf.ethz.ch Abstract: witcherland is a distributed computing system optimized for running applications that process continuous data such as video and audio. For this purpose, witcherland implements a communication model that offers quality of service (Qo) for a distributed shared memory architecture. Qo is provided in that memory can be accessed at guaranteed rates and in bounded time. witcherland is based on a scalable interconnection structure that can serve as an I/O interconnection structure of a workstation as well as a network interconnection structure of a cluster of workstations. This paper gives an overview of the architecture and communication model implemented by witcherland and describes the system components we are currently building. Keywords: interconnection structure, quality of service, distributed shared memory, cluster computing. 1 Introduction rocessing continuous data such as video and audio data will become an essential task of future computing systems. Current computing platforms use specialized subsystems for processing such data. The main reasons for using specialized subsystems rather than general-purpose system resources are I/O bandwidth limitations and a lack of real-time guarantees. oon, general-purpose processors will be able to process continuous data in realtime, e.g. to compress and decompress audio and video data [8]. To handle the high data rates of uncompressed video data, interconnection structures with adequate bandwidth are needed. Further, when processing continuous data real-time support in the form of communication channels with guaranteed bandwidths and bounded end-to-end transmission delays is of particular importance. Otherwise, data is produced, transmitted and reproduced at unpredictable rates and with high delay jitter.
2 4th GI/ITG-Fachtagung Arbeitsplatz-Rechensysteme, Koblenz, ay 21-22, 1997, pp odern networking technologies such as asynchronous transfer mode (AT) networks recognize the need for real-time support. Unfortunately, the real-time properties of AT networks do not extend into the workstations connected to them: the real-time guarantees are lost as soon as the data enters the workstations. Therefore, we want to investigate how such guarantees can be provided at all system levels including the hardware and software of the workstations connected to such an interconnection structure. Other projects with goals similar to ours are the Desk-Area Network [5], the calable Coherent Interface [4], Telegraphos [7] and TNet [6]. The common objective of these efforts is scalability and a simple communication model based on a distributed shared memory architecture. We are, however, not aware of any project that offers Qo for such a communication model. This paper is organized as follows. Chapter 2 gives an overview of the main characteristics of witcherland. Chapter 3 gives a status report on its implementation. Finally, Chapter 4 contains the conclusions. 2 Overview Figure 1 shows an example of a distributed computing system based on the witcherland interconnection structure. A port of a switch () can be connected either to a node or to another switch. A node corresponds to a processor () with local memory () or to an I/O device (I/O). Examples of I/O devices are frame buffers and secondary storage devices. As shown, a workstation can contain one or several switches. The switches have two purposes. Within a workstation, they serve as an I/O interconnection structure and, within a cluster, they are used as a network interconnection structure. By using the same interconnection structure for inter- and intra-workstation communication the boundary of the workstation is less clear than in a traditional networked system since the logical grouping of nodes can easily be different from the physical arrangement. By cascading switches any arbitrary topology is possible. The aggregate bandwidth of such a system can be many times the bandwidth of a single switch. By adding switches and links, the aggregate bandwidth can be increased as required. Also, availability can be improved by adding redundant links and switches. The following paragraphs summarize the main characteristics of the witcherland interconnection structure. ore details can be found in [1,2]. calability: In most workstations the components are interconnected by a single shared link or bus. The main attraction of the bus is its low cost and low complexity thanks to the use of a shared medium. The drawbacks are limited extensibility and scalability. The maximum number of nodes is fixed and only relatively short distances can be spanned. These limitations become even more evident at high speeds due to the electrical properties of busses. Further, the bandwidth is fixed and cannot be increased when new nodes are added. A possible alternative to a bus is an interconnection structure based on switches. ince such an interconnection structure uses multiple links rather than one shared link, it cannot compete in terms of cost. However, an interconnection structure based on switches is attractive
3 4th GI/ITG-Fachtagung Arbeitsplatz-Rechensysteme, Koblenz, ay 21-22, 1997, pp Figure 1: A Distributed ystem based on the witcherland Interconnection tructure because of its high bandwidth, scalability and availability. Compared with busses, switches provide higher bandwidth because multiple links can be used simultaneously. ince switches can be clustered easily, the aggregate bandwidth can be many times the link bandwidth and also many times the switch bandwidth. Availability is higher for a switch than for a bus since there is no single point of failure. With a bus all communication fails if the shared link fails. If a link of a switch-based interconnection structure fails, typically only a subset of the nodes is affected. Further, redundant links can be added to achieve higher availability. Load/tore Architecture: witcherland implements a load/store architecture. This means that local communication within a workstation as well as remote communication within a cluster of workstations translate to load and store operations. These operations are applied to a distributed memory which resides in a single address space. Compared with message passing, shared memory offers a simpler communication model since the mechanisms to access local and remote memory are the same. With it, the programmer is presented a uniform model for inter- and intra-workstation communication. Of course, the latency differs with local accesses taking a fraction of the time required by accesses to remote memory. ince our interconnection structure is intended for running loosely-coupled distributed applications rather than tightly-coupled parallel applications, there is little hardware support provided for synchronizing processors and keeping memories consistent. The only synchronization primitive implemented in hardware is an atomic compare_and_swap operation. This operation is typically used for implementing critical regions. There is, however, no
4 4th GI/ITG-Fachtagung Arbeitsplatz-Rechensysteme, Koblenz, ay 21-22, 1997, pp hardware support for keeping main memories and cache memories consistent. If memory consistency is required, it needs to be implemented in software. Traffic Classes: imilar to an AT network witcherland distinguishes between constant bit rate (CBR) traffic and variable bit rate (VBR) traffic. The traffic classes differ in the guarantees provided by the switches. For CBR traffic, the switches provide bandwidth guarantees and bounded transmission delays. For VBR traffic, a certain amount of buffering is preallocated in the switches, thereby guaranteeing that cells belonging to this class are never dropped due to buffer overflow. When a switch becomes heavily loaded, the delivery of VBR cells, however, may be arbitrarily delayed without an upper bound while the delivery of CBR cells remains unaffected. Typically, CBR connections are used for transferring continuous data. uch transfers need to be characterized by low latency and little jitter. An example is the transmission of video frames at a given rate. VBR connections are used for transmitting non-continuous data. The transfer of such data is characterized by variable delays. An example might be an interactive application with a user generating requests to read sectors on a disk. In this scenario, data is transmitted in bursts making it difficult to specify any bandwidth and latency requirements. Fixed-size Cells: witcherland transfers data in the form of cells, that is, small packets with a fixed length. The length of a cell is 64 bytes or sixteen 32-bit words. Cells contain one control word, one address word and fourteen data words. The control word specifies the routing path, the traffic class and the type of memory operation while the address and data words make up the actual memory operation. ulticast: ulticast is offered for transferring CBR data from one source node to many destination nodes. It is implemented by the switches in that they can forward data from one input port to multiple output ports. This feature allows to save communication bandwidth when executing applications such as video conferencing. End-to-end Flow Control: ince we limit the diameter of our interconnection structure to about ten switches, flow control is done end-to-end rather than link-by-link. This simplifies the design of the switches significantly since they do not have to be involved in controlling the flow of data. Different mechanisms are used to control the flow of CBR and VBR traffic. Rate-based flow control is used for CBR traffic in that a node may inject data into the interconnection structure at a rate specified for the corresponding connection. Credit-based flow control is used for VBR traffic in that a node injects data as long as the buffer space, which was reserved along the path of the connection, has not been used up. A description of how flow control works in detail can be found in [3]. 3 Implementation We are currently working on a prototype system consisting of switches, processor nodes, frame buffer nodes, disk nodes, audio/video input/output nodes and standard workstations connected through CI adapters. We use off-the-shelf components only and, in particular,
5 4th GI/ITG-Fachtagung Arbeitsplatz-Rechensysteme, Koblenz, ay 21-22, 1997, pp field-programmable gate arrays since rapid prototyping and flexibility are our main concerns. witch: The implemented prototype switch supports four ports. Each port connects to a 266 bit/s full-duplex serial link. Deducting the overhead of the 8B/10B encoding scheme [9] used for transmitting data over the links the switch provides a bandwidth of 0.85 Gbit/s. The links use shielded twisted-pair wiring and can span distances of up to 50 m. Logically, the implementation of the switch represents a non-blocking crossbar switch with output buffering. The switching fabric and output buffers provide enough bandwidth so that data is never lost due to congestion. rocessor Node: The processor node consists of a I R4700 CU, synchronous DRA to reduce memory access time and serial interfaces for connecting a keyboard, a mouse and other devices. Its link interface provides support in hardware for efficiently handling remote load and store operations. Frame Buffer Node: In addition to a bitmap memory and display refresh controller, this node provides hardware support for clipping and windowing. This feature will, for example, allow direct transfer of multiple video streams between sources of video data and frame buffers without the need for processor intervention. Disk Node: The disk node is based on the processor node which, for this purpose, is extended with a CI interface. We use audio/video hard disk drives which allow tighter control of access times than traditional drives. To complement the real-time guarantees of the interconnection structure, the disk node will allow disk data to be accessed at guaranteed rates. CI Adapter: The CI adapter connects a C or workstation based on the CI bus to the witcherland interconnection structure. It is designed to support the full link bandwidth, i.e. it can simultaneously receive and transmit data at 266 bit/s. With it, witcherland can also be used as a high performance cluster interconnection structure for commercial platforms. Audio/Video Input Node: The audio/video input node digitizes analog audio and video signals and sends the corresponding digital signals to a witcherland link. The video input signal can be taken from up to three different external sources or an on-board TV tuner. ultichannel Audio Input/Output Node: This node simultaneously samples eight audio input channels and plays back two audio channels. The corresponding digital signals are sent and received by a witcherland link. The analog signals are sampled at a rate of 44.1 khz and quantized at 18 bit/sample. EG-2 Decoder Node: The EG-2 decoder node inputs a EG-2 encoded stream from a witcherland link, decodes it and outputs it either as an analog TV baseband signal available at a board connector or as a digital signal sent to the link. 4 Conclusions
6 4th GI/ITG-Fachtagung Arbeitsplatz-Rechensysteme, Koblenz, ay 21-22, 1997, pp To process continuous data such as video and audio data, real-time support is required at all system levels. odern local area networks, such as AT networks, provide support for processing such data in the form of connections with guaranteed bandwidths and bounded delays. These guarantees, however, do not extend into current workstations. witcherland fills this gap. The presented interconnection structure offers high bandwidth and support for processing continuous data. It is the basis for a uniform treatment of continuous and noncontinuous data. Video and audio data will eventually become standard data types and, therefore, need to be able to pass through a system by using standard communication channels. witcherland provides a uniform communication model for a distributed computing environment. hysically, uniformity is achieved in that the interconnection structure can be used not only for connecting the components of a workstation but also for interconnecting a cluster of workstations. In terms of the programming model, uniformity is provided in that all nodes are part of a single address space, and there is no distinction between local and remote memory accesses. References [1] H. Eberle, A calable Interconnect for Distributed ultimedia ystems. 2nd IATED/I Int. Conference on Distributed ultimedia ystems and Applications, tanford, CA, August 7-9, 1995, pp [2] H. Eberle, witcherland - A calable Interconnection tructure for Distributed Computing. 3rd Int. Conf. of the Austrian Center for arallel Computation, Klagenfurt, eptember 22-25, In L. Böszörmenyi, Editor, arallel Computation, Lecture Notes in Computer cience, vol. 1127, pringer-verlag, 1996, pp [3] H. Eberle, E. Oertli, Flow Control in the witcherland Interconnection tructure, ICE 96, 11th Int. Conference on ystems Engineering, Las Vegas, July 9-11, [4] D. Gustavson, The calable Coherent Interface and Related tandard rojects. IEEE icro, vol. 12, no. 1, February 1992, pp [5]. Hayter, D. cauley, The Desk-Area Network. AC Operating ystems Review, vol. 25, no. 4, October 1991, pp [6] R. Horst, TNet: A Reliable ystem Area Network. IEEE icro, vol. 15, no. 1, February 1995, pp [7]. Katevenis, Telegraphos: High-peed Communications Architecture for arallel and Distributed Computer ystems. Technical Report 123, Foundation for Research and Technology, Heraklio, Crete, [8] R. Lee, Accelerating ultimedia with Enhanced icroprocessors. IEEE icro, vol. 15, no. 2, April 1995, pp [9] A. Widmer,. Franaszek, A DC-Balanced, artioned-block, 8B/10B Transmission Code, IB Journal on Research Developments, vol. 27, no. 5, eptember 1983, pp
A Scalable Multiprocessor for Real-time Signal Processing
A Scalable Multiprocessor for Real-time Signal Processing Daniel Scherrer, Hans Eberle Institute for Computer Systems, Swiss Federal Institute of Technology CH-8092 Zurich, Switzerland {scherrer, eberle}@inf.ethz.ch
More informationNOW Handout Page 1. Recap: Gigaplane Bus Timing. Scalability
Recap: Gigaplane Bus Timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Address Rd A Rd B Scalability State Arbitration 1 4,5 2 Share ~Own 6 Own 7 A D A D A D A D A D A D A D A D CS 258, Spring 99 David E. Culler
More informationNon-Uniform Memory Access (NUMA) Architecture and Multicomputers
Non-Uniform Memory Access (NUMA) Architecture and Multicomputers Parallel and Distributed Computing Department of Computer Science and Engineering (DEI) Instituto Superior Técnico February 29, 2016 CPD
More informationComputer Networks and reference models. 1. List of Problems (so far)
Computer s and reference models Chapter 2 1. List of Problems (so far) How to ensure connectivity between users? How to share a wire? How to pass a message through the network? How to build Scalable s?
More informationLearning Curve for Parallel Applications. 500 Fastest Computers
Learning Curve for arallel Applications ABER molecular dynamics simulation program Starting point was vector code for Cray-1 145 FLO on Cray90, 406 for final version on 128-processor aragon, 891 on 128-processor
More informationEECS 122: Introduction to Computer Networks Switch and Router Architectures. Today s Lecture
EECS : Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering and Computer Sciences University of California, Berkeley Berkeley,
More informationGeneric Architecture. EECS 122: Introduction to Computer Networks Switch and Router Architectures. Shared Memory (1 st Generation) Today s Lecture
Generic Architecture EECS : Introduction to Computer Networks Switch and Router Architectures Computer Science Division Department of Electrical Engineering and Computer Sciences University of California,
More informationNon-Uniform Memory Access (NUMA) Architecture and Multicomputers
Non-Uniform Memory Access (NUMA) Architecture and Multicomputers Parallel and Distributed Computing Department of Computer Science and Engineering (DEI) Instituto Superior Técnico September 26, 2011 CPD
More informationNon-Uniform Memory Access (NUMA) Architecture and Multicomputers
Non-Uniform Memory Access (NUMA) Architecture and Multicomputers Parallel and Distributed Computing MSc in Information Systems and Computer Engineering DEA in Computational Engineering Department of Computer
More informationECE 697J Advanced Topics in Computer Networks
ECE 697J Advanced Topics in Computer Networks Switching Fabrics 10/02/03 Tilman Wolf 1 Router Data Path Last class: Single CPU is not fast enough for processing packets Multiple advanced processors in
More informationQoS-Aware IPTV Routing Algorithms
QoS-Aware IPTV Routing Algorithms Patrick McDonagh, Philip Perry, Liam Murphy. School of Computer Science and Informatics, University College Dublin, Belfield, Dublin 4. {patrick.mcdonagh, philip.perry,
More informationTopic 4a Router Operation and Scheduling. Ch4: Network Layer: The Data Plane. Computer Networking: A Top Down Approach
Topic 4a Router Operation and Scheduling Ch4: Network Layer: The Data Plane Computer Networking: A Top Down Approach 7 th edition Jim Kurose, Keith Ross Pearson/Addison Wesley April 2016 4-1 Chapter 4:
More informationThree basic multiprocessing issues
Three basic multiprocessing issues 1. artitioning. The sequential program must be partitioned into subprogram units or tasks. This is done either by the programmer or by the compiler. 2. Scheduling. Associated
More informationOceanStor 9000 InfiniBand Technical White Paper. Issue V1.01 Date HUAWEI TECHNOLOGIES CO., LTD.
OceanStor 9000 Issue V1.01 Date 2014-03-29 HUAWEI TECHNOLOGIES CO., LTD. Copyright Huawei Technologies Co., Ltd. 2014. All rights reserved. No part of this document may be reproduced or transmitted in
More informationScalable Multiprocessors
arallel Computer Organization and Design : Lecture 7 er Stenström. 2008, Sally A. ckee 2009 Scalable ultiprocessors What is a scalable design? (7.1) Realizing programming models (7.2) Scalable communication
More informationMaster Course Computer Networks IN2097
Chair for Network Architectures and Services Prof. Carle Department of Computer Science TU München Master Course Computer Networks IN2097 Prof. Dr.-Ing. Georg Carle Christian Grothoff, Ph.D. Stephan Günther
More informationAsynchronous Transfer Mode
ATM Asynchronous Transfer Mode CS420/520 Axel Krings Page 1 Protocol Architecture (diag) CS420/520 Axel Krings Page 2 1 Reference Model Planes User plane Provides for user information transfer Control
More informationModule objectives. Integrated services. Support for real-time applications. Real-time flows and the current Internet protocols
Integrated services Reading: S. Keshav, An Engineering Approach to Computer Networking, chapters 6, 9 and 4 Module objectives Learn and understand about: Support for real-time applications: network-layer
More informationReal-Time Protocol (RTP)
Real-Time Protocol (RTP) Provides standard packet format for real-time application Typically runs over UDP Specifies header fields below Payload Type: 7 bits, providing 128 possible different types of
More informationOverview of Networks
CMPT765/408 08-1 Overview of Networks Qianping Gu 1 Overview of Networks This note is mainly based on Chapters 1-2 of High Performance of Communication Networks by J. Walrand and P. Pravin, 2nd ed, and
More informationLecture 9: MIMD Architectures
Lecture 9: MIMD Architectures Introduction and classification Symmetric multiprocessors NUMA architecture Clusters Zebo Peng, IDA, LiTH 1 Introduction A set of general purpose processors is connected together.
More informationMore on LANS. LAN Wiring, Interface
More on LANS Chapters 10-11 LAN Wiring, Interface Mostly covered this material already NIC = Network Interface Card Separate processor, buffers incoming/outgoing data CPU might not be able to keep up network
More informationLecture 9: MIMD Architectures
Lecture 9: MIMD Architectures Introduction and classification Symmetric multiprocessors NUMA architecture Clusters Zebo Peng, IDA, LiTH 1 Introduction MIMD: a set of general purpose processors is connected
More informationMore on IO: The Universal Serial Bus (USB)
ecture 37 Computer Science 61C Spring 2017 April 21st, 2017 More on IO: The Universal Serial Bus (USB) 1 Administrivia Project 5 is: USB Programming (read from a mouse) Optional (helps you to catch up
More informationImplementing RapidIO. Travis Scheckel and Sandeep Kumar. Communications Infrastructure Group, Texas Instruments
White Paper Implementing RapidIO Travis Scheckel and Sandeep Kumar Communications Infrastructure Group, Texas Instruments In today s telecommunications market, slow and proprietary is not the direction
More informationCOMP 249 Advanced Distributed Systems Multimedia Networking. Performance of Multimedia Delivery on the Internet Today
COMP 249 Advanced Distributed Systems Multimedia Networking Performance of Multimedia Delivery on the Internet Today Kevin Jeffay Department of Computer Science University of North Carolina at Chapel Hill
More informationDesign and Performance Evaluation of a New Spatial Reuse FireWire Protocol. Master s thesis defense by Vijay Chandramohan
Design and Performance Evaluation of a New Spatial Reuse FireWire Protocol Master s thesis defense by Vijay Chandramohan Committee Members: Dr. Christensen (Major Professor) Dr. Labrador Dr. Ranganathan
More informationBROADBAND AND HIGH SPEED NETWORKS
BROADBAND AND HIGH SEED NETWORKS LAYERS The function and associated information of the planes is as follows: The reference model is composed of the following planes: Control lane manages the call and connection.
More informationIP Video Network Gateway Solutions
IP Video Network Gateway Solutions INTRODUCTION The broadcast systems of today exist in two separate and largely disconnected worlds: a network-based world where audio/video information is stored and passed
More informationData Center Network Topologies II
Data Center Network Topologies II Hakim Weatherspoon Associate Professor, Dept of Computer cience C 5413: High Performance ystems and Networking April 10, 2017 March 31, 2017 Agenda for semester Project
More informationET4254 Communications and Networking 1
Topic 10:- Local Area Network Overview Aims:- LAN topologies and media LAN protocol architecture bridges, hubs, layer 2 & 3 switches 1 LAN Applications (1) personal computer LANs low cost limited data
More informationArchitecture or Parallel Computers CSC / ECE 506
Architecture or Parallel Computers CSC / ECE 506 Summer 2006 Scalable Programming Models 6/19/2006 Dr Steve Hunter Back to Basics Parallel Architecture = Computer Architecture + Communication Architecture
More informationCSE 123: Computer Networks Alex C. Snoeren. HW 2 due Thursday 10/21!
CSE 123: Computer Networks Alex C. Snoeren HW 2 due Thursday 10/21! Finishing up media access Contention-free methods (rings) Moving beyond one wire Link technologies have limits on physical distance Also
More informationLecture 16: Network Layer Overview, Internet Protocol
Lecture 16: Network Layer Overview, Internet Protocol COMP 332, Spring 2018 Victoria Manfredi Acknowledgements: materials adapted from Computer Networking: A Top Down Approach 7 th edition: 1996-2016,
More informationCS 218 F Nov 3 lecture: Streaming video/audio Adaptive encoding (eg, layered encoding) TCP friendliness. References:
CS 218 F 2003 Nov 3 lecture: Streaming video/audio Adaptive encoding (eg, layered encoding) TCP friendliness References: J. Padhye, V.Firoiu, D. Towsley, J. Kurose Modeling TCP Throughput: a Simple Model
More informationMulti-path Forward Error Correction Control Scheme with Path Interleaving
Multi-path Forward Error Correction Control Scheme with Path Interleaving Ming-Fong Tsai, Chun-Yi Kuo, Chun-Nan Kuo and Ce-Kuen Shieh Department of Electrical Engineering, National Cheng Kung University,
More informationIntel Thunderbolt. James Coddington Ed Mackowiak
Intel Thunderbolt James Coddington Ed Mackowiak Thunderbolt Basics PCI Express and DisplayPort through a single connection made available to external devices. Thunderbolt Basics Developed by Intel and
More informationOutline. Limited Scaling of a Bus
Outline Scalability physical, bandwidth, latency and cost level of integration Realizing rogramming Models network transactions protocols safety input buffer problem: N-1 fetch deadlock Communication Architecture
More informationProtocol Architecture (diag) Computer Networks. ATM Connection Relationships. ATM Logical Connections
168 430 Computer Networks Chapter 11 Asynchronous Transfer Mode Protocol Architecture Similarities between ATM and packet switching Transfer of data in discrete chunks Multiple logical connections over
More informationRECOMMENDATION ITU-R BT.1720 *
Rec. ITU-R BT.1720 1 RECOMMENDATION ITU-R BT.1720 * Quality of service ranking and measurement methods for digital video broadcasting services delivered over broadband Internet protocol networks (Question
More informationDEPARTMENT of. Computer & Information Science & Engineering
CIS-6930: Distributed Multimedia Systems Enhancing aggregate QoS for video streaming Authors: Chung wei Lee, Randy Chow, Jonathan C.L. Liu Aditi Malviya Presented By: Anubha DEPARTMENT of Computer & Information
More informationELEC 691X/498X Broadcast Signal Transmission Winter 2018
ELEC 691X/498X Broadcast Signal Transmission Winter 2018 Instructor: DR. Reza Soleymani, Office: EV 5.125, Telephone: 848 2424 ext.: 4103. Office Hours: Wednesday, Thursday, 14:00 15:00 Slide 1 In this
More informationATM Logical Connections: VCC. ATM Logical Connections: VPC
ATM Logical Connections: VCC Logical Connections in ATM are referred to as virtual channel connections (VCCs). Virtual channel (VC) is a generic term used to describe unidirectional transport of ATM cells
More informationPerformance of a Switched Ethernet: A Case Study
Performance of a Switched Ethernet: A Case Study M. Aboelaze A Elnaggar Dept. of Computer Science Dept of Electrical Engineering York University Sultan Qaboos University Toronto Ontario Alkhod 123 Canada
More informationAn Approach for Enhanced Performance of Packet Transmission over Packet Switched Network
ISSN (e): 2250 3005 Volume, 06 Issue, 04 April 2016 International Journal of Computational Engineering Research (IJCER) An Approach for Enhanced Performance of Packet Transmission over Packet Switched
More informationWilliam Stallings Data and Computer Communications 7 th Edition. Chapter 11 Asynchronous Transfer Mode
William Stallings Data and Computer Communications 7 th Edition Chapter 11 Asynchronous Transfer Mode Protocol Architecture Similarities between ATM and packet switching Transfer of data in discrete chunks
More informationMemory Systems in Pipelined Processors
Advanced Computer Architecture (0630561) Lecture 12 Memory Systems in Pipelined Processors Prof. Kasim M. Al-Aubidy Computer Eng. Dept. Interleaved Memory: In a pipelined processor data is required every
More informationLecture 9: Bridging & Switching"
Lecture 9: Bridging & Switching" CSE 123: Computer Networks Alex C. Snoeren HW 2 due Wednesday! Lecture 9 Overview" Finishing up media access Contention-free methods (rings) Moving beyond one wire Link
More informationCrossbar switch. Chapter 2: Concepts and Architectures. Traditional Computer Architecture. Computer System Architectures. Flynn Architectures (2)
Chapter 2: Concepts and Architectures Computer System Architectures Disk(s) CPU I/O Memory Traditional Computer Architecture Flynn, 1966+1972 classification of computer systems in terms of instruction
More informationMedium Access Protocols
Medium Access Protocols Summary of MAC protocols What do you do with a shared media? Channel Partitioning, by time, frequency or code Time Division,Code Division, Frequency Division Random partitioning
More informationThree parallel-programming models
Three parallel-programming models Shared-memory programming is like using a bulletin board where you can communicate with colleagues. essage-passing is like communicating via e-mail or telephone calls.
More informationIEEE 802 LANs SECTION C
IEEE 802 LANs SECTION C Outline of the Lecture Basic characteristics of LAN Topology Transmission Media MAC IEEE 802 LANs 802.3 - CSMA/CD based (Ethernet) 802.4 Token bus-based 802.5 Token ring-based Comparison
More informationMulti-Processor / Parallel Processing
Parallel Processing: Multi-Processor / Parallel Processing Originally, the computer has been viewed as a sequential machine. Most computer programming languages require the programmer to specify algorithms
More informationTopologies. Maurizio Palesi. Maurizio Palesi 1
Topologies Maurizio Palesi Maurizio Palesi 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and
More informationCSE Introduction to Parallel Processing. Chapter 4. Models of Parallel Processing
Dr Izadi CSE-4533 Introduction to Parallel Processing Chapter 4 Models of Parallel Processing Elaborate on the taxonomy of parallel processing from chapter Introduce abstract models of shared and distributed
More informationNetwork-on-chip (NOC) Topologies
Network-on-chip (NOC) Topologies 1 Network Topology Static arrangement of channels and nodes in an interconnection network The roads over which packets travel Topology chosen based on cost and performance
More informationQuality of Service (QoS)
Quality of Service (QoS) The Internet was originally designed for best-effort service without guarantee of predictable performance. Best-effort service is often sufficient for a traffic that is not sensitive
More informationImproving the quality of H.264 video transmission using the Intra-Frame FEC over IEEE e networks
Improving the quality of H.264 video transmission using the Intra-Frame FEC over IEEE 802.11e networks Seung-Seok Kang 1,1, Yejin Sohn 1, and Eunji Moon 1 1Department of Computer Science, Seoul Women s
More informationCSE 3214: Computer Network Protocols and Applications Network Layer
CSE 314: Computer Network Protocols and Applications Network Layer Dr. Peter Lian, Professor Department of Computer Science and Engineering York University Email: peterlian@cse.yorku.ca Office: 101C Lassonde
More informationBurst-mode Transceivers and Differentiated Classes of Service for PON. Dr. Monir Hossen ECE, KUET
Burst-mode Transceivers and Differentiated Classes of Service for PON Dr. Monir Hossen ECE, KUET 1 Concept of Burst-mode Types of Burst-mode ONU Transmitter ~ ON/OFF with time slot fast ON/OFF is required
More informationCOMPUTER NETWORKS UNIT I. 1. What are the three criteria necessary for an effective and efficient networks?
Question Bank COMPUTER NETWORKS Short answer type questions. UNIT I 1. What are the three criteria necessary for an effective and efficient networks? The most important criteria are performance, reliability
More informationOutline. Distributed Shared Memory. Shared Memory. ECE574 Cluster Computing. Dichotomy of Parallel Computing Platforms (Continued)
Cluster Computing Dichotomy of Parallel Computing Platforms (Continued) Lecturer: Dr Yifeng Zhu Class Review Interconnections Crossbar» Example: myrinet Multistage» Example: Omega network Outline Flynn
More informationChapter 4 Network Layer: The Data Plane
Chapter 4 Network Layer: The Data Plane A note on the use of these Powerpoint slides: We re making these slides freely available to all (faculty, students, readers). They re in PowerPoint form so you see
More informationDynamic Balancing Complex Workload in Workstation Networks - Challenge, Concepts and Experience
Dynamic Balancing Complex Workload in Workstation Networks - Challenge, Concepts and Experience Abstract Wolfgang Becker Institute of Parallel and Distributed High-Performance Systems (IPVR) University
More informationCROSS LAYER PROTOCOL (APTEEN) USING WSN FOR REAL TIME APPLICATION
CROSS LAYER PROTOCOL (APTEEN) USING WSN FOR REAL TIME APPLICATION V. A. Dahifale 1, N. Y. Siddiqui 2 PG Student, College of Engineering Kopargaon, Maharashtra, India 1 Assistant Professor, College of Engineering
More informationCineLink HD-D IP Decoder
CineLink HD-D IP Decoder [product image] We are receiving data on a moment-to-moment basis from all of our programs, and the video wall gives us a snapshot of events happening globally. - Ed Shubert, Senior
More informationATM. Asynchronous Transfer Mode. these slides are based on USP ATM slides from Tereza Carvalho. ATM Networks Outline
ATM Asynchronous Transfer Mode these slides are based on USP ATM slides from Tereza Carvalho 1 ATM Networks Outline ATM technology designed as a support for ISDN Definitions: STM and ATM Standardization
More informationIEEE Time-Sensitive Networking (TSN)
IEEE 802.1 Time-Sensitive Networking (TSN) Norman Finn, IEEE 802.1CB, IEEE 802.1CS Editor Huawei Technologies Co. Ltd norman.finn@mail01.huawei.com Geneva, 27 January, 2018 Before We Start This presentation
More informationNetwork Interface Architecture and Prototyping for Chip and Cluster Multiprocessors
University of Crete School of Sciences & Engineering Computer Science Department Master Thesis by Michael Papamichael Network Interface Architecture and Prototyping for Chip and Cluster Multiprocessors
More information15: OS Scheduling and Buffering
15: OS Scheduling and ing Mark Handley Typical Audio Pipeline (sender) Sending Host Audio Device Application A->D Device Kernel App Compress Encode for net RTP ed pending DMA to host (~10ms according to
More informationOPTIMISING NETWORKED DATA ACQUISITION FOR SMALLER CONFIGURATIONS
OPTIMISING NETWORKED DATA ACQUISITION FOR SMALLER CONFIGURATIONS DAVE BUCKLEY ACRA BUSINESS UNIT, CURTISS-WRIGHT CONTROLS AVIONICS & ELECTRONICS ABSTRACT Network switches are a critical component in any
More informationAdvanced Computer Networks Spring Set #1
Advanced Computer Networks Spring 2019- Set #1 Prof. Zygmunt J. Haas Computer Science Department The University of Texas at Dallas ECSS 4.405 Richardson, TX 75080 http://www.utdallas.edu/~haas/courses/acn
More informationDisk for Real-time Data. Presented at the THIC Meeting at the Sony Auditorium, 3300 Zanker Rd, San Jose CA March 4-5, 2003
Disk for Real-time Data Phil Brunelle Conduant Corporation 1501 S. Sunset St., Suite C, Longmont, CO 80501 Phone:303-485-2721 FAX: 303-485-5104 E-mail: phil@conduant.com Presented at the THIC Meeting at
More informationLocal Area Network Overview
Local Area Network Overview Chapter 15 CS420/520 Axel Krings Page 1 LAN Applications (1) Personal computer LANs Low cost Limited data rate Back end networks Interconnecting large systems (mainframes and
More informationMultimedia. Multimedia Networks and Applications
Course Code 005636 (Fall 2017) Multimedia Multimedia Networks and Applications Prof. S. M. Riazul Islam, Dept. of Computer Engineering, Sejong University, Korea E-mail: riaz@sejong.ac.kr Contents Synchronization
More informationImpact of Network Topology on Anonymity and Overhead in Low-Latency Anonymity Networks
Impact of Network Topology on Anonymity and Overhead in Low-Latency Anonymity Networks Claudia Diaz 1, Steven J. Murdoch 2, Carmela Troncoso 1 1 K.U.Leuven, ESAT/COSIC 2 University of Cambridge / The Tor
More informationCommunication Networks
Communication Networks Chapter 3 Multiplexing Frequency Division Multiplexing (FDM) Useful bandwidth of medium exceeds required bandwidth of channel Each signal is modulated to a different carrier frequency
More informationReal-Time ABR, MPEG2 Streams over VBR, and Virtual Source/Virtual Destination rt-abr switch
Real-Time ABR, MPEG2 Streams over VBR, and Virtual Source/Virtual Destination rt-abr switch Professor of Computer and Information Sciences The Ohio State University Columbus OH 432101-1277 http://www.cis.ohio-state.edu/~jain/
More informationRandomized User-Centric Clustering for Cloud Radio Access Network with PHY Caching
Randomized User-Centric Clustering for Cloud Radio Access Network with PHY Caching An Liu, Vincent LAU and Wei Han the Hong Kong University of Science and Technology Background 2 Cloud Radio Access Networks
More informationLAN Systems. Bus topology LANs
Bus topology LANs LAN Systems Design problems: not only MAC algorithm, not only collision domain management, but at the Physical level the signal balancing problem (signal adjustment): Signal must be strong
More informationINTERNATIONAL STANDARD
INTERNATIONAL STANDARD ISO/IEC 11518-10 First edition 2001-03 Information technology High-performance parallel interface Part 10: 6 400 Mbit/s Physical Layer (HIPPI-6400-PH) Reference number ISO/IEC 11518-10:2001(E)
More information[ 7.2.5] Certain challenges arise in realizing SAS or messagepassing programming models. Two of these are input-buffer overflow and fetch deadlock.
Buffering roblems [ 7.2.5] Certain challenges arise in realizing SAS or messagepassing programming models. Two of these are input-buffer overflow and fetch deadlock. Input-buffer overflow Suppose a large
More informationRelaxation Control of Packet Arrival Rate in the Neighborhood of the Destination in Concentric Sensor Networks
Relaxation Control of Packet Arrival Rate in the Neighborhood of the Destination in Concentric Sensor Networks 1 T.R.Gopalakrishnan Nair (SM-IEEE), 2 R. Selvarani, 3 Vaidehi M. 1 Director Research & Industry
More informationInfiniBand SDR, DDR, and QDR Technology Guide
White Paper InfiniBand SDR, DDR, and QDR Technology Guide The InfiniBand standard supports single, double, and quadruple data rate that enables an InfiniBand link to transmit more data. This paper discusses
More informationAbstract A SCALABLE, PARALLEL, AND RECONFIGURABLE DATAPATH ARCHITECTURE
A SCALABLE, PARALLEL, AND RECONFIGURABLE DATAPATH ARCHITECTURE Reiner W. Hartenstein, Rainer Kress, Helmut Reinig University of Kaiserslautern Erwin-Schrödinger-Straße, D-67663 Kaiserslautern, Germany
More informationCisco Virtualized Workload Mobility Introduction
CHAPTER 1 The ability to move workloads between physical locations within the virtualized Data Center (one or more physical Data Centers used to share IT assets and resources) has been a goal of progressive
More informationOPTIMIZING MOBILITY MANAGEMENT IN FUTURE IPv6 MOBILE NETWORKS
OPTIMIZING MOBILITY MANAGEMENT IN FUTURE IPv6 MOBILE NETWORKS Sandro Grech Nokia Networks (Networks Systems Research) Supervisor: Prof. Raimo Kantola 1 SANDRO GRECH - OPTIMIZING MOBILITY MANAGEMENT IN
More informationI/O Systems. Amir H. Payberah. Amirkabir University of Technology (Tehran Polytechnic)
I/O Systems Amir H. Payberah amir@sics.se Amirkabir University of Technology (Tehran Polytechnic) Amir H. Payberah (Tehran Polytechnic) I/O Systems 1393/9/15 1 / 57 Motivation Amir H. Payberah (Tehran
More informationPrinciples behind data link layer services
Data link layer Goals: Principles behind data link layer services Error detection, correction Sharing a broadcast channel: Multiple access Link layer addressing Reliable data transfer, flow control: Done!
More informationOperating Systems. Lecture 09: Input/Output Management. Elvis C. Foster
Operating Systems 141 Lecture 09: Input/Output Management Despite all the considerations that have discussed so far, the work of an operating system can be summarized in two main activities input/output
More informationModule 16: Distributed System Structures
Chapter 16: Distributed System Structures Module 16: Distributed System Structures Motivation Types of Network-Based Operating Systems Network Structure Network Topology Communication Structure Communication
More informationBasics (cont.) Characteristics of data communication technologies OSI-Model
48 Basics (cont.) Characteristics of data communication technologies OSI-Model Topologies Packet switching / Circuit switching Medium Access Control (MAC) mechanisms Coding Quality of Service (QoS) 49
More informationTHE OSI MODEL. Application Presentation Session Transport Network Data-Link Physical. OSI Model. Chapter 1 Review.
THE OSI MODEL Application Presentation Session Transport Network Data-Link Physical OSI Model Chapter 1 Review By: Allan Johnson Table of Contents Go There! Go There! Go There! Go There! Go There! Go There!
More informationBLM6196 COMPUTER NETWORKS AND COMMUNICATION PROTOCOLS
BLM6196 COMPUTER NETWORKS AND COMMUNICATION PROTOCOLS Prof. Dr. Hasan Hüseyin BALIK (2 nd Week) 2. Protocol Architecture, TCP/IP, and Internet-Based Applications 2.Outline The Need for a Protocol Architecture
More informationDesignCon SerDes Architectures and Applications. Dave Lewis, National Semiconductor Corporation
DesignCon 2004 SerDes Architectures and Applications Dave Lewis, National Semiconductor Corporation Abstract When most system designers look at serializer/deserializer (SerDes) devices, they often compare
More informationDigital Audio and Video in Industrial Systems
Mitsubishi Electric Research Laboratories Cambridge Research Center Digital Audio and Video in Industrial Systems Hugh C. Lauer, Chia Shen, Randy Osborne, John Howard, Qin Zheng, Morikazu Takegaki, Hiromitsu
More informationDigital Asset Management 5. Streaming multimedia
Digital Asset Management 5. Streaming multimedia 2015-10-29 Keys of Streaming Media Algorithms (**) Standards (*****) Complete End-to-End systems (***) Research Frontiers(*) Streaming... Progressive streaming
More informationChapter 15 Local Area Network Overview
Chapter 15 Local Area Network Overview LAN Topologies Bus and Tree Bus: stations attach through tap to bus full duplex allows transmission and reception transmission propagates throughout medium heard
More informationITEC310 Computer Networks II
ITEC310 Computer Networks II Chapter 29 Multimedia Department of Information Technology Eastern Mediterranean University 2/75 Objectives After completing this chapter you should be able to do the following:
More informationChapter 4 NETWORK HARDWARE
Chapter 4 NETWORK HARDWARE 1 Network Devices As Organizations grow, so do their networks Growth in number of users Geographical Growth Network Devices : Are products used to expand or connect networks.
More information