Product Description. Two Type-2 PICs: 4-port Channelized OC12/STM4 and 1-port Channelized OC48/STM16 Nonconcatenated. Features and Benefits

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1 Enhanced IQ PICs Product Overview Service providers and enterprises are constantly required to support higher numbers of customers per interface, which in turn maximizes their revenue potential and reduces operational and capital expenditures for each router deployed. The Juniper Networks Enhanced IQ PIC family is a collection of SONET/SDH, PDH, channelized and non-channelized interfaces that can support large numbers of customers per interface across a broad range of interface types and speeds (from T/E to OC48/STM6) with advanced class-of-service (CoS) capabilities. Product Description The Juniper Networks Enhanced IQ PIC product family is a suite of highly sophisticated hardware and software modules that implement the next generation of class of service, class-based traffic management and high-level channelization capabilities. The product suite consists of ten PICs to meet various speed and density requirements: Seven Type- PICs: -port Channelized OC/STM4, -port clear-channel OC/STM4, -port Channelized OC3/STM, 4-port clear-channel OC3/STM, 4-port Channelized DS3/E3, 4-port clear-channel DS3/E3, and 0-port Channelized E/T PIC Two Type- PICs: 4-port Channelized OC/STM4 and -port Channelized OC48/STM6 Nonconcatenated One Type-3 PIC: 4-port clear channel OC48/STM-6 Juniper Networks innovative Enhanced IQ PIC family extends the latest technical advancements in traffic management technology, allowing service providers and enterprises to meet their most demanding needs in term of cost-effective TDM aggregation. Leveraging Juniper Networks flexible channelization capabilities of the queuing FPGA, the Enhanced IQ PIC family applies a rich set of CoS features and hierarchical Traffic Management capabilities that underpin the assured delivery of high-value multiplay services in both enterprise and service provider environments. The FPGA is software programmable, increasing investment protection by permitting the future addition of new features via new software releases. Features and Benefits Flexible Port Configuration The Enhanced IQ PIC family allows per-port selection of the SONET or SDH framing type, providing customers with the ability to consolidate different access types on the same PIC. SONET/SDH PICs use standard small form-factor pluggable transceiver (SFP) modular optics, which adds another level of flexibility and further simplifies spare management. The PICs also support the full DLCI range along with sparse numbering for maximum ease of operation. Flexible and Dense Channelization Your ideas. Connected. In the case of Channelized PICs, the hardware based Traffic Manager provides deep channelization support of any type of port down to NxDS0 and offers the flexibility of mixing any combination of channel sizes on the same port. By offering an interface that can support a full range of access speeds, service providers and enterprises achieve a great level CapEx and OpEx savings by only needing to deploy one interface for any combination of NxDS0, DS/E, fractional DS/E or subrate DS3 and OC3/STM. The Enhanced IQ PICs multiple levels of channelization enable service providers and enterprises to easily grow subscribers from lower to higher bandwidth speeds without changing interfaces.

2 Advanced Hierarchical Traffic Management The Enhanced IQ PIC family supports the allocation of up to eight queues per channel and features a dual-rate shaper capability (committed and excess) with priority propagation from queues to channel levels across a 3-level hierarchy. Accordingly, the Traffic Manager can deliver differentiated multiplay services with distinct class-of-service requirements while ensuring proper prioritization and fairness among the various services and customers. These hierarchical scheduling 3 capabilities allow enterprises and service providers to efficiently consolidate their access networks and consequently maximize their revenue per port without compromising on the service quality and value. Enhanced Queuing Capabilities with Low Latency Egress Queuing The Traffic Manager supports up to eight queues per channel with five levels of priorities three guaranteed and two excess. An optional Layer (L)-aware rate limit can be enforced on the strict 4 high-priority level to prevent lower priority queues from traffic starvation. These queuing capabilities allow defining a very fine-grained class-of-service model to meet the most stringent multiplay traffic requirements, ensuring that prioritization, delay and jitter characteristics are enforced for each traffic class. Increased Delay Buffers The FPGA is capable of buffering several seconds 5 of traffic. This high level of buffering permits shaping of outgoing traffic on low-speed interfaces with minimal packet loss to meet assured forwarding network traffic requirements like critical file transfers. Enhanced Statistics and Diagnostic The FPGA also provides a complex and granular set of instrumentations and counters, such as L per-queue packet/ byte counters and L per-queue packet/byte drop counters. These features enable superior billing and accounting functionalities and allow statistics to be collected for network design and planning. The Enhanced IQ PIC family also features advanced diagnostics 6 such as far end activation code (FEAC), loopback testing at channel levels and a wide selection of bit error rate test (BERT) patterns for simplifying troubleshooting operations. -port Channelized OC/STM4 -port OC/STM4 -port channelized OC3/STM 4-port OC3/STM 4-port Channelized DS3/E3 4-port DS3/E3 0-port Channelized T/E 4-port Channelized OC/STM4 -port Channelized OC48NC/STM6

3 Specifications Physical (W x H x D) 4 x x 7 in (0.6 x.54 x 7.78 cm) CoS Support Weighted Random Early Detection (WRED) 6 unique drop profiles 7 4 drop precedences Tail queue drop Ingress DSCP rewrite Three levels of hierarchical scheduling with LLQ 8 PQ-MDRR algorithm 8k egress queues MIB Support SNMP information retrievable at all levels of channelization RFC 595 (SONET/SDH MIB) RFC 406 (T/E MIB) RFC 407 (T3/E3 MIB) Encapsulation Point-to-Point Protocol (PPP) MPLS Circuit Cross-connect (CCC) MPLS translational cross-connect (TCC) Frame Relay Frame Relay CCC MLPPP 8 MLFR 8 FRF.5, FRF.6 8 Flexible Frame Relay (not necessary) PPP over Frame Relay 8 Cisco High-Level Data Link Control (chdlc) BERT Support 8 Support at DS0, DS/E, DS3/E3 Default setting is 5- pseudorandom Test patterns configurable to run in framed and unframed mode BERT pattern is transmitted unframed BERT sessions are simultaneous Test patterns configurable per channel Test patterns with bit-error rates from 0 to 0-3 inject, detect and count Test patterns All ones All zeros Alternating ones and zeros (AA/55) :3 or in 4 pattern - bit set in every 4 :7 or in 8 pattern - bit set in every 8 PRBS 9 - (as specified in ITU-T O.53) PRBS - (as specified in ITU-T O.53) PRBS 5 - (as specified in ITU-T O.5/O.53) PRBS 0 - (as specified in ITU-T O.53) PRBS 3 - (as specified in ITU-T O.5/O.53) 3-bit programmable pattern Error insertion at user-defined rate of 0-3 SONET/SDH Features SONET/SDH Features Loopback supported on all interface speeds Remote payload loopback Local line loopback Remote line loopback Each channel can be looped back individually and independently Mapping Granularity: Each DS3/STS is individually configurable SONET scrambler SONET APS CRC: 6 bit and 3 bit SONET error detection: Loss of Light (LOL) Phase Lock Loop (PLL) Loss of Frame (LOF) Loss of Signal (LOS) Severely Errored Framing (SEF) Alarm Indication Signal - Line (AIS-L) Alarm Indication Signal - Path (AIS-P) Loss of Pointer (LOP) Bit Error Rate - Signal Degrade (BERR-SD) Bit Error Rate - Signal Fail (BERR-SF) Remote Defect Indicator - Line (RDI-L) Remote Defect Indicator - Path (RDI-P) Remote Error Indicator (REI) Unequipped (UNEQ) Payload Label Mismatch - Path (PLM-P) Loss of Clock (LOC) Virtual Container Alarm Indication Signal (VAIS) 8 Virtual Container Loss of Pointer (VLOP) 8 Virtual Container Remote Defect Indicator (VRDI) 8 Virtual Container Unequipped (VUNEQ) 8 Virtual Container Mismatch (VMIS) 8 Virtual Container Loss of Clock (VLOC) 8 SDH error detection: Loss of Light (LOL) Phase Lock Loop (PLL) Loss of Frame (LOF) Loss of Signal (LOS) Severely Errored Framing (SEF) Multiplex Section Alarm Indication Signal (MS-AIS) High Order Path Alarm Indication Signal (HP-AIS) Loss of Pointer (LOP) Bit Error Rate Signal Degrade (BERR-SD) Bit Error Rate Signal Fail (BERR-SF) Multiplex Section Far-End Receive Failure (MS-FERF) High-order Path Far-End Receive Failure (HP-FERF) Remote Error Indication (REI) 3

4 Unequipped (UNEQ) High-order Path Payload Label Mismatch Path (HP- PLM) Loss of Clock (LOC) Tributary Unit Alarm Indication Signal (TU-AIS) 8 Tributary Unit Loss of Pointer (TU-LOP) 8 Tributary Unit Remote Defect Indicator (TU-RDI) 8 Tributary Unit Unequipped (TU-UNEQ) 8 Tributary Unit Mismatch (TU-MIS) 8 Tributary Unit Loss of Clock (TU-LOC) 8 DS3/E3 Features DS3 and E3 are selectable on a per-port granularity Framing: M3, C-bit parity, framed clear channel DS3 Scrambling: Digital Link/Quick Eagle Kentrox Larscom ADTRAN Verilink Subrate is supported on DS3 with the following vendor algorithms: Digital Link/Quick Eagle Kentrox Larscom ADTRAN Verilink DS and E interface supports fractional DS/E Loopbacks that are supported: Remote payload loopback Local line loopback Remote line loopback Clocking: Internal and loop DS3 FEAC DS3/E3 Alarms (conformance to ANSI specification T.404) Alarm Indication Signal (AIS) Out Of Frame (OOF); also known as Loss Of Frame (LOF) Loss Of Signal (LOS) Phase-Locked Loop (PLL) Alarm reporting 4-hour history maintained for error statistics and failure counts, 5-minute intervals on all errors Alarm logged in system log file Intervals shown on Command Line Interface (CLI) show command DS3/E3 Error Detection (per-second polling) P-bit Code Violations (PCV) C-bit Code Violations (CCV) Line Errored Seconds (LES) P-bit Errored Seconds (PES) C-bit Errored Seconds (CES) Severely Errored Framing Seconds (SEFS) P-bit Severely Errored Seconds (PSES) C-bit Severely Errored Seconds (CSES) Unavailable Seconds (UAS) Far-end block error (FEBE) Excessive zeroes (EXZ) Far-end receive failure (FERF) CRC errors DS/T Features Framing: Superframe (D4) and Extended Superframe (ESF), framed clear channel Loopback support: Remote payload Local line Remote line Clocking: Internal and loop (clock recovered from network and used for TX) will be supported Default for Channelized T: Internal timing CRC: 6-bit (ESF only) Support sending and receiving inband loopback codes in both framed and unframed mode Framed inband loopback at CSU Framed inband loopback at Smartjack (ANSI) Unframed inband loopback at CSU Unframed inband loopback at Smartjack (ANSI) FDL loopback for T-ESF mode interfaces (ANSI T.403) MTU: 9K T Alarms (conformance to ANSI specification) Alarm Indication Signal (blue) AIS Out Of Frame (red) OOF; also known as Loss Of Frame (LOF) Remote Alarm Indication Signal (yellow) RAIS Alarm reporting 4-hour history maintained for error statistics and failure counts, 5-minute intervals on all errors Error Detection (conformance to ANSI specification) Controlled Slipped Seconds (CSS or CS) Line Errored Seconds (LES) Errored Seconds (ES) Bursty Errored Seconds (BES) Severely Errored Seconds (SES) Severely Errored Framing Seconds (SEFS) Loss Of Signal Seconds (LOS) Loss Of Framing Seconds (LOFS) Unavailable Seconds (UAS) CRC errors 4

5 Agency Approvals Safety EMC UL950 (USA) EN (Europe, derivative of IEC 60950) EN (Europe, special for laser safety) CSA C. No.950 (Canada) AS/NZS (Australia, New Zealand, derivative of IEC 60950) FCC Part 5 Class B (USA) EN 550 Class B (Europe) (colloquially called CISPR ) VCCI Class B (Japan) BSMI Class B (Taiwan) AS/NZ 3548 Class B (Australia) Immunity EN Power Line Harmonics EN ESD EN Radiated Immunity EN EFT EN Surge EN Low Frequency Common Immunity EN Voltage Dips and Sags ETS Switching Equipment CE Marking Meets European CE marking requirements Channelization Supported SONET/T-CARRIER Hierarchy PIC OC OC3 DS3 DS DS0 x ChOC48/ ChSTM6 4 x ChOC/ChSTM4 x ChOC/ChSTM4 0 x ChOC3/ChSTM 0 4 x ChDS3/E3 0 0 x ChT/ChE Optical Diagnostics and Monitoring (SFF-847 Rev 9.5) High Alarm Low Alarm High Warning Low Warning Temperature ±3 C ±3 C ±3 C ±3 C Supply Voltage ±3% ±3% ±3% ±3% TX Bias Current ±0% ±0% ±0% ±0% TX Output Power ±3 db ±3 db ±3 db ±3 db RX Recv Power ±3 db ±3 db ±3 db ±3 db Minimum CFEB/FPC 9 Requirements Platform Type- Type- Type-3 M0i/M7i Enhanced CFEB N/A N/A M40e M40e-FPC-EP M40e-FPC-EP N/A M0 M30 T30 T640/ T600 MX40/ MX480/ MX960 M0-FPC and associated M0-FEB M30-FPC-E, M30-FPC-E3 T30-FPC-E, T30-FPC-E T640-FPC-E, T640-FPC-E M0-FPC and associated M0-FEB M30-FPC-E, M30-FPC-E3 T30-FPC-E, T30-FPC-E T640-FPC-E, T640-FPC-E M0-FPC3 M30-FPC3-E3 N/A T640-FPC3-ES N/A N/A MX-FPC3 Juniper Networks Services and Support Juniper Networks is the leader in performance-enabling services that are designed to accelerate, extend, and optimize your high-performance network. Our services allow you to maximize operational efficiency while reducing costs and minimizing risk, achieving a faster time to value for your network. Juniper Networks ensures operational excellence by optimizing the network to maintain required levels of performance, reliability, and availability. For more details, please visit en/products-services. SDH/E-CARRIER Hierarchy PIC STM4 STM E3 E DS0 x ChOC48/ ChSTM6 4 x ChOC/ ChSTM x ChOC/ChSTM x ChOC3/ChSTM x ChDS3/E x ChT/ChE

6 Ordering Information Part numbers that begin with PE- are for deployment on M7i/ M0i routers; PB- part numbers are for installation in M40e, M0, M30, and T Series routers. Channelized PICs IQ-E Part Number* Description Type PB-4CHDS3-E3-IQE-BNC PE-4CHDS3-E3-IQE-BNC PB-CHOC-STM4-IQE-SFP PE-CHOCSTM4-IQE-SFP PB-CHOC3-STM-IQE-SFP PE-CHOC3-STM-IQE-SFP PB-0CHE-T-IQE-RJ48 PE-0CHE-T-IQE-RJ48 PB-4CHOC-STM4-IQE- SFP PB-CHOC48-STM6-IQE Non-Channelized PICs 4-port Channelized DS3/E3 -port Channelized OC/ STM4 - requires separate SFP optics -port Channelized OC3/ STM - requires separate SFP optics 0-port Channelized T/E 4-port Channelized OC/ STM4 - requires separate SFP optics -port Channelized OC48NC/STM6 - requires separate SFP optics IQ-E Part Number* Description Type PB-4DS3-E3-IQE-BNC PE-4DS3-E3-IQE-BNC PB-OC-STM4-IQE-SFP PE-OC-STM4-IQE-SFP PB-4OC3-STM-IQE-SFP PE-4OC3-STM-IQE-SFP 4-port DS3/E3 -port OC/STM4 - requires separate SFP optics 4-port OC3/STM - requires separate SFP optics PC-4OC48-STM6-IQE-SFP 4-port OC48/STM6 - requires separate optics 3 SFP Options IQ-E Part Number SFP-OC3-SR SFP-OC3-IR SFP-OC3-LR SFP-OC-SR SFP-OC-IR SFP-OC-LR SFP-OC-LR SFP-OC48-SR SFP-OC48-IR SFP-OC48-LR On appropriate platforms. Description OC3 SFP 30 nm km reach multimode OC3 SFP 30 nm 5 km reach OC3 SFP 30 nm 40 km reach OC SFP 30 nm km reach multimode OC SFP 30 nm 5 km reach OC SFP 30 nm 40 km reach OC SFP 50 nm 80 km reach single mode OC48 SFP 30 nm km reach multimode OC48 SFP 30 nm 5 km reach OC48 SFP 550 nm 80 km reach Type-3 4xOC48 PIC does not support queue level shaper. 3 Hierarchical scheduling capabilities not supported with the Type-3 PIC. 4 Type-3 4xOC48 PIC supports rate limit for any queue either strict of non-strict. 5 Type-3 4xOC48 PIC supports 4ms buffer which can be used for the 4DLCI where each DLCI is running.5 Gbps (one DLCI per OC48). 6 This is for channelized PICs only. For the non-channelized PICs, this is supported only at the port level. 7 Type-3 PIC 3 drop profiles are supported (4 drop profiles per queue). 8 Not supported on Type-3 4xOC48 PIC. 9 Compact Forwarding Engine Boards/Flexible PIC Concentrator. About Juniper Networks Juniper Networks is in the business of network innovation. From devices to data centers, from consumers to cloud providers, Juniper Networks delivers the software, silicon and systems that transform the experience and economics of networking. The company serves customers and partners worldwide. Additional information can be found at Corporate and Sales Headquarters Juniper Networks, Inc. 33 Innovation Way Sunnyvale, CA USA Phone: 888.JUNIPER ( ) or Fax: APAC and EMEA Headquarters Juniper Networks International B.V. Boeing Avenue 40 9 PZ Schiphol-Rijk Amsterdam, The Netherlands Phone: Fax: Copyright 04 Juniper Networks, Inc. All rights reserved. Juniper Networks, the Juniper Networks logo, Junos and QFabric are registered trademarks of Juniper Networks, Inc. in the United States and other countries. All other trademarks, service marks, registered marks, or registered service marks are the property of their respective owners. Juniper Networks assumes no responsibility for any inaccuracies in this document. Juniper Networks reserves the right to change, modify, transfer, or otherwise revise this publication without notice EN Dec 04