20. Daubachies, I. (1992), Ten Lectures on Wavelets, Philadelphia: Society for Industrial and Applied Mathematics (SIAM).

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1 BIBLIOGRAPHY 1. Acharya, T. and Chakrabarti, C. (2006), A survey on lifting-based discrete wavelet transform, Journal of VLSI Signal Processing, vol. 42, no. 3, pp Acharyya, A., Maharatna, K., Al-Hashimi, B.M., and Gunn, S. R. (2009), Memory reduction methodology for distributed arithmetic-based DWT/IDWT exploiting data symmetry, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 56, no. 4, pp Akansu, A.N. and Haddad, R.A. (1992), Multiresolution Signal Decomposition: Transform, Subbands and Wavelets, Academic Press, New York. 4. Alam, M., Rahman, C. A., Badawy, W. and Jullian, G. (2003), Efficient distributed arithmetic based DWT architectures for multimedia applications, in Proc. IEEE Workshop on System-on-chip for Real-Time Applications, pp Al-Haj, A.M. (2005), An FPGA-based parallel distributed arithmetic implementation of the 1-D discrete wavelet transform, Journal of Informatica, vol. 29, no. 2, pp Allred, D. J., Yoo, H., Krishnan, V., Huang, W. and Anderson, D. V. (2005), LMS adaptive filters using distributed arithmetic for high throughput, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 52, no.7, pp Andra, K., Chakrabarti, C. and Acharya, T. (2002), A VLSI architecture for lifting-based forward and inverse wavelet transform, IEEE Transactions on Signal Processing, vol. 50, no. 4, pp Barua, S., Carletta, J. E., Kotteri, K. A. and Bell, A. E. (2005), An efficient architecture for lifting-based two-dimensional discrete wavelet transform, Integration The VLSI Journal, vol. 38, no. 3, pp Beylkin, G., Coifman, R. and Rokhlin, V. (1992), Wavelet in Numerical Analysis in Wavelets and Their Applications, New York: Jones and Bartlett. 10. Cao, X., Xie, Q., Peng, C., Wang, Q., and Yu, D. (2006), An efficient VLSI implementation of distributed architecture for DWT, in Proc. IEEE Workshop on Multimedia Signal Processing, pp

2 11. Cao, P., Wang, C., Yang, J. and Shi. L. (2009), Area-efficient line-based twodimensional discrete wavelet transform architecture without data buffer, in Proc. IEEE International Conference on Multimedia and Expo, pp Chakrabarti, C. and Vishwanath, M. (1995), Efficient realization of the discrete and continuous wavelet transforms: from single chip implementations to mappings on SIMD array computers, IEEE Transactions on Signal Processing, vol. 43, no. 3, pp Chakrabarti, C. and Mumford, C. (1996), Efficient realizations of analysis and synthesis filters based on the 2-D discrete wavelet transform, in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), vol. 6, pp Chao, W., Zhilin, W., Peng, C. and Jie, L. (2007), "An efficient VLSI architecture for lifting-based discrete wavelet transform," in Proc. IEEE International Conference on Multimedia and Expo, pp Cheng, C.-C., Huang, C.-T., Tseng, P.-C., Pan, C.-H. and Chen, L.-G. (2005), Multiplelifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp Cheng, C.-C., Huang, C.-T., Cheng, C.-Y., Lian, C.-J. and Chen, L.-G. (2007), On-chip memory optimization scheme for VLSI implementation of line-based two dimensional discrete wavelet transform, IEEE Transactions on Circuits and Systems for Video Technology, vol. 17, no. 7, pp Cheng, C. and Parhi, K.K. (2008), High-speed VLSI implementation of 2-D discrete wavelet transform, IEEE Transactions on Signal Processing, vol. 56, no. 1, pp Chiper, D. F., Swamy, M. N. S., Ahmad, M. O., and Stouraitis, T. (2005), Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST, IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 52, no. 6, pp Chrysafis, C. and Ortega, A. (2000), Line-based, reduced memory, wavelet image compression, IEEE Transactions on Image Processing, vol. 9, no. 3, pp Daubachies, I. (1992), Ten Lectures on Wavelets, Philadelphia: Society for Industrial and Applied Mathematics (SIAM). 113

3 21. Daubechies, I. and Sweldens, W. (1998), Factoring wavelet transform into lifting steps, Journal of Fourier Analysis and Applications, vol. 4, no. 3, pp Dai, Q., Chen, X. and Lin, C. (2004), A novel VLSI architecture for multidimensional discrete wavelet transform, IEEE Transactions on Circuits and Systems for Video Technology, vol. 14, no. 8, pp Gao, Z.-R. and Xiong, C.-Y. (2005), An efficient line-based architecture for 2-D discrete wavelet transform, in Proc. IEEE International Conference on Communication Circuits and Systems, vol. 2, pp Grzesczak, A., Mandal, M.K. and Panchanathan, S. (1996), VLSI implementation of discrete wavelet transform, IEEE Transactions on Very Large Scale Integration Systems, vol. 4, no. 4, pp Guo, J.-I., Liu, C.-M., and Jen, C.-W. (1992), The efficient memory-based VLSI array design for DFT and DCT, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 10, pp Hartley, R.I. (1996), Subexpression sharing in filters using canonic sign digit multipliers, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 10, pp Huang, C.-T., Tseng, P.-C. and Chen, L.-G. (2002), "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform," in Proc. Asia-Pacific Conference on Circuits and Systems (APCCAS), vol. 1, pp Huang, C.-T., Tseng, P.-C. and Chen, L.-G. (2004a), Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform, IEEE Transactions on Signal Processing, vol. 52, no. 4, pp Huang, C.-T., Tseng, P.-C. and Chen, L.-G. (2004b), Memory analysis and architecture for two-dimensional discrete wavelet transform, in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), vol. 5, pp.(v) Huang, C.-T., Tseng, P.-C. and Chen, L.-G. (2005a), Analysis and VLSI architecture for 1-D and 2- D discrete wavelet transform, IEEE Transactions on Signal Processing, vol. 53, no. 4, pp

4 31. Huang, C.-T., Tseng, P.-C. and Chen, L.-G. (2005b), Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method, IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 7, pp Jain, R. and Panda, P.R. (2007), An efficient pipelined VLSI architecture for liftingbased 2-D discrete wavelet transform, in Proc. IEEE International Symposium on Circuits and Systems, pp Jiang, W. and Ortega, A. (2001), Lifting factorization-based discrete wavelet transform architecture design, IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 5, pp Jing, C. and Bin, H.Y. (2007), Efficient wavelet transform on FPGA using advanced distributed arithmetic, in Proc. International Conference on Electronic Measurement and Instruments (ICEMI), pp Kotteri, K.A., Barua, S., Bell, A.E. and Carletta, J.E. (2005) A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 52, no. 5, pp Kronland-Martinet, R., Morlet, J. and Grossman, A. (1987), Analysis of sound patterns through wavelet transform, International Journal of Pattern Recognition and Artificial Intelligence, vol. 1, no. 2, pp Kung, H.T. (1982), Why systolic architectures, IEEE Transactions on Computers, vol. 15, no. 1, pp Lai, Y.-K., Chen, L.-F. and Shih, Y.-C. (2009), A high-performance and memory efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform, IEEE Transactions on Consumer Electronics, vol. 55, no. 2, pp Lan, X., Zheng, N. and Liu, Y. (2005), Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform, IEEE Transactions on Consumer Electronics, vol. 51, no. 2, pp Lewis, A. S. and Knowles, G. (1991), VLSI architecture for 2-D Daubechies wavelet transform without multipliers, Electronics Letters, vol. 27, no. 2, pp

5 41. Lewis, A.S. and Knowles, G. (1992), Image compression using the 2-D wavelet transform, IEEE Transactions on Image Processing, vol. 1, no. 2, pp Li, W.-M., Hsia, C.-H. and Chiang, J.-S. (2009), Memory-efficient architecture of 2-D dual-mode discrete wavelet transform using lifting scheme for motion-jpeg 2000, in Proc. IEEE International Symposium on Circuit and Systems (ISCAS), pp Liao, H., Mandal, M. K. and Cockburn, B. F. (2004), Efficient architectures for 1-D and 2-D lifting-based wavelet transforms, IEEE Transactions on Signal Processing, vol. 52, no. 5, pp Limqueco, J. C. and Bayoumi, M. A. (1998), A VLSI architecture for separable 2-D discrete wavelet transforms, Journal of VLSI Signal Processing, vol. 18, no. 2, pp Longa, P., Miri, A., and Bolic, M. (2008), Modified distributed arithmetic based architecture for discrete wavelet transforms, Electronics Letters, vol. 44, no. 4, pp Louis, A.K., Maass, D. and Rieder, A. (1997), Wavelets: Theory and Applications, Wiley 47. Mahajan, A. and Mohanty, B.K. (2010a), Bit serial design for VLSI implementation of 1-D discrete wavelet transform using 9/7 filters based on distributed arithmetic, in Proc. CSI National Conference on Education and Research (ConfER 2010), JUET, Guna, pp Mahajan, A. and Mohanty, B.K. (2010b), Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic, in Proc. 10th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010), Kuala Lumpur, Malaysia, pp Mallat, S. G. (1989a), A theory for multiresolution signal decomposition: The wavelet representation, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 11, no. 7, pp Mallat, S.G. (1989b), Multifrequency channel decompositions of imagesand wavelet models, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 37, no. 12, pp

6 51. Marino, F. (2000), Efficient high-speed/low-power pipelined architecture for the direct 2-D discrete wavelet transform, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, no. 12, PP Martina, M., and Masera, G. (2006), Low-complexity, efficient 9/7 wavelet filters VLSI implementation, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 53, no. 11, pp Martina, M., and Masera, G. (2007), Multiplierless, folded 9/7-5/3 wavelet VLSI architecture, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 54, no. 9, pp Meher, P.K., Mohanty, B.K. and Patra, J.C. (2008a), Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 55, no. 2, pp Meher, P.K., Chandrasekaran, S. and Amira, A. (2008b), FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic, IEEE Transactions on Signal Processing, vol. 56, no. 7, pp Meyer, Y. (1993), Wavelets: Algorithms and Applications, Philadelphia: Society for Industrial and Applied Mathematics (SIAM). 57. Mohanty, B.K. and Meher, P.K. (2006), Systolic architecture for transposition-free VLSI implementation of 2-D DWT, in Proc. 10th IEEE International Conference on Communication Systems (ICCS 2006), pp Mohanty, B.K. and Meher, P.K. (2007), Pipelined architecture for high-speed implementation of multilevel lifting 2-D DWT using 9/7 filters, in Proc. IEEE International Symposium on Signals, Circuits and Systems (ISSCS2007), pp Mohanty, B. K., and Meher, P. K. (2009), Efficient multiplierless designs for 1-D DWT using 9/7 filters based on distributed arithmetic, in proc. IEEE international symposium on integrated circuits (ISIC-2009), pp Mohanty, B.K. and Meher, P. K. (2011a), Memory-efficient modular VLSI architecture for high-throughput and low-latency implementation of multilevel lifting 2-D DWT, IEEE Transactions on Signal Processing, vol. 59, no. 5, pp

7 61. Mohanty, B.K. and Meher, P. K. (2011b), Memory-efficient architecture for 3-D DWT using overlapped grouping of frames, IEEE Transactions on Signal Processing, vol. 59, no. 11, pp Mohanty, B.K., Mahajan, A. and Meher, P.K. (2012), Area and power-efficient architecture for high-throughput implementation of lifting 2-D DWT, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 59, no. 7, pp Mohanty, B.K. and Meher, P. K. (2013), Memory-efficient high-speed convolution-based generic structure for multilevel 2-D DWT, IEEE Transactions on Circuits and Systems for Video Technology, vol. 23, no. 2, pp Mohanty, B.K. and Mahajan, A. (2013a), Efficient-block-processing parallel architecture for multilevel lifting 2-D DWT, ASP Journal of Low Power Electronics, vol. 9, no. 1, pp Mohanty, B.K., and Mahajan, A. (2013b), Scheduling-scheme and parallel structure for multilevel lifting 2-D DWT without using frame-buffer, IET Circuits, Devices and Systems, doi: /iet-cds Pan, W., Shams, A., and Bayoumi, M. A. (1999), NEDA: A new distributed arithmetic architectures and its application to one dimensional discrete cosine transform, in Proc. IEEE Workshops on Signal processing Systems, pp Parhi, K. K. and Nishitani, T. (1993), VLSI architectures for discrete wavelet transforms, IEEE Transactions on Very Large Scale Integration Systems, vol. 1, no. 2, pp Rao, R.M. and Bopardikar, A.S. (1999), Wavelet Transforms: Introduction to Theory and Applications, Pearson Education. 69. Senhadji, L., Carrault, G. and Bellanguer, J. J. (1994), Interictal EEG spike detection: A new framework based on the wavelet transforms, in Proc. IEEE-SP International Symposium on Time-Frequency and Time-Scale Analysis, pp Seo, Y.-H. and Kim, D.-W. (2007), VLSI architecture of line-based lifting wavelet transform for motion JPEG2000, IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp

8 71. Skodars, A., Christopoulos, C., and Ebrahimi, T. (2001), The JPEG 2000 still image compression standard, IEEE Signal Processing Magazine, vol. 18, no. 5, pp Sodagar, I., Lee, H.-J., Hatrack, P., and Zhang, Y.-Q. (1999), Scalable wavelet coding for synthetic/natural hybrid images, IEEE Transactions on Circuits and Systems for Video Technology, vol. 9, no. 2, pp Stoksik, M.A., Lane, R.G. and Nguyen, D.T. (1994), Accurate synthesis of fractional Brownian motion using wavelets, Electronic Letters, vol. 30, no. 5, pp Sweldens, W. (1996), The lifting scheme: A custom-design construction of biorthogonal wavelets, Applied and Computational Harmonic Analysis, vol. 3, no. 2, pp Taubman, D. (2000), High performance scalable image compression with EBCOT, IEEE Transactions on Image Processing, vol. 9, no.7, pp Tian, X., Wei, J. and Tian, J. (2010), Memory-efficient architecture for fast two dimensional discrete wavelet transform, in Proc. IEEE International Conference on Computational Intelligence and Software Engineering (CiSE), pp Tian, X., Wu, L., Tan, Y.H., and Tian, J.W. (2011), Efficient multi-input/multi-output VLSI architecture for two-dimensional lifting-based discrete wavelet transform, IEEE Transactions on Computers, vol. 60, no. 8, pp Tseng, P.-C., Huang, C.-T. and Chen, L.-G. (2002), Generic RAM-based architecture for two dimensional discrete wavelet transform with line based method, in Proc. Asia- Pacific Conference on Circuits and Systems (APCCAS), vol. 1, pp Vetterli, M. and Kovacevic, J. (1995), Wavelets and Subband Coding, Prentice Hall PTR, Englewood Cliffs, New Jersey. 80. Vishwanath, M. (1994), The recursive pyramid algorithm for the discrete wavelet transform, IEEE Transactions on Signal Processing, vol. 42, no. 3, pp Vishwanath, M., Owens, R. M. and Irwin, M. J. (1995), VLSI architectures for the discrete wavelet transform, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal processing, vol. 42, no. 5, pp Week, M. and Bayoumi, M. (2003), Discrete wavelet transform: architectures, design and performance issues, Journal of VLSI Signal Processing, vol. 35, no. 2, pp

9 83. Weste, N.H.E. and Eshraghian, K. (1993), Principles of CMOS VLSI Design: A Systems Perspective, Addison- Wesley. 84. White, S. A. (1989), Applications of the distributed arithmetic to digital signal processing: A tutorial review, IEEE ASSP Magazine, vol. 6, no. 3, pp Wu, P.-C. and Chen, L.-G. (2001), An efficient architecture for two-dimensional discrete wavelet transform, IEEE Transactions on Circuits and Systems for Video Technology, vol. 11, no. 4, pp Wu, B.-F. and Lin, C.-F. (2005), A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec, IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 12, pp Xiong, C.-Y., Tian, J.-W. and Liu, J. (2005), Efficient parallel architecture for liftingbased two-dimensional discrete wavelet transform, in Proc. IEEE International Workshop on VLSI Design and Video Technology, pp Xiong, C.-Y., Tian, J.-W. and Liu, J. (2006a), Efficient high-speed/low-power line based architecture for two-dimensional discrete wavelet transform using lifting scheme, IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 2, pp Xiong, C.-Y., Tian, J.-W. and Liu, J. (2006b), A note on flipping structure: An efficient VLSI architecture for lifting-based discrete wavelet transform, IEEE Transactions on Signal Processing, vol. 54, no. 5, pp Xiong, C.-Y., Tian, J.-W. and Liu, J. (2007), Efficient architecture for two dimensional discrete wavelet transform using lifting scheme, IEEE Transactions on Image Processing, vol. 16, no. 3, pp Yu, C. and Chen, S.J. (1997), VLSI implementation of 2-D discrete wavelet transform for real-time video signal processing, IEEE Transactions on Consumer Electronics, vol. 43, no. 4, pp Zhang, W., Jiang, Z., Gao, Z. and Liu, Y. (2012), An efficient VLSI architectures for lifting-based discrete wavelet transform, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 59, no. 3, pp

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