Reconfigurable Architecture for VLSI 9/7-5/3 Wavelet Filter

Transcription

1 Reconfigurable Architecture for VSI 9/7-5/3 Wavelet Filter Tze-Yun Sung * Hsi-Chin Hsin ** * Departent of Microelectronics Engineering Chung Hua University 77, Sec., Wufu Road, Hsinchu City 3- TAIWAN bobsung@chu.edu.tw ** Departent of Coputer Science and Inforation Engineering National United University, ien-da, Miao-i, 36-3 TAIWAN hsin@nuu.edu.tw Abstract: - In this paper, the high-efficient and reconfigurable lined-based architectures for the 9/7-5/3 discrete wavelet transfor (DWT) based on lifting schee are proposed. The proposed parallel and pipelined architectures consist of a horizontal filter (HF) and a vertical filter (VF). The critical paths of the proposed architectures are reduced. Filter coefficients of the biorthogonal 9/7-5/3 wavelet low-pass filter are quantized before ipleentation in the high-speed coputation hardware In the proposed architectures, all ultiplications are perfored using less shifts and additions. The proposed reconfigurable architecture is % hardware utilization and ultra low-power. The proposed reconfigurable architectures have regular structure, siple control flow, high throughput and high scalability. Thus, they are very suitable for new-generation iage copression systes, such as PEG-. Key-Words: - Reconfigurable architecture, 9/7-5/3 discrete wavelet transfor (DWT), horizontal filter (HF), vertical filter (VF), lifting schee. Introduction In the field of digital iage processing, the PEG- standard uses the scalar wavelet transfor for iage copression []; hence, the two-diensional (-D) discrete wavelet transfor (DWT) and IDWT has recently been used as a powerful tool for iage coding/decoding systes. Two-diensional DWT/IDWT deands assive coputations, hence, it requires a parallel and pipelined architecture to perfor real-tie or on-line video and iage coding and decoding, and to ipleent high-efficiency application-specific integrated circuits (ASIC) or field prograable gate array (FPGA). At the kernel of the copression stage of the syste is the DWT. Swelden proposed using the biorthogonal 9/7 wavelet based on lifting schee for lossy copression []. The syetry of the biorthogonal 9/7 filters and the fact that they are alost orthogonal [] ake the good candidates for iage copression application. Gall and Tabatai proposed using the biorthogonal 5/3 wavelet based on lifting schee for lossless copression [3]. The goal of the The National Science Council of Taiwan, under Grant NSC98--E-6-37 supported this work. proposed architectures is to ebed the 5/3 DWT coputation into the 9/7 DWT coputation. The coefficients of the filter are quantized before hardware ipleentation; hence, the ultiplier can be replaced by liited quantity of shift registers and adders. Thus, the syste hardware is saved, and the syste throughput is iproved significantly. In this paper, we proposed a high-efficient architecture for the even and odd parts of -D DWT based on lifting schee. The advantages of the proposed architectures are % hardwareutilization, ultiplier-less, regular structure, siple control flow and high scalability. The reainder of the paper is organized as follows. Section presents the lifting-based -D discrete wavelet transfor algorith, and derives new atheatical forulas. In Section 3, the high-efficient and reconfigurable architecture for the lifting-based -D DWT are proposed. Finally, coparison of perforance between the proposed reconfigurable architecture and previous works is ade with conclusions given in section 4. ISSN: Issue 5, Volue 9, May

2 The ifting-based -D DWT Algorith Usually the ifting-based DWT requires less coputation copared to the convolution-based approach. However, the savings depend on the length of the filters. During the lifting ipleentation, no-extra eory buffer is required because of the in-place coputation feature of lifting. This is particularly suitable for the hardware ipleentation with liited available on-chip eory. Many papers proposed the algoriths and architectures of DWT [3]-[], but they require assive coputation. In 996, Sweldens proposed a new lifting-based DWT architecture, which requires half of hardware copared to the conventional approaches [].. The 9/7 -D DWT Algorith The 9/7 discrete wavelet transfor factoring into lifting schee is represented as []: ~ α( + z ) γ ( + z ) P9 / 7 = β( + z) () ζ δ ( + z) / ζ where α, β, γ and δ are the coefficients of lifting schee, and ζ and / ζ are scale noralization factors. The architecture based on lifting schee consists of splitting odule, two lifting odules and scaling odules. The architecture of 9/7 -D DWT based on lifting schee is shown in Figure. The 9/7 -D DWT is a ultilevel decoposition technique. According to the architecture of 9/7 -D DWT based on lifting schee, the architecture of odified 9/7 -D DWT based on lifting schee can be derived and shown in Figure.. The Modified 9/7 -D DWT Algorith According to equation (), the transfor atrix of the 9/7 DWT based on lifting schee is odified as ~ α( + z ) P( z) = β ( + z) γ ( + z ) ζ δ ( + z) / ζ / α ( + z ) / β = / α ( + z) / β / γ ( + z ) / δ αβγδζ / γ ( + z) / δ αβγδ/ ζ + z / αβ = / α + z + z / γδ αβγδζ / βγ + z αβγ / ζ + z B = A + z () + z D K C + z K where A = / α, B = /αβ, C =/ βγ, D =/γδ, K = αβγδζ,and K = αβγ / ζ..3 The 5/3 -D DWT Algorith The data flow of 5/3 -D DWT based on lifting schee is shown in Figure 3. The 5/3 -D DWT is a ultilevel decoposition technique; that decoposes into four subbands such as HH, H, H and. The data flow of 5/3 -D DWT based on lifting schee can be derived and shown in Figure 4. The 5/3 discrete wavelet transfor factoring into lifting schee is represented as []: ~ α ( + z ) P 5 / 3 = β ( + z ) (3) 3 The High-Efficient and Reconfigurable Architectures for 9/7 and 5/3 ifting-based -D DWT The proposed reconfigurable architecture for 5/3 and 9/7 lifting based -D DWT including horizontal filter (HF) and vertical filter (VF) is shown in Figure 5. In this reconfigurable architecture, the architecture of horizontal filter and the architecture of vertical filter are shown in Figure 6 and 7, respectively. The proposed reconfigurable architecture for odified horizontal filter (HF) consists of eleven delay units, seventeen ultiplexers and two processing eleents (PEs). The PE(A/B/E) perfors O for data output 5/3() and PE(C/D/F) perfors O for data output ISSN: Issue 5, Volue 9, May

3 9/7(). The architecture of PE(A/B/E) and the architecture of PE(C/D/F) are shown in Figure 8 and 9, respectively. The architecture of scaling noralization (SN) is shown in Figure. Filter coefficients of the biorthogonal 9/7 and 5/3 wavelet low-pass filter are quantized before ipleentation in the high-speed coputation hardware. In the proposed architecture, all ultiplications are perfored using shifts and additions after approxiating the coefficients as a Booth binary recoded forat (BBRF). The constant ultiplier shown in Figure consists of two carry-save-adders (CSA(4,)), a Carry ookahead Adder (CA), and six hardwire shifters and replaces conventional ultiplier ( ) in PE(A/B/E), PE(C/D/F) and SN. Figure shows architectures of line delays D, D, D and D3 in vertical filter. We handle borders by the syetric extension ethod []. Hence, the quality of reconstructed iages can be iproved. The proposed reconfigurable architectures for 9/7 and 5/3 DWT reduce the critical path [3]-[9]. In N N -D DWT, it requires N( ) + N ( ) coputation 3 4 cycles (addition operations) with N / 4 + 9N eories to perfor 9/7 -D DWT, where is nuber of levels. It requires 4 + N( ) + N ( ) coputation 3 4 cycles (addition operations) with N / N eories to perfor 5/3 -D DWT, where is nuber of levels. Both of two architectures are % hardware utilization [-]. 4 Conclusion Filter coefficients are quantized before ipleentation using the biorthogonal 9/7 and 5/3 wavelet. The hardware is cost-effective and the syste is high-speed. The proposed architecture in 9/7 DWT reduces power dissipation by copared with conventional architectures in -bit operand (low-power utilization). The proposed architecture in 5/3 DWT with 4-bit fixed point operations had been applied to 5 5 original iages ena is shown in Figures 3(a) and the reconstructed iages ena is shown in Figure 3(b), respectively. The PSNRs of the reconstructed iages ena is 3.554dB. Hence, the proposed reconfigurable architecture has been applied to iage copression with great satisfaction. In this paper, the high-efficient and low-power reconfigurable architecture for -D DWT has been proposed. The proposed reconfigurable architecture perfors copression in 4 (9 + N( ) + N ( )) T a coputation 3 4 tie for 9/7 DWT and 3 ( N( ) + N ( )) T a for 5/3 DWT, 3 4 where the tie unit (Ta is tie of addition operation). The critical paths are 3 Ta for 9/7 DWT and Ta for 5/3 DWT, and the output latency tie are 49 Ta for 9/7 DWT and T a for 5/3 DWT. Buffer sizes are N / 4 + 9N for 9/7 DWT and N / N for 5/3 DWT. The control coplexity is very siple. The coparisons between previous works [4] [8] and this work are shown in Table for 9/7 DWT and Table for 5/3 DWT [4] [9]. The advantages of the proposed reconfigurable architecture are % hardware utilization and ultra low-power. The architecture has regular structure, siple control flow, high throughput and high scalability. Thus, it is very suitable for new-generation iage copression systes, such as PEG-. The proposed reconfigurable DWT is a reusable IP, which can be ipleented in various processes and cobined with an efficient use of hardware resources for the trade-offs of perforance, area, and power consuption. References: [] ITU-T Recoendation T.8. PEG iage coding syste Part, ITU Std., uly. [] W. Sweldens, The lifting schee: A custo-design construction of biorthogonal wavelet, Applied and Coputational Haronic Analysis, vol. 3, 996, pp [3] D.. Gall, A. Tabiatai, Sub-band coding of digital iages using syetric short kernel filters and arithetic coding techniques, Proc. IEEE Int. Conf. Acoust., Speech, signal Process., 988, pp [4] G. Beylkin, R. Coifan, V. Rokhlin, Wavelet in nuerical analysis in Wavelets and their applications, New York: ones and Bartlett, 99. [5] A. N. Akansu, R. A. Haddad, Multiresolution signal decoposition: Transfor, subbands and Wavelets, New York: Acadeic, 99. [6] I. Sodagar, H.-. ee, P. Hatrack, Y.-Q. Zhang, Scalable wavelet coding for synthetic/natural hybrid iages, IEEE Trans. Circuits and ISSN: Issue 5, Volue 9, May

4 Systes for Video Technology, Vol. 9, Mar. 999, pp [7] D. Tauban, High perforance scalable iage copression with EBCOT, IEEE Trans. Iage Processing, Vol. 9,. pp [8] R. Kronland-Martinet,. Morlet, A. Grossan, Analysis of sound patterns through wavelet transfor, Int.. Pattern Recognit. Artif. Intell., Vol., No., 987, pp [9] M. A. Stoksik, R. G. ane, D. T. Nguyen, Accurate synthesis of fractional Brownian otion using wavelets, Electronic etters, Vol. 3, No. 5, Mar. 994, pp [] T. Y. Sung, Meory-efficient and high-perforance parallel-pipelined architectures for 5/3 forward and inverse discrete Wavelet transfor, WSEAS Transactions on Electronics, Volue 4, No., February 7, pp.3-4. [] K. C. B. Tan, T. Arslan, An ebedded extension algorith for the lifting based discrete wavelet transfor in PEG, IEEE International conference on acoustic, speech, and signal processing, Vol.4,, pp [] K. Parhi, T. Nishitani, VSI architectures for discrete wavelet transfors, IEEE Trans. VSI Systes, Vol., No., 993, pp. 9-. [3] I. Daubechies, W. Sweldens., Factoring wavelet transfors into lifting schees,.fourier Anal. Appl., Vol.4, 998, pp [4] K. Andra, C. Chakrabarti, T. Acharya, A VSI architecture for lifting-based forward and inverse wavelet transfor, IEEE Trans. on Signal Processing, Vol. 5,, pp [5] C. Xiong, S. Zheng,. Tian,. iu, The iproved lifting schee and novel reconfigurable VSI architecture for the 5/3 and 9/7 wavelet filters, 4 IEEE International Conference on Counications, Circuits and Systes, Vol., 4, pp [6] T.-Y. Sung, Y.-S. Shieh, A high-speed / ultra low-power architecture for -D discrete Wavelet transfor, 5 IEEE International Conference on Systes and Signals (ICSS-5), Kaohsiung, Taiwan, April 8-9, 5, pp [7] T.-Y. Sung, C.-W. Yu, Y.-S. Shieh, H.-C. Hsin, A high-efficient line-based architecture for -D lifting-based DWT using 9/7 Wavelet filters, 9th oint Conference on Inforation Sciences (CIS-6), Kaohsiung, Taiwan, Oct. 8-, 6, pp [8] B.-F. Wu, C.-F. in, A high-perforance and eory-efficient pipeline architecture for the 5/3 and 9/7 discrete Wavelet transfor of PEG- Codec, IEEE Trans. Circuits and Systes for Video Technology, Vol. 5, No., Dec. 5, pp [9]. S. Chiang, and C. H. Hsia, An efficient VSI architecture for -D DWT using lifting schee, IEEE International Conference on Systes and signals, April, 5, pp [] T.-Y. Sung, ow-power and highperforance -D DWT and IDWT architectures based on 4-tap Daubechies filters, 7th WSEAS International Conference on Multiedia Systes & Signal Processing, 7, pp [] M. A. Farahani, M. Eshghi, Ipleenting a new architecture of wavelet packet transfor on FPGA, 8th WSEAS international conference on Acoustics & usic: theory & applications, 7, pp [] T.-Y. Sung, Reconfigurable VSI architecture for FFT processor, WSEAS Transactions on Circuits and Systes, Vol. 8, No. 6, 9, pp ISSN: Issue 5, Volue 9, May

5 Table Coparison between previous works and this work (9/7 DWT architecture with single input, T : ultiplication tie, T a :addition tie and T d : latency delay ) Architecture Wu [8] 5 Andra [4] This work [Sung, Hsin, ] Perforance Meory Size(bytes): N / N 4 Coputation Cycle: ( + 6N( ) + N ( )) T 3 4 Border Handling: NO Hardware Utilization: % Meory Size(bytes): N 4 Coputation Cycle: Td + N ( ) T 3 4 Border Handling: NO Hardware Utilization: 5% Meory Size(bytes): N / 4 + 9N 4 Coputation Cycle: (9 + N( ) + N ( )) T 3 4 Border Handling: YES Hardware Utilization: % a Table Coparison between previous works and this work (5/3 DWT architecture with dual input, T : ultiplication tie and T a :addition tie) Architecture Chiang [9] 5 Andra [4] This work [Sung, Hsin, ] Perforance Meory Size(bytes): N / 4 + 5N Coputation Cycle: N T Border Handling: NO Hardware Utilization: % Meory Size(bytes): N / + 4N N Coputation Cycle: ( + N) T Border Handling: NO Hardware Utilization: % Meory Size(bytes): N / N 3 Coputation Cycle: ( N( ) + N ( )) T 3 4 Border Handling: YES Hardware Utilization: % a ISSN: Issue 5, Volue 9, May

6 Fig.. The architecture of 9/7 -D DWT based on lifting schee( P=α(+z), U=β(+z - ), P=γ(+z) and U=δ(+z - )) Fig.. The architecture of odified 9/7 -D DWT based on lifting schee Fig. 3. The data flow of 5/3 -D DWT based on lifting schee ISSN: Issue 5, Volue 9, May

7 Fig. 4. The data flow of 5/3 -D DWT based on lifting schee MEM SN 9/7:x(i,j) 5/3:x(i,j) 5/3:x(i,j+) HF Data out 5/3 () Data out 9/7 () VF Data out 5/3 () Data out 9/7 () Fig. 5. The proposed reconfigurable architecture for 5/3 and 9/7 -D DWT based on lifting schee ISSN: Issue 5, Volue 9, May

8 Input 9/7:x ( i,j) 5/3:x ( i,j) 5/3: x ( i,j+ ) S d S 53b S 97b S d S d PE( A / B / E ) O Data Out 5/3 () S 97b S 53b S d S d S 97b3 O PE( C /D / F ) Data Out 9/7 () S 97b4 Fig. 6 The architecture of horizontal filter (HF) in the proposed reconfigurable architecture ISSN: Issue 5, Volue 9, May

9 Input 53: (,n) 97:H (,n) (,n) D D3 D3 Input 53:H (,n) D3 D3 D3 S d3 S d S d S d S 53b3 S d3 S d3 S 97b5 Data Out 5/3 () PE(A/B/E) O 3 D D D S 97b6 S 53b4 S d4 S d4 S 97b7 Data Out 9/7 () SN PE(C /D /F) O 4 D output D D Fig. 7 The architecture of vertical filter (VF) in the proposed reconfigurable architecture S 97b8 A B S d3 er s + + PE(A/B/E) Fig. 8 The architecture of PE(A/B/E) in the proposed reconfigurable architecture ISSN: Issue 5, Volue 9, May

10 C D S d4 er 3 s + + PE(C /D /F) Fig. 9 The architecture of PE(C/D/F) in the proposed reconfigurable architecture K er K S q5/3 Input Data Out 5/3 () er K K er CSA K K K K 3 3 Data Out 9/7 () S q9/7 CSA CA Fig. The architecture of scaling noralization (SN) in the proposed reconfigurable architecture Fig. The constant ultiplier replaces conventional ultiplier ( ) in PE(A/B/E), PE(C/D/F) and SN ISSN: Issue 5, Volue 9, May

11 evel 3 evel evel evel 3 evel evel input input N/4 N/4 N/ (N/4)- N/4 N/ Sj Sj output output D D evel 3 evel evel evel 3 evel evel input (N/8)- N/8 N/4 input N/8 N/8 N/4 output output D D3 Fig. The architectures of line delays D, D, D and D3 in vertical filter (a) (b) Fig ena (a) Original iage (b) Reconstructed iage (9/7 DWT with 5-level) ISSN: Issue 5, Volue 9, May